2.1Quy trnh thit k d n trong ISE 10.

1 Quy trnh thit k to mt profect vit chng trnh trong ISE 10.1 ,v m phng chng trnh bng simulink. S dng ngn ng m t phn cng VHDL. ( y em s dng chip CPLD ca hng Xilinx v phn mm lp trnh km theo cho hng ny l ISE, nu s dng chip CPLD ca Altera th l phn mm Quatuasr) + Bc 1. M phn mm c tn l Xilinx ISE 10.1, giao din ban u ca phn mm nh di y:

Hnh 3.7 : Giao din khi ng + Bc 2: Bt u khi to 1 d n mi .Vo file -> new project

Hnh 3.8 khi to d n mi + Bc 3: Trong mc new project Wizard bn ghi tn cho Project (TopTxDisp) v ni lu tr d n ca bn

Hnh 3.9 giao din lu tn project v ni lu tr

+ Bc 4: Chn cc thng s board np cho ph hp vi loi board nhn

Next.

Hnh 3.10 : giao din ci t cc thng s ph hp + Bc 5: Khi ta trn mn hnh ta s thy giao din sau, trong mc Sources bn tri bn chon th v d, kch chut phi v chon New source

Hnh 3.11: giao din to 1 newsoure

+ Bc 6: Chn kiu to linh kin l ngn ng lp trnh VHDL chn VHDL

Module nhp tn cho thc th khung File Name (v d l DC_buoc) chn Next

Hnh 3.12 Chn cc thng s lp trnh

+ Bc 7: Trong mc tip theo s hin ra bng cc bn khai bo u vo v u ra cho d n nu nh cc bn bit trc cc u vo v u ra th ghi vo, nu cha bit th cc bn b qua (vo trong chng trinh ri khai bo sau).V d trong chng trnh c s dng cc tn hiu xung clk, rst, chieu , start lm u vo x l c khai bo di dng bit v in, C u ra k hiu l ra c khai bo di dng vector t 0-3 v out. Sau n nex

Hnh 3.13: Khai bo u vo v ra ca d n + Bc 8: Cui cng ta to xong mt project cho d n ca mnh vi ngn ng s dng l VHDL,file mc cha d n l vidu, tn ca d n l DC_buoc. Giao din ca project chnh vit chng trnh nh hnh sau:

Hnh 3.14: giao din vit chng trnh B9 : Sau khi lp trnh xong th chn Save v kim tra li bng cch n Double vo Check Syntax, nu b li hy kch vo ch bo li sa li, v check Syntax li.

Hnh 3.15 kim tra li B10 : Nu c php ng th khng bo li. B11 : Khi khng cn li na, chn mc Sythesize Right Click chn Run tng hp linh kin v bo thnh cng.

Hnh 3.16: Giao din chnh trong lp trnh v Chy tng hp.

Hnh 3.17 : Giao din chnh lp trnh v bo chy tng hp thnh cng. 5

2.2Cch m phng mt le VHDL trong Xilinx ISE Bc 1:Sau khi bo chy tng hp thnh cng, bn mc soure for bn tri kch chn Behavioral Simulation vo mc m phng.

Hnh 3.18 la chon mc m phng Bc 2: cy th mc bn tri kch chut phi chn New soure

Hnh 3.19 To file m phng Bc 3: Tip theo cc bn chn Test bench waveform v chn ng dn, t tn cho th mc m phng sau n Next

Hnh 3.20 t tn v ng dn cho file m phng Bc 4: mc tip theo chn thng s m phng. sau n Next

Hnh 3.21 Chn thng s m phng Bc 5: Ci cc ng tn hiu u vo theo cc yu cu ca phn lp trnh

Hnh 3.22 Ci cc ng tn hiu m phng Bc 6: Lu chng trnh li sau n Run chy chng trnh m phng

Hnh 3.23 chy file m phng Bc 7:Khi m phng ta s c dng xung nh sau:

Hnh 3.24 SPWM out put

2.3 Cc bc np chng trnh vo board thc tp Bc 1: : Trong Tab Process chn mc Users Constraints Assign Package Pin : gn chn linh kin ln trn Boards; s xut hin cc thng bo, bn chn Yes ng to file DC_buoc.ucf.

Hnh 3.25 : Thng bo chn to file ch nh chn. B13 : Xut hin giao din ch nh chn trn Board, nhp tn cc chn tng ng vi chc nng trn Board.

Hnh 3.26 : Giao din ch nh chn. B14 : Chn Save, xut hin bng chn nh sau, n OK, ng giao din gn chn li.

Hnh 3.27 : Thng bo chn lu file ch nh chn

Bc 2: Cu hnh li cp np data nh sau :

Hnh 3.28 : Giao din thc hin chn loi cp truyn data v chn cc thng s B18 : to file lp trnh , trong Tab Process chn Configure Device (iMPACT) right click Run

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Hnh 3.29 : Thc hin chy giao din to file SPWM.bit

B19 : Xut hin giao din sau chn Finish

Hnh 3.30 : Giao din m u to file SPWM.bit B20 : Chn file : SPWM.bit n Open

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Hnh 3.31 : Thng bo chn file np chng trnh. B23 : Nu khng c li , bo np chng trnh thnh cng.

Hnh 3.32 : Thng bo np thnh cng.

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