8051 I/O and 8255

Class 7 EE4380 Fall 2002

Pari vallal Kannan

Center for Integrated Circuits and Systems University of Texas at Dallas

Why I/O Ports

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Controllers need to get external inputs and produce external outputs

I/O ports serve the purpose

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8051 has 4 built-in I/O ports Too many ports increase pin-count and device cost. Too few makes it inadequate for complex control needs Generally, Ports are scarce and Port usage/allotment is an engineering decision
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8051 I/O Ports Internal Structure

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32 pins are allotted for 4 eight bit I/O ports

Vcc PORT LATCH D Q P1.X Write CLK QB M1 Internal Load Pin P1.X

P0, P1, P2, P3

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At power-on all are output ports by default To configure any port for input, write all 1s (0xFF) to the port

READ LATCH INTERNAL BUS READ PIN

Q=1, QB=0, M1=OFF, Read_Pin asserted by read instruction

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8051 I/O Ports (contd.)

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Ports can be read and written to like normal registers

mov A, #55H mov P0, A mov P1, A mov P2, #0AAH xlr P1, #0FFH mov P0, #0FFH mov A, P0 ; can use A ; write A to P0 ; can use immediate mode ; read-modify-write (ex-or) ; configure P0 for input ; read from P0

Ports can be bit manipulated (single bit addressable) using cpl and setb instructions
cpl P1.2 setb P1.3 clr P0.0 ; complement bit 2 of Port1 ; set bit 3 for Port1 to 1 ; clear bit 0 of Port0

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8051 I/O Ports Pin Muxing

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Port pins are muxed with other signals

P0 : Also carry A0:A7 and D0:D7 P1 : dedicated P2 : Also carry A8:A15 P3 : Also carry serial I/O (TxD, RxD), Timer inputs (T0, T1), external interrupts (INT0, INT1) and read write signals (RD, WR)

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For 8051 or DS5000, with no external memory, P0, P1 and P2 are available. For 8031, only P2 is available To increase the number of ports, use a Parallel port interface chip like 8255

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8051 I/O Ports : Hardware Specs

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P0 is open drain.

Has to be pulled high by external 10K resistors. Not needed if P0 is used for address lines

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P1, P2, P3 have internal pull-ups Port fan-out (number of devices it can drive) is limited.

Use buffers (74LS244, 74LS245, etc) to increase drive. P1, P2, P3 can drive up to 4 LS-TTL inputs P0 fan-out is dependant on the pull-up resistor value, limited by the max current it can sink on the output stage.

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8051 I/O Ports : Input Quirks

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Port read instructions either

Read from the 8051 pins (voltage levels on the pins) Read from an internal latch on the ports
Write

Vcc PORT LATCH D P1.X CLK QB M1 Q Internal Load Pin P1.X

Writing 1 to the latch

Q=1, QB=0 M1 off P1.x is available at tristate buffer Q=0, QB=1 M1 ON Input always gets 0 Can damage the port (M1) if P1.x is Vcc Use 10K resistance between switch on P1.x and Vcc Or use a SPST switch connected to GND

Writing 0 to the latch

READ LATCH INTERNAL BUS READ PIN

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Input Quirks (contd.)

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Instructions that read the pins (READ_PIN is asserted)

mov A, Px jnb Px.y jb Px.y mov C, Px.y

Instructions that read the latch (READ_LATCH is asserted)

They read the last output value and not the value on the pins
[anl, orl, xrl] Px [jbc, djnz] Px.y, target [cpl, clr, setb] Px.y [inc, dec] Px

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8051 - Switch On IO Ports

Vcc +5V 10K

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Port Pin

Case-1:

Port Pin

1. Good Internal Pullup

Gives a logic 0 on switch close Current is 0.5ma on switch close Gives a logic 1 on switch close High current on switch close Can damage port if 0 is output

GND

GND

Case-2:

Vcc +5V

Vcc +5V

Port Pin

Port Pin

Case-3:

2. Poor

470

3. Poor

GND

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DIP Switches on IO port

Vcc +5 V 10K ResPack

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8051
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

GND

SW-DIP8

DIP switches usually have 8 switches Use the case-1 from previous page Can use a Resistor Pack, instead of discrete resistors

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LED on IO Port
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Vcc +5V Vcc +5V

470

Port Pin

Port Pin

Port Pin

1. Good

2. Poor

3. Poor

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GND

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Vcc +5 V 8051
CA a

Vcc +5 V 8051
CA

Try to use current sinking Case-1 LED is ON for an output of zero Most LEDs drop 1.7 to 2.5 volts and need about 10ma Current is (5-2)/470 Case-2 Too much current Failure of Port or LED Case-3 Not enough drive (1ma) LED too dim

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7

330

b c d e f g dp

Seven Segment LEDs

330 7seg LED - Common Anode

7seg LED - Common Anode

Common Anode/ Cathode CA preferred Case-1 may have LEDs of different brightness

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8051 Interfacing with the 8255

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8255 - Widely used I/O chip

40 pins Provides 3 eight bit ports PA, PB and PC Port PC can be used as two 4 bit ports PCL and PCU Ports have handshaking ability Two address lines A0,A1 and a Chip select CS
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Address space of 4 bytes 00b selects Port A 01b selects Port B 10b selects Port C 11b selects a control register

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8255 Functional Diagram

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CS is used to interface with 8051 If CS is generated from lets say Address lines A15:A12 as follows, A15:A12 = 1000 Base address of 8255 is

D7-D0

PA

RD

8 2 5 5

PB

WR A0 A1

PC

1000 xxxx xxxx xx00b 8000H PA = 8000H PB = 8001H PC = 8002H CR = 8003H

Address of the registers

CS RESET

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8255 Operating Modes

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Mode 0 : Simple I/O

Any of A, B, CL and CU can be programmed as input or output A and B can be used for I/O C provides the handshake signals A is bi-directional with C providing handshake signals B is simple I/O (mode-0) or handshake I/O (mode-1) C alone is available for bit mode access

Mode 1: I/O with Handshake

Mode 2: Bi-directional with handshake

BSR (Bit Set Reset) Mode

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8255 Configuration
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Configured by writing a control-word in CR register CR definition

D7 : 1I/O mode, 0BSR D6,D5 : Mode selection for A and CU l 00Mode0, 01Mode1, 1xMode2 D4 : Port A control l 1A input, 0 A output D3 : Port CU control l 1CU input, 0CU output D2 : Port B Mode selection l 0B is in mode 0, 1B is in mode 1 D1 : Port B control l 1B input, 0B output D0 : Port CL control l 1CL input, 0CL output

Refer to 8255 datasheet for additional options

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8255 Usage: Simple Example

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8255 memory mapped to 8051 at address 8000H base

PA = 8000H, PB = 8001H, PC = 8002H, CR = 8003H CR : 1000 0000b = 80H

test: mov A, #80H mov DPTR, #8003H movx @DPTR, A mov A, #55h mov DPTR, #8000H movx @DPTR, A inc DPTR movx @DPTR, A inc DPTR movx @DPTR, A cpl A acall MY_DELAY sjmp repeat ; control word ; address of CR ; write control word ; will try to write 55 and AA alternatively ; address of PA ; write 55H to PA ; now DPTR points to PB ; write 55H to PB ; now DPTR points to PC ; write 55H to PC ; toggle A (55AA, AA 55) ; small delay subroutine ; for (1)
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Control word for all ports as outputs in mode0

Code snippet

repeat:

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Next Class
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Interfacing a keypad Interfacing a character LCD Scanned LED displays

17-Sep-02

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