1

TRNG I HC BCH KHOA H NI

KHOA IN T - VIN THNG




N
TT NGHIP I HC



ti:
XY DNG H THNG THU PHT TRN
NN DSP S DNG K THUT OFDM

Sinh vin thc hin: L NH NY
Lp T12 - K48
Ging vin hng dn: TS. NGUYN VN C



H Ni, 6-2008
2
B GIO DC V O TO

CNG HA X HI CH NGHA VIT NAM
TRNG I HC BCH KHOA H NI
--------------------------------------------------
c lp - T do - Hnh phc
---------------------------------

NHIM V N TT NGHIP

H v tn sinh vin: L nh Ny.... S hiu sinh vin: 20032445
Kho: 48.Khoa: in t - Vin thng Ngnh: .........
1. u n:
..
.....
2. Cc s liu v d liu ban u:
......
.....
.
3. Ni dung cc phn thuyt minh v tnh ton:
...
...
...

4. Cc bn v, th ( ghi r cc loi v kch thc bn v ):
...
...
.
5. H tn ging vin hng dn: ..
6. Ngy giao nhim v n: .
7. Ngy hon thnh n: ..
Ngy thng nm
Ch nhim B mn Ging vin hng dn





Sinh vin hon thnh v np n tt nghip ngy thng nm
Cn b phn bin
3
B GIO DC V O TO
TRNG I HC BCH KHOA H NI
---------------------------------------------------

BN NHN XT N TT NGHIP

H v tn sinh vin: L nh Ny............................................................ S hiu sinh vin: 20032445.............
Ngnh: .................................................................................................. Kho: 48 ....................................................
Ging vin hng dn: TS. Nguyn Vn c
Cn b phn bin: .......................................................................................................................................
1. Ni dung thit k tt nghip:
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..............................................................................

2. Nhn xt ca cn b phn bin:
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
..................................................................................................................................................................................................................................................
........................................................................................

Ngy thng nm
Cn b phn bin
( K, ghi r h v tn )



4
LI NI U


Ti xin chn thnh cm n thy gio Tin S Nguyn Vn c v cng
ng thi l gio vin hng dn ti, ngi lun tn tnh ch bo, dy d v mt
chuyn mn, ng vin khch l v mt tinh thn cho ti hon thnh n ny.
Ti cng mun ni li cm n ti b m, anh ch em v nhng ngi thn ca
ti. Nhng ngi lun theo st, ng h, ng vin ti trong qu trnh hc tp
cng nh lm n tt nghip ti trng i hc Bch Khoa H Ni.
Ti rt n lc hon thnh n ny. Tuy nhin, do thi gian gp rt
v kh nng c hn nn chc chn cn nhiu hn ch v thiu st. Ti rt mong
nhn c s ng gp kin ca qu thy c v bn b.

Xin chn thnh cm n.


H Ni, ngy 01 thng 06 nm 2008













5
TM TT


Trong n ny em tm hiu l thuyt ca cng ngh OFDM, cc h
thng ng dng k thut ny, cc k thut iu ch s, thu pht v tuyn, ng
dng ca vi x l tn hiu s, cng vi vic s dng phn mm CCS ( Code
composer Studio) xy dng mt h thng vin thng s dng cng ngh
OFDM trong vic thu pht d liu s.
Vi quy m v thi gian thc hin ti, kt qu ca n t c
mc chy thnh cng trong vic truyn thng gia cc DSK6416 TI, tn hiu t
mt DSK c pht ra ng line output v mt DSK khc nhn qua ng
line input. Cc chng trnh cng thnh cng trong vic truyn d liu gia
my tnh v DSK. y l mt hng nghin cu c th trin khai thc t v a
vo sn xut sn phm thu pht d liu khng dy.



ABSTRACT

In my thesis, I have learnd about theory of OFDM technique, the systems
using this technique, digital modutaion techniques, radio frequency, digital signal
processing, using CCS ( Code composer Studio ) to design an OFDM system in
wich we can transmit and receive digital data.
The result of this thesis is complete the OFDM system with out
communication channels, transmit data from a computer or the line in of
DSK6416, receive data through the line out of DSK or store in computer. The
next step, we can intergrate the radio frequency, the estimation block, the
equalization block to the full system.


6
MC LC

LI NI U .................................................................................................... 4
TM TT ........................................................................................................... 5
MC LC .......................................................................................................... 6
DANH MC HNH V ...................................................................................... 9
DANH MC BNG BIU ............................................................................... 10
CC T VIT TT ......................................................................................... 11
M U .......................................................................................................... 13
Chng 1 : H thng OFDM v qu trnh x l tn hiu .................................... 14
1.1 Gii thiu v k thut ofdm. .................................................................... 14
1.1.1 Gii thiu ......................................................................................... 14
1.1.2 Lch s pht trin. ............................................................................. 15
1.1.3 Cc u v nhc im ...................................................................... 15
1.2 Phng php iu ch v gii iu ch OFDM ........................................ 16
1.2.1 Khi nim v s trc giao ca hai tn hiu ........................................ 17
1.2.2 iu ch OFDM ............................................................................... 17
1.2.3 Gii iu ch ODFM ........................................................................ 20
1.3 H thng v tuyn s dng k thut OFDM ............................................ 23
1.3.1 Khong bo v ................................................................................. 24
1.3.2 c lng knh truyn ..................................................................... 26
1.3.3 ng b ........................................................................................... 30
1.3.4 Phng php iu ch v gii iu ch QAM ................................... 32
1.3.5 V d mch iu ch QAM ............................................................... 38
1.3.6 nh hng s lng sng mang con v khong thi gian bo v ...... 39
1.4 Kt lun ................................................................................................... 41
Chng 2 Mt s h thng truyn dn s dng k thut OFDM ........................ 42
2.1 Gii thiu ................................................................................................ 42
2.2 H thng DRM ........................................................................................ 42
2.3 H thng HiperLAN (IEEE802.11a) ........................................................ 44
2.4 H thng Wimax (IEEE802.16a,e) .......................................................... 45
2.5 Kt lun ................................................................................................... 47
CHNG 3: X L TN HIU TRN DSP .................................................... 48
3.1 Gii thiu ................................................................................................ 48
3.2 TMS320C6416 DSK ............................................................................... 48
3.2.1 Tng quan v phn cng .................................................................. 48
3.2.2 Khi x l trung tm TMS320C6416 ............................................... 50
3.2.3 B nh.............................................................................................. 50
3.2.4 AIC23 .............................................................................................. 52
3.2.5 CPLD ............................................................................................... 53
3.2.6 Cc m rng (daughter card) ............................................................ 53
3.2.7 Cc yu cu to mt chng trnh cho DSK vi CCS .................. 54
3.3 Kt lun ................................................................................................... 55
Chng 4: Bt u vi CCS .............................................................................. 56
7
4.1 Gii thiu ................................................................................................ 56
4.2 Code composer Studio Tutorial ............................................................... 56
4.3 Chu trnh xy dng v pht trin sn phm vi CCS................................ 56
4.4 Cu hnh h thng ( Creating a system configuration ) ............................ 56
4.5 Qun l cc thnh phn ............................................................................ 59
4.6 Kt lun ................................................................................................... 59
Chng 5: Cng c qun l v bin dch CCS .................................................... 60
5.1 Gii thiu ................................................................................................ 60
5.2 Khi to project mi: ............................................................................... 60
5.3 Xy dng v chy chng trnh: .............................................................. 61
5.4 La chn cu hnh hot ng Project: ...................................................... 64
5.5 Thay i cu hnh hot ng ca project .................................................. 64
5.6 Add cu hnh hot ng mi cho project ................................................. 64
5.7 Thay i tn s cho DSK. ........................................................................ 65
5.8 im tm dng chng trnh khi chy (Breakpoint): ............................... 65
5.9 im thm d ( Probe Point) ................................................................... 66
5.10 Ca s quan st hot ng ca chng trnh ( Watch Window ) ............ 68
5.11 Kt lun ................................................................................................. 69
Chng 6. Bt u CCS vi mt s ng dng n gin ..................................... 70
6.1 Gii thiu ................................................................................................ 70
6.2 Chng trnh Led .................................................................................... 70
6.2.1 M t v chng trnh led.c .............................................................. 74
6.2.2 Thay i chng trnh led. ............................................................... 74
6.3 Chng trnh hello.pjt ............................................................................. 75
6.4 V d vi chng trnh Maxminmath ....................................................... 76
6.5 Chng trnh SineWave .......................................................................... 78
6.6 Kt lun ................................................................................................... 83
Chng 7 DSP/BIOS ..................................................................................... 83
7.1 Gii thiu ................................................................................................ 83
7.2 Cc thnh phn ca DSP/BIOS ................................................................ 84
7.2.1 DSP/BIOS API ................................................................................ 84
7.2.2 DSP/BIOS Configuration ................................................................. 85
7.2.3 DSP/BIOS Analysis Tools ................................................................ 86
7.3 Mt s v d ............................................................................................ 88
7.3.1 V d 1 Hellobios.pjt ....................................................................... 88
7.3.2 V d 2 Ledprd.pjt ............................................................................ 92
7.3.3 Chng trnh x l tn hiu volume thc hin bng DSP ................... 94
7.4 Kt lun ................................................................................................... 96
Chng 8 K thut truyn thng........................................................................ 97
8.1 Gii thiu ................................................................................................ 97
8.2 iu phi truyn thng vi b m Ping pong ......................................... 97
8.3 S dng lin kt EDMA ( Linked EDMA transfers ) ............................... 97
8.4 c im ca lung d liu truyn: ......................................................... 98
8.5 EDMA kt hp vi McBSP : ................................................................... 99
8.6 Hot ng ca chng trnh: ................................................................. 100
8.7 Cu hnh EDMA ( EDMA configuration manager):............................... 100
8
8.7.1 Thm i tng cu hnh EDMA: .................................................. 100
8.7.2 nh dng trng a ch ( Specifying Address Formats) ............... 101
8.7.3 McBSP handle (DRR) or (DXR): ................................................... 106
8.7.4 S khung truyn v ch s khung ( Transfer Count and Index Setting )
................................................................................................................ 108
8.7.5 Thit lp s khung truyn s dng file header (Transfer Count
Register Setting using the Users Header File) ........................................ 109
8.7.6 Thit lp a ch lin kt ( Link address setting).............................. 110
8.7.7 Thit lp bng Table Number: ........................................................ 111
8.7.8 Cu hnh EDMA bng cc lnh trong file ngun. ........................... 113
8.8 McBSP ( Multichannel Buffered Serial Port ) ........................................ 115
8.9 Cu hnh cho khi Codec AIC23 ........................................................... 120
8.10 Mt s v d ........................................................................................ 121
8.10.1 Tone.pjt ........................................................................................ 121
8.10.2 Dsp_app ....................................................................................... 122
8.11 Kt lun ............................................................................................... 125
Chng 9 Truyn thng gia host v target ..................................................... 126
RTDX (Real-Time Data Exchange) ................................................................. 126
9.1 Gii thiu .............................................................................................. 126
9.2 Chng trnh ng dng trn target (Target Application) ........................ 126
9.3 Chng trnh ng dng trn host (Host Application basics) ................... 130
9.4 Pht trin ng dng vi VB ................................................................... 133
9.4.1 Phn 1 ............................................................................................ 134
9.4.2 Phn 2 ............................................................................................ 135
9.4.3 Phn 3 ............................................................................................ 139
9.4.4 Phn 4 ............................................................................................ 140
9.4.5 Kt lun .............................................................................................. 140
TI LIU THAM KHO ............................................................................... 141
Ph lc 1 ......................................................................................................... 142
Ph lc 2 ......................................................................................................... 145
Ph lc 3 ......................................................................................................... 148
Ph lc 4 ......................................................................................................... 150
Ph lc 5 ......................................................................................................... 152
Ph lc 6 ......................................................................................................... 153
Ph lc 7 ......................................................................................................... 157
Ph lc 8 ......................................................................................................... 164
Ph lc 9 ......................................................................................................... 168




9
DANH MC HNH V

Hnh 1.1 Biu din ph ca cc tn hiu OFDM18
Hnh 1.2 S b iu ch OFDM .......19
Hnh 1.3 M hnh mt knh truyn n gin .20
Hnh 1.4 S b gii iu ch OFDM.21
Hnh 1.5 M hnh tng quan h thng OFDM . ....23
Hnh 1.6 Khong bo v c cng vo k t OFDM . 25
Hnh 1.7 Tri tr nh hn khong bo v s khng gy ra ISI v ICI . 25
Hnh 1.8 S khi ca khi thu OFDM dng c lng knh....26
Hnh 1.9 S khi c lng knh da trn pilot....27
Hnh 1.10 S khi b iu khin QAM..33
Hnh 1.11 Cc dng biu din 4 QAM.34
Hnh 1.12 Xung c s dng ch nht..35
Hnh 1.13 B iu ch I/Q...36
Hnh 1.14 S khi b gii iu ch QAM..36
Hnh 1.15 B gii iu ch I/Q....37
Hnh 1.16 iu ch v gii iu ch QAM-16....39
Hnh 1.17 QAM-16..39
Hnh 2.1 Mi trng truyn sng ca h thng DRM.43
Hnh 2.2 S khi ca h thng DRM..44
Hnh 2.3 M hnh truyn thng ca Wimax.....46
Hnh 3.1 Hnh nh bo mch TMS320C6416 DSK...48
Hnh 3.2 S khi ca bo mch.....49
Hnh 3.3 Phn vng b nh ca C6416....51
Hnh 3.4 B chuyn i s - tng t AIC23...52
Hnh 4.1 Chu trnh xy dng v pht trin sn phm vi CCS....56
Hinh 9.1 Dng d liu gia RTDX host v target......125


10
DANH MC BNG BIU


Bng 7.1 Cc module trong API c s dng trong chng trnh..84






















11
CC T VIT TT

ADSL Asymmetric Digital Subcriber Line
API Application Programming Interface
AWGN Additive White Gaussian Noise
BER Bit-Error-Rate
BOM Bill of Materials
BS Base Station
BSL Board Support Library
BTS Base Transceiver Station
CCS Code Composer Studio
CSL Chip Support Library
CMOS Complementary Metal Oxide Semiconductor
CODEC Coder-Decoder
CPLD Complex Programble Logic Device
CPU Central Processing Unit
DAB Digital Audio Broadcasting
DARAM Dual Access Random Access Memory
DIP Dual In-line Package
DMA Direct Memory Access
DRM Digital Radio Mondiable
DSK DSP Starter Kit
DSP Digital Signal Processor
EMIF External Memory Interface
FFT Fast Fourier Transform
HiperLan/2 High Performal Local Area NetWork Type 2
HPI Host Port Interface
IDE Integrated Development Enviroment
12
IDFFT Inverse Fast Fourier Transform
IEEE Institute of Electrical and Electronic Engineers
ISI Intersymbol Interface
IQ Inphase-Quaderature
J TAG J oint Test Action Group
LED Light Emitting Diode
McBSP Mutil-Channel Buffered Sirial Port
MHz Megahertz
NMI Non-Maskable Interrupt
OFDM Orthoganal Frequency Division Multiplexing
OS Operating System
PC Personal Computer
POST Power On Self Test
PLL Phase Locked Loop
PQFP Plastic Quad Flat Pack
QAM Quadrature Amplitude Modulation
RF Radio Frequency
ROM Read-Only Memory
SDI Spectrum Digital Incorporated
SARAM Single Access Random Access Memory
SRAM Static Random Access Memory
SDRAM Synchronous Dynamic Random Access Memory
TI Texas Intruments
TTL Transistor-Transistor Logic




13

M U

Thng tin v tuyn l lnh vc ang ni bt v pht trin nhanh chng trong
nhng nm gn y. Tc cao cho in thoi di dng, Lan khng dy, s pht
trin theo hm m ca Internet i hi phi c mt phng php mi t
c mng khng dy dung lng cao. OFDM K thut a sng mang phn
chia theo tn s trc giao vi nhng im ni bt nh s dng ph tn hn hiu
qu, truyn tc cao, c kh nng chng nhiuha hn s l mt cha kha
k thut cho cc ng dng v tuyn trong tng lai gn.
Quyn n ny ch yu tm hiu v thit k mt h thng s dng cng
ngh OFDM trn DSP ca TI, thc hin truyn dn trn h thng xy dng.
Ni dung c chia thnh cc phn sau:

Chng 1: gii thiu tng quan v cng ngh OFDM.
Chng 2: tm hiu mt s ng dng ca cng ngh OFDM
Chng 3: tm hiu kin trc ca dsk TMS320C6416 ca TI
Chng 4: hng dn cch bt u lm vic vi CCS
Chng 5: trnh by cc cng c xy dng, qun l, v bin dch
chng trnh ca CCS.
Chng 6: lm vic vi CCS thng qua mt s v d.
Chng 7: tm hiu vDSP/BIOS v cch xy dng mt s chng
trnh n gin.
Chng 8: tm hiu v k thut truyn thng gia cc card DSP.
Chng 9: tm hiu v xy dng chng trnh truyn thng gia host
v target.



14
Chng 1 : H thng OFDM v qu trnh x l tn hiu
1.1 Gii thiu v k thut ofdm.
1.1.1 Gii thiu
a phng tin (multimedia) l cng ngh hiu qu c s dng trong
nhiu lnh vc khc nhau nh tnh ton, truyn thng, gii tr v xut bn. Cc
ng dng mi ang ni ln, khng ch trong mi trng truyn thng hu tuyn
m c trong mi trng v tuyn. Hin nay, ch c cc dch v s liu tc thp
cho ngi dng di ng. Tuy nhin, nhu cu v h thng a phng tin bng
rng khng dy ang c xem xt v dn c a vo trin khai c trong cc
dch v cng cng cng nh trong dch v c nhn.
Truyn thng a phng tin c yu cu ln i vi bng rng v cht
lng dch v so vi nhng g hin c i vi ngi s dng di ng. Tc bit
cc ng dng s bin i t Kb/s cho thoi ti khong 20Mb/s cho HDTV v
thm ch cao hn.
gii quyt vn ny, cu hi t ra l lm cch no a dng d
liu c tc cao vo khng gian m vn m bo cht lng dch v. Mi
trng v tuyn gy ra nhiu kh khn v s c nhiu sng phn x v cc hiu
ng khc. S dng b cn bng thch ng my thu c th gii quyt vn
nhng kh ng dng trong thc t vi thit b nh gn, chi ph thp. Mt cng
ngh c th loi b vic s dng cc b cn bng phc tp l cng ngh iu ch
phn chia theo tn s sng mang trc giao OFDM, mt cng ngh iu ch a
sng mang.
OFDM l mt cng ngh iu ch a sng mang, phng php ny chia
min ph s dng cho nhiu sng mang, mi sng mang c iu ch bi dng
s liu c tc thp.OFDM tng t nh FDMA ch nhiu ngi s dng
ph c hiu sut cao hn nhiu do khong cch cc knh rt gn nhau. iu ny
c c nh vic lm cho tt c cc sng mang trc giao nhau, trnh c nhiu
gia cc sng mang c khong cch gn nhau.
15
1.1.2 Lch s pht trin.
K thut iu ch OFDM l mt trng hp c bit ca phng php iu
ch a sng mang trong cc sng mang ph trc giao vi nhau, nh vy ph
tn hiu cc sng mang ph cho php chng ln ln nhau m pha thu vn c
th khi phc li tn hiu ban u. S chng ln ph tn hiu lm cho h thng
OFDM c hiu sut s dng ph tn hiu ln hn nhiu sovi cc k thut iu
ch thng thng.
K thut OFDM do R.W CHANG pht minh nm 1966 M. Trong nhng
thp k va qua nhng cng trnh khoa hc v k thut ny c thc hin
khp ni trn th gii. c bit l cc cng trnh khoa hc ca Weisteil v Ebert,
ngi chng minh rng php iu ch OFDM c th thc hin c thng qua
php bin i IDFT v php gii iu ch OFDM c th thc hin c thng
qua php bin i DFT. Pht minh ny cng vi s pht trin ca k thut s lm
cho k thut iu ch OFDM c ng dng ngy cng tr nn rng ri. Thay v
s dng IDFT v DFT ngi ta c th s dng php bin i nhanh IFFT cho b
iu ch OFDM, FFT cho b gii iu ch OFDM. Ngy nay k thut OFDM
cn kt hp vi cc phng php m knh s dng trong thng tin v tuyn. Cc
h thng ny cn c gi vi khi nim l COFDM ( coded OFDM ). Trong cc
h thng ny tn hiu trc khi c iu ch OFDM s c m knh vi cc
loi m khc nhau vi mc ch chng li cc li ng truyn. Do cht lng
knh ( pha inh v t l tn hiu/ tp m ) ca mi sng mang ph l khc
nhau, ngi ta thc hin iu ch tn hiu trn mi sng mang vi cc mc iu
ch khc nhau. H thng ny m ra khi nim v h thng truyn dn s dng k
thut OFDM vi b iu ch tn hiu thch ng. K thut ny hin c s
dng trong h thng thng tin my tnh bng rng HiperLAN/2 Chu u. Trn
th gii h thng ny c chun ha theo tiu chun IEEE.802.11a.
1.1.3 Cc u v nhc im
Bn cnh nhng u im k trn ca OFDM, cc h thng s dng k thut
ny cn c nhiu u im c bn lit k sau:
16
- H thng OFDM c th loi b hon ton nhiu phn tp a ng ( ISI)
nu di chui bo v ln hn tr truyn dn ln nht ca knh.
- Ph hp cho vic thit k h thng truyn dn bng rng ( h thng c tc
truyn dn cao), do nh hng ca phn tp v tn s (frequency
selectivity ) i vi cht lng h thng c gim nhiu so vi h thng
truyn dn n sng mang.
- H thng c cu trc b thu n gin
K thut iu ch OFDM c mt vi nhc im c bn sau:
- ng bao bin ca tn hiu pht khng bng phng. iu ny gy mo
phi tuyn cc b khuch i cng sut pha pht v thu. Cho n nay nhiu
k thut khc nhau c a ra khc phc nhc im ny.
- S s dng chui bo v trnh c nhiu phn tp a ng nhng li
gim i mt phn hiu sut ng truyn, do bn thn chui bo v khng
mang tin c ch.
- Do yu cu v iu kin trc giao gia cc sng mang ph, h thng
OFDM rt nhy cm vi hiu ng Doppler cng nh l s dch tn (
frequency offset ) v dch thi gian ( time offset ) do sai s ng b.
Ngy nay k thut OFDM c tiu chun ha l phng php iu ch
cho cc h thng pht thanh s DAB v DRM, truyn hnh mt t DVB T,
mng my tnh khnng dy vi tc truyn dn cao HiperLAN/2,
1.2 Phng php iu ch v gii iu ch OFDM
H thng OFDM l h thng s dng nguyn l ghp knh phn chia theo
tn s trc giao, hot ng trn nguyn l pht d liu bng cch phn chia lung
d liu thnh nhiu lung d liu song song c tc bt thp hn nhiu v s
dng cc lung con ny iu ch sng mang vi nhiu sng mang con c tn
s khc nhau. Cng ging nh h thng a sng mang thng thng, h thng
OFDM phn chia di tn cng tc thnh cc bng tn con khc nhau cho iu
ch, c bit tn s trung tm ca cc bng con ny trc giao vi nhau v mt
ton hc, cho php ph tn ca cc bng con chn ln nhau tng hiu qu s
dng ph tn m khng gy nhiu.
17
1.2.1 Khi nim v s trc giao ca hai tn hiu
V mt ton hc xt tp cc tn hiu vi
p
l cc phn t th p ca tp,
cc tn hiu trong tp trc giao i mt vi nhau l:


*
,
( ) ( )
0,
a
p q
b
k p q
a t a t dt
p q
=

=

=

}

Trong
*
( )
q
t
l lin hp phc ca
( )
a
p
b
t
}
. khong thi gian t a
n b l chu k ca tn hiu, cn k l mt hng s.
1.2.2 iu ch OFDM
Da vo tnh trc giao, ph tn hiu ca cc sng mang ph cho php chn
ln ln nhau. S chng ln ph tn hiu ny lm hiu sut s dng ph ca ton
b bng tn tng ln mt cch ng k. S trc giao ca sng mang ph c
thc hin nh sau: ph tn hiu ca sng mang ph th p c dch vo mt knh
con th p thng qua php nhn vi hm phc
s
jp t
e

, trong
2
s s
f =
l
khong cch tn s gia 2 sng mang. Thng qua php nhn vi s phc ny m
cc sng mang ph trc giao vi nhau. Tnh trc giao ca hai sng mang ph
c kim chng nh sau:

( 1) ( 1)
( )
( )*
s S
t t
s s
k T k T
jq j p q jp
kT kT
e e dt e dt

+ +

=
} }



( 1)
( )
1
( )
s
s
s
t k T
j p q t
t kT
s
e
j p q

= +

=
=

0,
,
s
p q
T p q
=

=

=

(1.2)
18

phng trnh trn ta thy hai sng mang ph p v q trc giao vi nhau do
tch phn ca mt sng manglin hp phc vi sng mang cn li bng o nu
chng l hai sng mang khc bit. Trong trng hp tch phn vi chnh n s
cho kt quar l mt hng s. S trc giao ny l nguyn tc thc hin gii iu
ch OFDM
s
jL t
e


f
s
f
-L
F
o
F
+L
Hnh 1.1 Biu din ph ca cc tn hiu OFDM
f

Q
19



Thc hin b gii iu ch thng qua php bin i IFFT
Trn hnh 1.2, gi dng bt trn mi lung song song l {a
i,n
}, sau khi qua
b iu ch QAM thnh tn hiu phc a mc {d
k,n
}. Trong n l ch s sng
mang ph, i l ch s ca khe thi gian tng ng vi N
c
bit song sau khi qua
bbin i ni tip/ song song, k l ch s khe thi giantng ng vi N
c
mu tn
hiu phc. Sau khi nhn vi xung c s, c dch tn v qua b tng th cui
cng c biu din nh sau:

'
,
( ) '( )
L
jn t
k k n
n L
M t d s t kT e

+
=
=

(1.3)
Khi bin i lung tn hiu trn thnh s, lung tn hiu trn c ly mu
vi tn s:

1 1
s
a
FFT s FFT
T
t
b N f N
= = =
(1.4)
Trong , B l ton b bng tn ca h thng. Ti thi im ly mu t =
kT+lt
a
, S(t-kT)=s
0
, do vy phng trnh (1.3)

c vit li:

B
phn
ni
tip/
song
song

iu ch
bng
c s (M
QAM )
Xung
c s
Xung
c s
Xung
c s




B
tng



Chn
chui
bo
v
Hnh 1.2 S b iu ch OFDM
s
jL t
e


s
jL t
e


s
jL t
e


20

( )
0 ,
' ( )
s s a
L
jn kT lt
k s a k n
n L
m kT lt s d e

+
+
=
+ = =

0 ,
s s s a
L
jn kT jn T
k n
n L
s d e e

+
=
=

2
0 ,
FFT
nl
L
jn
N
k n
n L
s d e

+
=
=

(1.5)
Php bin tn hiu OFDM phng trnh 1.5 trng vi php bin i
IDFT. Do vy b iu ch OFDM c th thc hin d dng bng php bin i
IDFT. Trong trng hp N
FFT
l bi ca s 2, php bin i IDFT dc thay th
bng phng php IFFT.
u im ca phng php iu ch trc giao ODFM khng ch l s hiu
qu v s dng bng tn m cn c kh nng loi tr c nhim lin tn hiu
ISI thng qua s dng chui bo v. Do vy, tn hiu OFDM trc khi pht i
phi c chn thm chui bo v chng nhiu xuyn tn hiu.
1.2.3 Gii iu ch ODFM
phn tch qu trnh truyn tn hiu OFDm Mt cch n gin ta gi
thit mi trng truyn dn khng c can nhiu tp m trng. Mi lin h gia
tn hiu pht m(t), tn hiu thu T(u) v p ng xung ca knh h( , t) c m t
nh hnh sau:


min thi gian tn hiu thu l tch chp ca tn hiu pht v p ng
xung ca knh:
H(jw,t)
h( ,t)
M(t) u(t)
Hnh 1.3 M hnh mt knh truyn n gin

21

U(t) =m(t) * h(

,t) (1.6)

S cu trc b gii iu ch OFDM c m t nh hnh di y. Tn
hiu a vo b gii iu ch l u(t). Cc bc thc hin b gii iu ch c
chc nng ngc li so vi cc chc nng thc hin b iu ch:
- Tch khong bo v mi tn hiu thu.
- Nhn vi hm s phc
s
jp t
e

( dch bng tn ca tn hiu mi
sng mang v bng tn gc nh trc khi iu ch)
- Gii iu ch cc sng mang ph.
- Chuyn i mi tn hiu phc thnh dng bit.
- Chuyn i dng bit song song thnh dng bit ni tip,ging dng
bit pht.


Thc hin b gii iu ch thng qua php bin i FFT



Tch
chui
bo
v



Chuyn
mu
thnh bit
tn hiu
Gii
iu ch

Gii
iu ch

Gii
iu ch




Chuyn
i song
song /
ni tip
s
jL t
e

s
jL t
e

s
jL t
e

Hnh 1.4 S b gii iu ch OFDM
22
B gii iu ch OFDM dng tng t l b tch phn dng mch s,
tn hiu c ly mu vi chu k ly mu l t
a
. Mt mu OFDM T
s
c chia
thnh N
FFT
mu tn hiu:
a
FFT
Ts
t
N
=
(1.7)
Sau khi ly mu, tn hiu nhn c s l lung tn hiu s.
^
, k l
d
c
biu din nh sau:

1 ^
( ) '
,
1
( )
FFT
s s a
N
jl kT nt
a
k l s a
n
s
t
d u kT nt e
T

+
=
= +

(1.8)
Nh trnh by trong phn gii iu ch ta bin i c nh sau:

1 ^
2 / '
,
0
1
( )
FFT
FFT
N
j nl N
k l s a
n
FFT
d u kT nt e
N

=
= +

(1.9)
Biu thc trn chnh l bin i DFT vi chiu di l N
FFT
, Nu N
FFT
l
bi s ca 2 th ta c th thc hin bng php bin i FFT. Nh vy, ta c th
thc hin m hnh gii iu ch OFDM bng php bin i nhanh FFT.
















23
1.3 H thng v tuyn s dng k thut OFDM


Ngun bit l mt lung bit c iu ch bng tn c s thng qua
phng php iu ch nh QPSK, M-QAM. Tn hiu dn ng c chn vo
mu tn hiu, sau c iu ch thnh mu tn hiu OFDM thng qua b bin
i IFFT v chn chui bo v. Lung tn hiu s s c chuyn thnh lung tn
hiu tng t qua b chuyn i s-tng t trc khi c chuyn thnh lung
tn hiu tng t qua b chuyn i s- tng t trc khi truyn trn knh v
tuyn qua anten pht. Tn hiu truyn qua knh v tuyn b nh hng bi nhiu
pha inh v nhiu trng.
Tn hiu dn ng v tn hiu bit c pha pht v pha thu, v c
pht cng vi tn hiu c ch vi nhiu mc ch khc nhau nh vic khi phc
knh truyn v ng b h thng.
iu ch
bng tn
c s
Chn mu
tn hiu
dn ng
IFFT
Chn
chui
bo v
Bin i
s / tng
t
Knh v
tuyn
Nhiu
Bin i
tng t
/ s
Tch
chui
bo v
FFT
Cn bng
knh
Tch mu
tn hiu dn
ng
Khi phc
knh truyn
Gii iu
ch bng
tn c s
Ngun
bit
Hnh 1.5 M hnh tng quan h thng OFDM

24
My thu thc hin cc chc nng ngc li nh thc hin my pht.
Tuy nhin khi phc c tn hiu pht th hm truyn ca knh v tuyn
cng phi c khi phc. Vic thc hin khi phc hm truyn ca knh v
tuyn c thc hin thng qua mu tin dn ng nhn c pha thu. Tn
hiu nhn c sau khi gii iu ch OFDM c chia lm hai lung tn hiu.
Lung tn hiu th nht l lung tn hiu c ch c a nb knh bng knh.
Lung tn hiu th hai l mu tin dn ng c a vo b khi phc knh
truyn. Knh truyn sau khi c khi phc cng s c a vo b knh bng
knh khi phc tn hiu ban u.
1.3.1 Khong bo v
Tc k t ca tn hiu OFDM thp hn nhiu so vi c truyn n
sng mang. Th d iu ch n sng mang BPSK, tc k t tng ng vi
tc bit truyn. Tuy nhin i vi k thut OFDM, lung d liu ng vo
c chia thnh N lung d liu song song pht i, kt qu l tc k t
OFDM gim N ln so vi tc truyn n sng mang, do n lm gim
c nhiu lin k t ISI b gy ra bi truyn a ng.
Hiu ng ISI trn tn hiu OFDM c th loi b hon ton bng cch cng
thm khong bo v trc mi k t. Khong bo v ny c chn sao cho ln
hn gi tr tri tr cc i trong mi trng cho cc thnh phn a ng ca
k t trc khng th giao thoa vi k t hin ti. Khong bo v c th l khong
trng ( khng c tn hiu g c ). Tuy nhin, nu ta s dng khong trng cho
khong bo v th s gy ra nhiu lin sng mang ICI, v khi cc sng mang
con nhn c my thu khng cn trc giao na. iu ny xy ra do cc
thnh phn a ng ca k t khi nhn c my thu s khng c s nguyn
ln chu k trong thi khong FFT. loi b nhiu ICI th k t OFDM phi
c m rng chu k trong khong bo v m bo rng cc thnh phn a
ng ca k t lun c s nguyn ln chu k trong thi khoang FFT. Do c
m rng chu k nn khong bo v cn c gi l cyclic prefix ( tin t lp ).
Khong bo v c to ra bng cch copy mt s mu pha cui ca mi k t
OFDM v a ln u k t.
25




Chiu di tng ca k t l T
S
=T
G
+T
FFT
, vi T
S
l tng chiu di ca k
t, T
G
l chiu di khong bo v, T
FFT
l kch thc ca IFFT c s dng
pht tn hiu OFDM.

Nh trn hnh 1.6, ta c thy rng nu di tr nh hn khong bo v s
khng c hin tng giao thoa gia k t trc v k t hin ti, do s khng
gy ra ISI v ICI. Tuy nhin do tn hiu nhn c ti my thu l tng ca nhiu
thnh phn a ng nn s gy ra s dch pha cho cc sng mang. Vic c
lng knh ca my thu s khc phc s dch pha ny.
IFFT Guard
Period
IFFT output Guard
Period
IFFT
Symbol N
T
s
Symbol N-1
Symbol N+1
T
G
T
FFT
Time
Hnh 1.6 Khong bo v c cng vo k t OFDM

T
G
T
FFT
Direct

Direct

Sampling period

Hnh 1.7 Tri tr nh hn khong bo v s khng gy ra ISI v ICI
26
1.3.2 c lng knh truyn

Vic c lng nh bm theo knh truyn l cn thit trc khi gii iu
ch OFDM, bi v knh v tuyn l chn lc tn s v bin i theo thi gian
trong h thng di ng.
c lng knh c th thc hin c bng cch a tn hiu dn ng
(pilot) vo tt c sng mang con ca k t OFDM vi chu k ring hoc a mt
s tone pilot vo mi k t OFDM. Cch th nht, c lng knh pilot dng
khi (block), c pht trin di gi s knh fading chm. Thm ch vi b cn
bng feedback quyt nh, cng tha nhn rng hm truyn knh khng thay i
nhanh chng. Vic c lng knh sp xp pilot dng khi da vo LS(least
square: bnh phng ti thiu) hoc MMSE (bnh phng trung bnh cc tiu).
c lng MMSE (l s phc tp)vi li 10 15dB ca SNR, cho cng sai
s bnh phng ti thiu c lng knh LS [6]. Theo [7] xp x hng thp c
ng dng vi MMSE tuyn tnh, bng cch s dng hm tng quan tn s ca
knh loi b iu tr ngi chnh ca MMSE( l s phc tp). Cch th hai l
c lng knh pilot dng lc(comb), c a ra p ng cn thit cho cn
bng khi knh thay i nhanh, thm ch thay i ngay trong mt khi OFDM.
c lng knh pilot dng lc bao gm gii thut c lng knh ta tn s
pilot v ni suy knh.
Khi phc
knh truyn
(c lng
knh)
Tch
mu tn
hiu dn
ng
Cn
bng
knh
(ng
Gii iu
ch bng
tn c s
Tch
chui
bo v
Bin i
tng
t/s
IFFT
Hnh 1.8 S khi ca khi thu OFDM dng c lng knh
27
S c lng knh ti tn s pilot cho c lng dng lc c th da
vo LS, MMSE hoc LMS(least mean square). MMSE cho thy s thc hin tt
hn nhiu so vi LS. S phc tp ca MMSE gim xung xut pht t b c
lng ti u hng thp vi vic phn tch gi tr singular.
Ni suy knh vi c lng dng lc c th dc vo: ni suy tuyn tnh,
ni suy bc 2 (second order), ni suy low- pass, ni suy bc 3, ni suy spline
cubic, ni suy min thi gian . . . Ni suy bc 2 thc hin tt hn ni suy tuyn
tnh. Ni suy min thi gian c chng minh l cho BER thp hn so vi ni
suy tuyn tnh.
M t h thng:


H thng OFDM c lng knh da vo pilot c bu din trong hnh
4.8. Thng tin nh phn th nht c nhm li v nh x ph hp vi iu ch
tn hiu mapper. Sau a pilot hoc tt c cc sng mang con vi chu kc
th hoc ng nht gia chui d liu thng tin, khi IDFT c s dng bin
i chui d liu c chiu di N{X(k)} ra tn hiu min thi gian {x(n) } theo
phng trnh:


Map

S/P

Pilot
Insertio
n

IDF
T
Guard
Inserttio
n

P/S
Guard
Remova
l

DFT
Channel
estimate

P/S

Dema
p

S/P
Channel
Binary
data
Output
data
Y(k) y(k) y
f
(k)
X(k)
h(n)
X
f
(k) x(k)

AWGN

Hnh 1.9 S khi c lng knh da trn pilot
28
1
(2 / )
0
( ) {X(k)} ,n=0,1,2,...,N-1
1
= ( )
N
j kn N
n
x n TDFT
X k e
n

=
=

(1.10)
Sau khi IDFT, khong bo v oc chn ln hn tri tr mong mun,
c a vo chng nhiu lin k t. Bng thng bo v ny bao gm thnh
phn lp li m rng ca k t OFDM loi b nhiu lin sng mang ( ICI).
Kt k t OFDM c cho bi:

1
0
( )
L
j
l
l
H k h e

=
=

x(N+n) , n=-N , 1,.., 1
( )
x(n) , n=0,1,...N-1
g g
f
N
x n
+

(1.11)

Vi N
g
: chiu di ca khong bo v.
Tn hiu truyn x
f
(n) sau khi bin i t song song sang ni tip s c
a qua knh fadinh chn lc tn s v bin i theo thi gian, v c cng
thm nhiu. ti b thu, tn hiu nhn c:


( ) ( ) w(n)
f f
y x n h n = +
(1.12)

Vi w(n): nhiu AWGN, h(n): p ng nhu xung knh truyn.
p ng xung knh truyn h(n) c th uc biu din:


1
(2 / )
0
( ) ( )
Dl n
L
j N f T
l l
l
h n h e

=
=

(1.13)

Trong :
- L: chiu di p ng xung knh truyn.
29
- H
1
: p ng xung phc ca ng truyn th l trong knh truyn a
ng ( L ng ).
- f
D1
: dch tn s Doppler ca ng truyn th l.
-

: ch s tri tr.
- T : chu k ly mu .
-
l

: thi gian tr ca ng truyn th l ( uc chun ha bi thi

gian ly mu ).

Ti b thu, sau khi qua b bin i A/D v b lc low pass, khong bo
v c loi b:

y
f
(n) , -N
g
n N-1
y(n) =y
f
(n+N
g
) , n=0, 1, , N-1

Sau , y(n) c a n khi DFT:


1
(2 / )
0
Y(k)=DFT{y(n)}
= ( )
N
j kn N
n
y n e

(1.14)

Gi s khng c ISI, khi mi quan h gia Y(k) v H(k)=DFT{h(n)},
I(k) (nhiu ICI do dch Doppler), W(k)= DFT{w(n)} l:

Y(k)=X(k)H(k) +I(k) +W(k) , k =0,1,2,,N-1 (1.15)

Vi:

30
1
(2 / )
0
sin( )
( )
Dl l
L
j f T j k
Dl
l
l
Dl
f T
H k h e e
f T

=
=

2 ( )
1 1
(2 / )
(2 / )2 ( )
0 0,
( ) 1
( )
1
l
l
l
j f T k K
L N
j d K
l
j N f T k K
l K
K k
h X K e
H k e
N e

+

+
= =
=

Sau khi qua khi DFT, tn hiu pilot c tch ra v c lng knh
H
e
(k)cho nhng knh con t c trong khi c lng knh. Sau , d liu
truyn c c lng bng:


( )
( )
e
e
Y k
X
H k
=
, k =0,1,,N-1 (1.16)

Sau cng, d liu thng tin truyn c c bng cachs nh x d liu tr
li trong khi Demap tn hiu.
1.3.3 ng b
ng b l nhim v c bn ca nhiu h thng tin s. Vic khng thc
hin gii thut ng b lm cho vic thu d liu truyn thng tin cy. T tung
ca k s thit k gii thut bng gc s, gii thut ng b l vn thit k
chnh m phi c gii quyt xy dngv sn phm thnh cng.
H thng OFDM c nhiu li ch trong vic s dng hiu qu ph tn qua
tnh trc giao v iu ch thch nghi nh c trnh by chng trc. Ngoi
ra vi bn cht bng rng truyn tc cao t nhng d liu tc thp truyn
song song cho php h thng chng ISI, hin tng fadinh chn lc tn s gy ra
sai lch ch mt s sng mang con v vic khi phc trong OFDM c th s
dng FEC (forward error control)v c lnh knh b suy hao. Tuy nhin h
31
thng OFDM vi chiu di k t ln lm cho n chy nhanh hn vi fadinh (
chn lc thi gian) gy bi hin tng dch doppler v s offset tn s sng
mang gia b thu v pht, dn n sng mang con trong h thng OFDM, mt
trc giao v gy nhiu ICI, dn n suy gim cht lng h thng. Vic ng b
trong h thng OFDM cng cn thit i vi h thng OFDM, li nh thi k t
v li tn s ly mu gy ra hin tng xoay pha v mt trc giao. V vy vic
c lng knh truyn v ng b trong h thng OFDM l cn thit vic thu
d liu tin cy v hiu qa. Vic nghin cu hin ang tp trung vo cc gii
phu k thut cn bng gia tnh hiu qu v phc tp ca chng.
ng b trong h thng OFDM
Trong h thng OFDM, nhng sng mang ch hon ton trc giao nu
my pht v thu s dng nhng tn s hon ton ging nhau. Bt c s dch tn
s no cng lp tc gy ra ICI bi v sng mang ny khng cn trc giao na.
Mt vn c lin quan na l nhiu pha. Mt b giao ng trong thc t khng
th to ra mt sng mang chnh xc mt tn s, m thng to ra cc sng
mang c pha ngu nhin, dn n tn s 9 l o hm ca pha theo thi gian)
khng bao gi l mt hng s v th gy ra ICI trong OFDM. cc h thng n
sng mang, nhiu pha v dch tn s thng ch gim t s S/N my thu hn l
gy ra nhiu. y l l do ti sao m nhy vi nhiu pha v dch tn s l mt
im bt loi ca OFDM so vi h thng n sng mang. V vy vic ng b
my thu l mt vn rt quan trng trong h thng OFDM, n phi thc hin
c t nht 2 nhim v sau y:
- Th nht, n phi tm ra u l ng bin ca k hiu v khong thi gian
ti u lm gim ti a nh hng ca ICI v ISI
- Th hai, n phi c long v chnh sa li dch tn s ca sng mang
nhn c trnh ICI. i vi nhng my thu kt hp, ngoi tn s, pha ca
sng mang cng cn uc ng b. Trong h thng OFDM, ngi ta thng
nhc n 3 loi ng b : ng b k t, ng b tn s sng mang v ng b
tn s ly mu.Mt s vn lin quan n x l tn hiu OFDM.
32
1.3.4 Phng php iu ch v gii iu ch QAM
Trong h thng thng tin tng t, c 3 cch c bn iu ch sng
mang: AM, FM, PM. AM c trin khai trc v n d thc hin v d hiu.
n 1933 E.H. Armtrong pht trin FM, t nh hng bi nhiu hn AM.
H thng thng tin s yu cu dung lng ln hn, cht lng tn hiu cao
hn, bo mt tt hn, tng thch vi d liu s. AM v FM cho thy s khng
tng thch vi nhng yu cu v ng truyn lu lng ln. Vi hng triu
thu bao s dng ht bng thng thoi, chng ta cn mt phng php iu ch
m c th truyn thng tin mt cch hiu qu v tin cy.
Cc phng php iu ch mi c pht trin nhanh trong vi nm tr
v trc, kt hp c 3 phng php c bn trn. Kt hp vi cc k thut s, cc
phng php ny cho chng ta hiu qu vi cc u im ca k thut s so vi
k thut tng t.
V sao phi s dng iu ch s? Mt bng tn c bn c s ha c th
lm bt c th g. Chng ta c th gi n bt c khi no, gi xen gia cc
messages, hoc l tnh ton bng cc gii thut truyn vi s bt t hn, c
ngha l s dng t ti nguyn hn.
Mt k thut iu ch thch hp vi x l s gi l IQ modulation. I
y l In-phase tham s pha ca sng mang. Vi nhiu kiu iu ch IQ a
dng, IQ l mt cch truyn thng tin hiu qu, v n cng rt ph hp vi dng
d liu s. Mt b iu ch IQ c th thc s to ra AM, FM v PM.
Khi iu ch mt sng mang vi dng sng c tn s thay i nh, ta c
th coi vic iu ch nh thc hin bin i pha ca sng mang. Khi pha ca
sng mang cha c phn thc v phn o, hay I v Q. Chng ta c th to ra b
thu v gii m thng tin trong sng mang bng cch c ra thnh phn I v Q
ca n.
33


u tin dng d liu dng chui nh phn ly t ngun tin c chuyn
i thnh mu tn hiu phc nh sau



' '' | |
k
i
k k k k
d d jd d e

= + =
(1.17)
vi k {IN}


Trong d
k
v d
k
l cc gi tr thc, d
k
l mu tn hiu phc trong tp M
mu tn hiu khc nhau ca QAM.

d
k
{A
m
} vi k,m =1,2,,M

A
m
c gi l mu tn hiu M-QAM.
T (1.11) ta thy tn hiu QAM c iu ch c v bin |d
k
| v pha
k

.
Do c M mu tn hiu khc nhau nn cn L bit, vi L=log
2
M , cho vic
m ha mt mu tn hiu. L phi l s nguyn nn M phi ly gi tr l 2
L
cho
cc trng hp L = 1,2,3 ta c BPSK, 4-QAM, 8-QAM, 16- QAM v 32
QAM Hnh 1.2 th hin mt v d c th cho trng hp 4-QAM:

Chuyn
i bit
thnh
tn hiu
phc
Xung c
s s(t)
Xung c
s s(t)



B
iu
ch
I/Q
d
k

Dng
bit
d
k
m
TI
(t)
m
TR
(t)
m(t)
Hnh 1.10 S khi b iu ch QAM
34

QAM kiu I,
0
=0


QAM kiu II,
0
=

/ 4


cng thc 1.11, tn hiu nh phn sau khi c chuyn sang mu tn
hiu phc {d
k
} s c nhn vi xung c s s(t). Mc ch ca vic nhn vi
xung c s l ng b cch tn hiu pht v mt thi gian (ng b vi chu k
ly mu T) . C th l bin chui mu tn hiu phc t cc gi tr phc ri rc
jA
A
m

A
2
jA
m

A
3
-jA
A
4
A
0 -A

A
m
A
1
Hnh 1.11 Cc dng biu din 4 - QAM
jA
A
m

A
2
jA
m

A
3
-jA
A
4
A
0 -A
2-QAM

2-ASK

A
m
A
1
35
thnh mt chui cc xung lin tip vi chu k xung l chu k ly mu v c
iu ch vi mt mu tn hiu phc nh sau.


0
( ) ( ) ( ) | | ( )
k
j
T TR TI k
k
m t m t m t d e s t kT

+
=
= + =

(1.18)
Vic nhn vi xung c s ngoi nhim v ng b vi chu k ly mu cn
c tc dng gim nhiu lin tn hiu ISI pha my thu, ty thuc vo vic thit
k dng xung c s. Trng hp n gin nht ca xung c s l xung vung
hnh ch nht.


PT (1.12) th hin tn hiu QAM bng tn c s . Tn hiu ny c
iu ch c v bin v pha.
pht tn hiu i xa, tn hiu bng tn c s m
T
(t) phi c chuyn
ln tn hiu tn s cao thng qua b u ch I/Q nh sau:
s(t)
T t
0
1
Hnh 1.12 Xung c s dng ch nht
36

Tn hiu sau khi iu ch I/Q c biu din nh sau:

0
0 0
( ) Re {m (t) }
=m (t)cos ( )sin
j t
T
TR TI
m t al e
t m t t

(1.19)
Tn hiu m(t) c gi l tn hiu bng thng c a vo b khuch
i cao tn v tn x anten pht.
L thuyt v gii iu ch:


B
gii
iu
ch
I/Q
Ly mu
chu k T
Ly mu
chu k T


Chuyn
i mu
phc
thnh
dng bit
tn hiu
m
TR
(t)
m(t)
m
TI
(t) d
k

d
k

Dng bit
Hnh 1.14 S khi b gii iu ch QAM
m
TR
(t)
cos
0
t

m
TI
(t)
-sin
0
t


m(t)
Hnh 1.13 B iu ch I/Q
37
T tn hiu m(t) thu c ta cn gii iu ch QAM thu c dng bit
ban u. B gii iu ch I/Q thc cht l b bin i tn hiu m(t) thu c
bng tn c s m
T
(t) .


Hnh (1.13) cho thy tn hiu m(t) thu c gm 2 thnh phn, bi vy sau
khi qua cc b nhn cos
0
t v sin
0
t ta s tch m(t) thnh cc thnh phn tn
cao v tn thp nh sau:
2
0 0 0 0
( ). os ( ). os ( )sin . os
TR TI
m t c t m t c t m t t c t =


0 0
1 1
( ).(1 os 2 ) ( )sin2
2 2
TR TI
m t c t m t t = +

0 0
1 1 1
( ). os 2 ( )sin2
2 2 2
TR TR TI
m m t c t m t t = +

(1.20)
2
0 0 0 0
( ).( sin ) ( ). os ( sin ) ( )sin
TR TI
m t t m t c t t m t t = +
cos
0
t

-sin
0
t


Hnh 1.15 B gii iu ch I/Q
B lc
thng thp
( LPF )
B lc
thng thp
( LPF )
m(t)

m
TR
(t)
m
TI
(t)

38

0 0
1 1
( ).sin2 ( )(1 os2 )
2 2
TR TI
m t t m t c t = +

0 0
1 1 1
( ) ( )sin2 ( ) os2 )
2 2 2
TR TR TR
m t m t t m t c t =

(1.21)
Tn hiu s(t) sau khi qua cc b nhn cos
0
t v sin
0
t c a vo b
lc thng thp loi b cc thnh phn tn cao ly ra thnh phn c tn s
bng tn c s l m
TR
(t) v m
TI
(t).
Cc tn hiu lin tc m
TR
(t) v m
TI
(t) c chuyn i thnh cc mu tn
hiu ri rc d
k
v d
k
thng qua b ly mu vi chu k ly mu bng vi chu k
xung c s pha pht nhm m bo ng b tn hiu thu vi tn hiu pht.
Cui cng cc mu tn hiu ri rc qua b chuyn i symbol to bits
thu c dng bit ban u truyn i.
1.3.5 V d mch iu ch QAM
t c tc iu ch cao ngi ta kt hp iu ch ASK vi PSK. V
d trng hp c bit l iu ch PSK-18P t c dng hn l QAM-16.
iu ch QAM-16 ta c th kt hp ASK 4 mc vi PSK 4P. Xem hnh di
iu ch QAM-16. Dng s liu c chia thnh hai dng s liu song song ri
qua mch bin i thnh tn hiu 1 chiu 4 mc (1 mc s tng ng vi 2 bit ).
Cc tn hiu ny s ln lt c iu ch bi cc sng mang cos v sin sau
cng li vi nhau.
39


Hnh 1.16 iu ch v gii iu ch QAM-16

Hnh 1.17 QAM-16

1.3.6 nh hng s lng sng mang con v khong thi gian bo v
Xt h thng OFDM 64 sng mang con s dng iu ch 16 QAM vi
mt knh a ng 2 tia. Cng sut ca tia th hai nh hn 6dB so vi tia th
nht. Nhiu my thu c b qua xem xt nh hng ca ISI v ICI hiu
nng h thng tng ng vi hai tham s ny.
90
0

90
0
iu ch Gii iu ch
cose
0
t cose
0
t
sine
0
t
sine
0
t
40
Hin tng t nhiu lm cho mt s im tn hiu vt qua cc bin quyt
nh v lm gim cp tng i hiu nng BER. Do cc b cn bng knh
mt pha phi c trin khai ti u ra FFT sa mo bin v mo pha gy
bi tr a ng.
i vi h thng OFDM 64 sng mang con vi b cn bng mt hng
ti my thu, khi thi gian tr truyn a ng cng tng th nhiu ISI cng tng
khi tr ln hn khong thi gian bo v, dn ti lm tng BER ca h thng.
nh hng ca ISI c th lm gim c bng cch tng thi gian k hiu
OFDM, xc nh nh hng ta nh ngha mt s o:

=( tr truyn lan ) / ( thi gian k hiu )

Vi rng bng tn hiu OFDM cho trc, thi gian k hiu t l vi s
lng sng mang con, nu

ln, mt lng ln cc mu k hiu OFDM khc

nhau b nh hng bi ISI v do h thng c BER cao v ngc li. Ta thy
rng ISI cng gim hn khi h thng OFDM c s lng sng mang con cng
tng. Tuy nhin, khi s lng sng mang con tng nhiu lm thu hp khong
cch tn s gia chng khin chng d b hiu ng doppler.
Cc k hiu OFDM thi gian di mm do hn vi fading la chn tn s
nhng nhy cm hn vi fading la chn thi gian. Fading la chn thi gian
lm mt tnh trc giao gia cc sng mang con. Vi mt rng bng cho trc,
khong cch tn s gia cc sng mang con gim khi s sng mang con tng.
Khong cch tn s gia 2 sng mang con nh lm chng d b ICI do dch tn
gy bi hiu ng Doppler ca knh.
nh hng ca s sng mang con v khong thi gian bo v n hiu
nng h thng c tng kt nh sau:
Vi s lng sng mang con cho trc, tng khong bo v s lm
gim ISI do gim t l tr thi gian k hiu, nhng ng thi cng lm
gim hiu qu cng sut v hiu qu bng tn.
41
Vi rng bng tn tn hiu cho trc, tng s lng sng mang con
tng hiu qu cng sut nhng cng tng thi gian k hiu lm cho h
thng nhy cm hn vi tri ph doppler.
1.4 Kt lun
Ni dung ca chng u tin ny l nhng vn c bn lin quan n k
thut phn knh theo tn s trc giao. Hiu c nhng vn c bn ca
OFDM, chng ta s hiu c kh nng ng dng ca n, v lm c s khi thit
k k thng thu pht s dng k thut OFDM ny.























42
Chng 2 Mt s h thng truyn dn s dng k thut
OFDM
2.1 Gii thiu
Cng ngh OFDM ngy cng c ng dng rng ri. S kt hp gia k
thut s v k thut vi mch DSP c kh nng tnh ton nhanh gip to tn hiu
OFDM n gin v hiu qu. Nh vy OFDM c ng dng rng ri trong
nhiu h thng thng tin khc nhau nh: h thng pht thanh s, h thng truyn
hnh mt tV chng ny chng ta s n vi mt s h thng truyn dn
s dng cng ngh OFDM.
2.2 H thng DRM
DRM l h thng pht thanh s thay th cho h thng pht thanh iu tn
truyn thng FM. Tn s sng mang cho h thng DRM tng i thp, c th l
nh hn 30MHz, ph hp cho vic tuyn sng khong cch ln. Mi trng
truyn sng ca h thng l knh phn tp a ng c s tham gia phn x ca
mt t v tng in li nh m t hnh 3.1. Phm vi ph sng ca DRM do vy
rt ln, c th l a quc gia, hoc lin lc a. Do s dng k thut s v cng
ngh OFDM, cht lng tn hiu ca h thng DRM tng i tt.
43

Hnh 2.2 m t s khi mt h thng DRM, trong h thng c th
truyn ti c d liu v m thanh v cc dch v khc. S s dng m ha knh
cho php sa li pha thu.
Cc tham s c bn ca h thng c a ra nh sau
- B rng bng tn B = 9,328 kHz
- di FFT N
FFT
=256
- di chui bo v T
G
=5.3 ms
- S sng mang s dng truyn tin N
c
=198





400km
400km
Truyn dn khong cch nh
( Gc pht gn thng ng)

Truyn dn khong cch ln
( Gc pht thp)
Hnh 2.1 Mi trng truyn sng ca h thng DRM
44

M hnh knh truyn dn

Tham s Tuyn phn x th nht Tuyn phn x th 2
Tr truyn dn
ax m

0 1,664 ms
Tn s Doppler ln
nht f
D

1 Hz 1Hz

T m hnh knh truyn dn ta thy knh truyn dn c tr truyn dn ln,
c ngha l knh tng i nh so vi khong chc gia hai sng mang. H
thng DRM c thit k ch cho cc my thu tnh hoc xch tay. iu ny khc
hn so vi h thng DAB, thng ny c thit k cho c cc my thu c tc
chuyn doongj tuowong di ln nh otoo, tu ha,v.v.v
2.3 H thng HiperLAN (IEEE802.11a)
H thng HiperLAN/2 tng ng vi tiu chun IEEE802.11a c
thit k cho mng my tnh khng dy WLAN. Tc truyn dn ln nht h
M ha
ngun
Tin m
ha
Tin m
ha

Tin m
ha



Ghp
knh
Phn
tn
nng
lng
M
ha
kh

Ci
xen











nh
x
Pht
pilot
M ha
knh
M ha
knh

Phn tn nng
lng
Phn tn nng
lng

iu ch
tn hiu
OFDM
iu
ch
Dng d
liu m
thanh

D liu
Thng
tin truy
cp
knh
nhanh

Thng
tin m
t dch
v
Bo v
bnh
thng
Bo v cao
Bo v
bnh
thng
Bo v cao
Bo v
bnh
thng
/ cao


MSC

FAC

SDC
Hnh 2.2 S khi ca h thng DRM


Tn
hiu
DRM
45
thng c th cung cp c vo khong 54 Mbit/s ty thuc vo mi trng
truyn dn. B rng bng tn s dng l 20 MHz v c khai thc vng tn s
khong 5 GHz. Mi trng truyn dn l trong nh v gia cc ta nh.
Khong cch truyn dn tng i nh khong vi mt n vi trm mt.
Cc tham s c bn ca h thng c lit k nh sau
- B rng bng tn: B = 20 MHz
- di FFT: N
FFT
=64
- Chu k ly mu t
a
=
1
B
=50 ns
- di chui bo v T
G
=0.4

s i vi mi trng truyn dn
trong nh v khong 0.8

s i vi mi trng truyn dn ngoi

tri.
2.4 H thng Wimax (IEEE802.16a,e)
Wimax (IEEE-1) ra i nhm cung cp mt phng tin truy cp Interneet
khng dy tng hp c th thay th cho ADSL v WLAN. H thng WiMax c
kh nng cung cp ng truyn vi tc ln n 70 Mb/s v vi bn knh ph
sng ca mt trm anten pht ln n 50 km. M hnh ph sng ca mng
Wimax tng t nh mng in thoi t bo. Mt h thng Wimax nh m t
hnh 3.3 gm 2 phn:
- Trm pht: ging nh cc trm BTS trong mng thng tin di ng
vi cng sut ln c th ph sng mt vng rng ti 8000
2
km
.
- Trm thu: C th l cc anten nh nh cc Card mng cm vo
hoc c thit lp sn trn Mainboard bn trong my tnh, theo
cch m WLAN vn dng.
Cc trm pht BTS c kt ni ti mng Internet thng qua cc ng
truyn tc cao ring hoc c th c ni ti mt BTS khc nh mt trm
trung chuyn bng ng truyn thng (line of sight), v chnh v vy Wimax c
th ph sng n nhng vng rt xa.
46
Cc anten thu/pht c th trao i thng tin vi nhau qua cc tia sng
truyn thng hoc cc tia phn x. Trong trng hp truyn thng LOS (Line of
sight), cc anten c t c nh trn cc im cao, tn hiu trong trng hp
ny n nh v tc truyn c th t ti a. Bng tn s dng c th dng
tn s cao n 66 GHz v tn s ny tn hiu t b giao thoa vi cc knh tn
hiu khc v bng thng s dng cng ln hn. i vi trng hp c vt chn
NLOS ( non line of sight ), Wimax s dng bng tn thp hn, 2-11GHz, tng
t nh WLAN, tn hiu c th vt qua cc vt cn thng qua phn x, nhiu
x, un cong, vng qua cc vt th n ch.

Hnh 2.3 M hnh truyn thng ca Wimax

H thng Wimax c cc c chnh sau (IEEE-1):
- Khong cch gia trm thu v pht c th ti 50 km.
- Tc truyn c th thay i, ti a 70 MHz.
- Hot ng trong c hai mi trng truyn dn: ng truyn tm
nhn thng LOS v ng truyn che khut NLOS.
47
- Di tn lm vic 2-11 GHz v t 10-66 GHz hin v ang c
tiu chun ha.
- Trong Wimax hng truyn tin c chia thnh hai ng ln v
xung. ng ln c tn s thp hn ng xung v u s dng
cng ngh OFDM truyn. OFDM trong Wimax s dng ti a
2048 sng mang, trong c 1536 sng mang dnh cho thng tin
c chia thnh 32 knh con mi knh con tng ng vi 48
song mang. Wimax s dng iu ch nhiu mc thch ng t
BPSK, QPSK n 256- QAM kt hp cc phng php sa li d
liu nh ngu nhin ha, vi m ha sa li Reed Solomon, m
xon t l t n 7/8.
- rng bng tn ca Wimax t 5 MHz n trn 20 MHz c chia
thnh nhiu bng con 1,75 MHz. Mi bng con ny c chia nh
hn na nh cng ngh OFDM, cho php nhiu thu bao c th
truy cp ng thi mt hay nhiu knh mt cch linh hot m
bo tit u hiu qu s dng bng tn. Cng ngh nay c gi l
cng ngh a truy nhp OFDMA (OFDM access)
- Cho php s dng c hai cng ngh TDD ( time division duplexing
) v FFD (frequency division duplexing ) cho vic phn chia truyn
dn ca hng ln (uplink) v hng xung (downlink )
- V cu trc phn lp, h thng Wimax c phn chia thnh 4 lp:
lp con tng ng (Convergence) lm nhim v giao din gia lp
a truy nhp v cc lp trn, lp a truy nhp (MAC layer ), lp
truyn dn (Transmission) v lp vt l (Physical). Cc lp ny
tng ng vi hai lp di ca m OSI v c tiu chun ha
c th giao tip vi nhiu ng dng lp trn.
2.5 Kt lun
Chng ny cho chng ta thy ng dng ca cng ngh OFDM trong mt
s h thng thng tin v truyn dn. Trong tng lai chc chn cng ngh OFDM
s cn c mt vai tr quan trng hn cng vi nhiu ng dng rng ri trong
nhiu h thng truyn thng, truyn dn.

48
CHNG 3: X L TN HIU TRN DSP
3.1 Gii thiu
Trong i sng cng nh trong k thut ngy nay, k thut s c ng
dng v s dng rt rng ri. Nn vic nghin cu, s dng cc phng php x
l tn hiu s l rt quan trng. Mt trong nhng phng php c s dng
nhiu l phng php dng cc loi vi iu khin. Trong chng ny ta s nghin
cu vi iu khin TMS 320C6416 DSP do Texas instrument sn xut. M c th
l tm hiu TMS320C6416 DSK, y l mt mch tch hp cc linh kin phc v
hot ng ca con vi x l ch C6416. Mch ny c sn xut tin dng cho
vic nghin cu, hc tp, m phng t i n nhng ng dng thc t. Cc
linh kin tch hp trn bo mch vic th, lp trnh, ng dng ca vi x l l
thun li nht. Sau y l trnh by c im c bn nht ca bo mch v phng
php hot ng ca n.
3.2 TMS320C6416 DSK
3.2.1 Tng quan v phn cng
Hnh nh ca c bo mch:

Hnh 3.1 Hnh nh bo mch TMS320C6416 DSK
49
TMS320C6416 DSK l mt mch thuc h TI C64xx DSP. Mch c
thit k cho vi x l TMS320C6416. Sau y l s n gin ca mch


Hnh 3.2 S khi ca bo mch
Mch gm cc thnh phn c bn sau:
- Mt vi x l TMS320C6416 hot ng tn s 600 hoc720MHz
- Mt b bin i s-tng t AIC23
- 16Mbytes SDRAM
- 512 Kbytes b nh Flash
- 4 LED v 4 chuyn mch cho ngi dng
- Thanh ghi logic CPLD
- Cc khe cm giao tip vi b nh ngoi v thit b ngoi vi
- Giao tip vi my tnh qua cng USB bi kt ni JTAG
- Cng ngun (+5v)
Trn y l cc linh kin c s dng trong mch, tip theo ta nghin
cu c th cc khi ca mch
50
3.2.2 Khi x l trung tm TMS320C6416
TMS320C6416 DSP hot ng tn s 720MHz. DSP c sn xut vi
cng ngh cao, n l tch hp ca nhiu vi mch vi chc nng c ci tin rt
nhiu. Khi vi x l bao gm mt s khi c bn sau:
- VLIWcore: y l mt cu trc x l cho php x l nhiu yu cu ti
mt thi im ( 6416 DSP l 8 ) trong mt xung ng h trong khi vn
hot ng tc cao. Cu ca VLIW c th t tc x l cc k cao
nhng vn tin dng cho ngi lp trnh thng qua code composer
- 1Mbyte b nh trong vi tc truy nhp rt cao
- On chip PLL( vng kha pha trn chip): To ra xung ng h cho chip
t xung ng h vi tn s nh hn bn ngoi.
- EDMA Controler: iu khin lm tng tc truyn d liu m khng
cn s can thip ca khi trung tm.
- 3McBSPs: y l phn m giao tip gia khi x l trung tm vi thit
b ngoi vi. Mi McBSP c th s dng truyn d liu tc cao vi
thit b ngoi vi hay chc nng vo ra. McBSP2 s dng truyn v
nhn tn hiu m audio t AIC23. McBSP1 s dng iu khin vic m
ha trong khi bin i A-D. McBSP0 kt ni vi thit b ngoi vi.
- EMIFA l bus giao tip gia khi x l vi b nh ngoi hoc cc thit b
khc c th kt ni, bus s dng l 64 bit.
- EMFIB l bus cng dng kt ni vi b nh ngoi hoc cc thit b
khc nhng ch dng 16 bit. N c s dng trong nhng trng hp
tm thi hay l khi khng cn bng thng ln.
Trn y ta tm hiu cu trc c bn ca khi x l trung tm, l b phn quan
trng nht ca bo mch, n iu khin mi hot ng ca h thng. Sau y ta
tm hiu v b phn lu tr ca h thng, l b nh.
3.2.3 B nh
H vi x l C64xx c kh nng to ra b nh ln, vi khng gian a ch
ln, dng 32 bit a ch. Vi C6416 c s phn b a ch vng nh sau:

51

Hnh 3.3 Phn vng b nh ca C6416

Vi mc nh a ch bt u c nh t b nh trong ca khi x l,
ni cha m lnh. Sau tip tc n vng nh ngoi nh c ch ra trn
hnh.
- DSK s dng 64 megabit SDRAM, giao tip bi bus CE0 ca EMIFA, 64
bit. DSK s dng xung ng h cho EMIFA l 120MHz. Khi s dng
DRAM cn lu l mi hng ca ma trn nh s c lm ti sau mi
khong thi gian l 15,6 mirco giy.
- DSK s dng b nh ngoi l 512 Kbyte Flash. N kt ni vi CE1 ca
EMIFB vi giao din 8 bit. Flash l dng b nh khng b mt khi mt
ngun. Khi c n cng khng c nh c ROM. Flash c th xa v ghi
li nhiu ln qua phn mm. Flash yu cu 70 ns cho c c v ghi.
52
3.2.4 AIC23
DSK s dng b Texas Instrument AIC23 ( #TLV320AIC320 ) bin
i s - tng t cho tn hiu audio vo v ra. Tn hiu tng t c th vo qua
ng MIC IN hoc l ng LINE IN chuyn i sang dng s m DSP c
th x l. Sau khi kt thc qu trnh x l, tn hiu s c th chuyn i ngc li
thnh tn hiu tng t v xut ra ngoi thng qua ng Headphone hoc ng
LINE OUT. B chuyn i s - tng t s dng hai knh iu khin. Mt knh
iu khin thanh ghi trong nh dng cho b m ha. Mt knh c chc nng gi
v nhn cc mu tn hiu s v tng t. McBSP1 c s dng v hng
iu khin knh. N s c chng trnh gi mt t iu khin nh dng
thanh ghi. Cn 9 bit thp l gi tr thanh ghi. Knh diu khin ch s dng khi
nh dng khi to cho b m ha, n thng c s dng khi tn hiu m
thanh ang c truyn.


Hnh 3.4 B chuyn i s - tng t AIC23

McBSP2 c s dng nh l mt knh tn hiu c hng. Tt c tn hiu
m thanh s dc truyn qua knh ny. Nhiu d liu nh dng s c c bn
cung cp trn ba bin l rng mu, ngun tn hiu ng h v ngun nh
53
dng d liu. Cc v d ca DSK thng s dng mu c rng l 16 bit m
ha, n to ra khung ng b v xung ng h chun ha tn s ly mu.
B m ha c h thng ng h 12 MHz ny ph hp vi tn s ca USB
v nhiu h thng USB s dng ng h 12MHZ v cng c th dng chung
ng h cho b m ha v iu b iu khin USB. C th to ra nhiu tn s
nh hn t tn s c s ny, nh cc tn s 48KHz, 44.1 KHz v 8KHz. Tn s
ly mu c th c khi to bng thanh ghi SAMPLERATE.
3.2.5 CPLD
C6416 DSK s dng mt thit b logic tch hp c kh nng lp trnh
c l EMP312TC100-10. N bao gm cc phn chnh l:
- 4 vng nh iu khin trng thi thanh ghi n cho php iu khin
phn mm v s thay i trn bo mch.
- a ch gii m v b nh truy nhp logic.
- iu khin giao din v tn hiu ca daughter card.
- Lin kt logic cc b phn trn bo vi nhau.
CPLD c s dng vi chc nng c bit trn DSK. Phn cng ca ta
c thit k vi cng ngh cao, n c chc nng v u im ln khi DSP hot
ng mc cao m ta khng cn dng cc thit b logic ngoi.
CPLD cng l mt thit b c hm logic ngu nhin m khng cn thit b
no thm. Hn na, CPLD t hp cc bin tn hiu khi dng n t nt reset v
qun l ngun v to ra lnh khi to ton cc.
EMP312TC100-10 s dng ngun 3,3V (c th chp nhn l 5V), vi 100
chn QPF, 80 chn vo ra, tr t chn ny ti chn kia l 10ns. Thit b c
EEPROM-base v mt h thng trong kh trnh iu khin dnh cho giao din
J TAG. File ngun ca CPLD c vit bi ngn ng VHDL v c lu trong
DSK.
3.2.6 Cc m rng (daughter card)
DSK cung cp ba kt ni m rng c th s dng ni cc ci. Cc ny
cho php kt ni trn nn DSK, cung cp cc ng dng cho ngi dng hoc l
54
cng vo ra. Kt ni m rng ny l b nh ngoi, thit b ngoi vi, v Host Port
Interface (HPI).
B nh kt ni c cung cp truy nhp vi tn hiu ng b EMIF ca
DSP c giao din vi cc b nh khc v s b nh ca DSP, c cung cp
mt khng gian ring bit. a ch nh l 32 bit nh ta tm hiu trn. S kt
ni ny thng qua McBSPs, ngt, v ng h. Cc kt ni ny cng cung cp
ngun v t cho cc m rng.
HPI l mt giao din c tc cao, n c cho php thc hin nhiu giao
tip vi DSP. Kt ni HPI a tn hiu ra, iu khin tn hiu tt nh l
McBSP2.
3.2.7 Cc yu cu to mt chng trnh cho DSK vi CCS
DSK TM32C6416 do Texas Instrument sn xut v phn phi, ngoi
mch chnh, cn cc ph kin i km nh dy ngun, dy kt ni vi my tnh
qua cng USB, a ci Code Composer Studio( CCS ).
DSK kt ni vi my tnh thng qua cng USB. Qua y chng trnh s
c np vo DSK thng qua phn mm Code Composer Studio, l phn
mm s dng ngn ng C lp trnh cho DSK.C giao din cho ngi dng.
Cc bc to mt chng trnh cho DSK:
Ci t phn mm Code Composer Studio trn my tnh.
Cm ngun v kt ni vi cng USB my tnh
Kim tra li cc kt ni bng phn mm
Thc hin chng trnh
Sau khi ci t CCS trn my tnh, ta thy cc biu tng sau:



55
kim tra xem h thng sn sng lm vic cha, ta chy phn mm
64176 diagnost... qu trnh kim tra hon thnh khi tt c cc n xanh c bt
hin ln, nu c li khi no th n c mu .


Sau khi kim tra xong ta m phn mm C6416 DSK CCS bt u
lm vic. Mt giao din c m ln. Chng trnh ca chng ta s c to ra
y. Cc chng sau s ch cho chng ta cch lm vic vi CCS to ra cc
ng dng ca mnh.
3.3 Kt lun
Chng ny trnh by tng quan v DSK TM320C6416 ca TI. Cc thnh
phn c bn hp thnh nn DSK cng nh cch ci t v kim tra trng thi sn
sng lm vic ca phn mm CCS km theo. Khi chc chn c phn mm v
phn cng sn sng lm vic chng ta s n vi cc chng sau lm vic
vi chng nhm to ra cc chng trnh ng dng thc hin cc cng vic ca
chng ta.
56
Chng 4: Bt u vi CCS
4.1 Gii thiu
CCS l phn mm i km theo DSK, n l trnh son tho, g li cng
nh bin dch cc chng trnh ca chng ta.
4.2 Code composer Studio Tutorial
Bt u hng dn CCS bng cch chn Help Tutorial
Phn ny bao gm cc bi ging gip chng ta lm quen nhanh vi CCS
IDE. CCStudio Tutorial cho php bn rt ngn thi gian hc CCS ng thi cung
cp cho bn cc thng tin c bn v cc th tc.
4.3 Chu trnh xy dng v pht trin sn phm vi CCS

4.4 Cu hnh h thng ( Creating a system configuration )
CCS cho php chng ta cu hnh h thng lm vic vi h phn cng
khc nhau. Chng ta c bt u lm vic nhanh bng cch cu hnh cc h thng
mc nh theo cc cu hnh chun m CCS cung cp. Chng hn h thng
5000
TM
C th c file h thng chun l 55
TM
C x v h thng 6000
TM
C chng ta c
file h thng chun l 64
TM
C x . 6000
TM
C 55
TM
C x
CCS cho php chng ta la chn cch cu hnh h thng s dng cc file
h thng chun hoc khi to cc file cu hnh theo yu cu ca ngi s dng
cc file cu hnh ring.
Thit k
Khi nim
Lp k hoch
Vit m v
xy dng
Project, vit
file ngun v
file cu hnh
G li
Kim tra
cu trc
Kho st

Phn tch
thi gian
thc, g li,
thng k,
ha li.
Hnh 4.1 Chu trnh xy dng v pht trin sn phm vi CCS
57
Cc bc khi to cu hnh h thng s dng cc file cu hnh h thng
chun:
- Bc 1: Bt u bng cch click p vo biu tng Setup
CCStudio
- Bc 2: Click vo Remove All trong hp thoi System
Configuration loi b cc cu hnh nh ngha trc .


- Bc 3: Click Yes chng thc lnh Remove All.
- Bc 4: Chn cu hnh chun ph hp t cc cu hnh c sn
nh hnh sau:
58


- Bc 5: Click phm Add chn cu hnh va la chn. Cu
hnh la chn s hin th pha di biu tng My System
icon trong bng System Configuration ca ca s Setup.
Nu bn mun cu hnh cho nhiu h thng khc nhau th hy
lp li cc bc 4 v 5. Phn bn phi ca ca s Code
Composer Studio Setup l cc thng tin m t cu hnh la
chn. Chng ta xem xt xem cu hnh c ph hp vi h
thng ca chng ta khng. Nu khng ph hp chng ta c
th thay i li bng cch click phm Modify Properties. Sau
khi khai bo cc thng s thch hp ta click OK.
- Bc 6: Click phm Save&Quit lu li cu hnh va la
chn v bt u lm vic vi CCS.
- Bc 7: Click Yes bt u lm vic vi CCStudio khi
thot khi to CCStudio. Ca s Setup CCStudio ng v
CCStudio IDE t ng m ra cho ta s dng vi cu hnh h
thng va to.

59


Bn c th bt u lm vic vi CCStudio IDE.
4.5 Qun l cc thnh phn
Qun l cc thnh phn l thanh cng c cao cp s dng chnh ty
chnh hoc sa li cc khi to ca bn. Ch s dng cc thanh cng c ny
gii cc tng tc gia cc b phn trong ty chnh hoc khi to nhiu mi
trng lm vic.
Ta c th m Compoment manager:
- Bc 1: T menu help chn About hp thoi About CCS
xut hin
- Bc 2: Click button Compoment Manager
Ta c th m Compoment Manager bng cch vo:
C:\ti\cc\bin\comp_mgr.exe
4.6 Kt lun
Chng ny ch cho chng ta cch cu hnh cho phn mm ph hp vi
cu hnh ca DSK m chng ta s lm vic.
60
Chng 5: Cng c qun l v bin dch CCS
5.1 Gii thiu
Cng c qun l v bin dch CCS cho php chng ta bt u lm vic vi
CCS mc c bn t vic khi to mt chng trnh n vic bin dch v g
li. Bn cnh cn c thm cc cng c h tr cho qu trnh lm vic ca
chng ta tr nn d dng hn. C th nh cc phn di.
5.2 Khi to project mi:
Cc bc khi to d n mi:
- Bc 1: T menu chn New Hp thoi xut hin.



- Bc 2: Chn cc thng s tng ng vi h thng ca bn v
click Finish
Sau khi to project mi th ca s sau xut hin:
61


5.3 Xy dng v chy chng trnh:
xy dng v chy chng trnh ta thc hin theo cc bc sau:
- Bc 1: Vit cc file ngun cho chng trnh. y l cc file
c dng file.c. to ra cc file ngun ny chng ta vo File
New Source file. Cc cu lnh trong chng trnh ca chng
ta s c to ra ti y. Sau chng ta s lu file ngun li
bng cch click File Save as. Chn ng dn cho file
ngun vo ng th mc cha project ca chng ta, khai bo
tn v click Save.
- Bc 2: Add cc file vo project bng cch click chut phi ln
tn ca project ang lm vic bn phi ca ca s chng
trnh CCS, chn Add Files to Project nh hnh sau.
62


- Bc 3: Chn file ngun ( file.c ) va to ra v click Open.
- Bc 4: Add cc file th vin vo chng trnh. y chng
ta lm vic vi chip C6416 nn chng ta s Add file rts6400.lib
trong th mc C:\Program
Files\CCStudio_v3.1\C6000\cgtools\lib vo chng trnh nh
Add file ngun bc 3.
- Bc 5: Click Scan All File Dependencies tham chiu cc
file.h vo chng trnh. Cc file.h ny s t ng c to ra.
63


- Bc 6: Chn Project Rebuild All hoc click vo biu
tng trn thanh cng c.
- Bc 7: Theo mc nh th file .out s c to ra ti th mc
cha Project. thay i ni cha file.out to ra ta chn bng
cch vo Project/build option/link..
- Bc 8: Chn Fileload Program. Chn file.out va to ra
v click Open.
- Bc 9: Chn ViewMixed Source/ASM. La chn ny s
cho php chng trnh to ra ng thi code C v cc on
code Assembly tng ng trong qu trnh chy.
64
- Bc 10: Chn DebugGo Main bt u thc thi chng
trnh t on chng trnh chnh. Qu trnh thc thi s dng li
on chng trnh chnh v n c ch ra bi k hiu
- Bc 11: Chn DebugRun chy chng trnh hoc l
click vo biu tng trn thanh cng c.
- Bc 12: Chn DebugHalt dng chng trnh.
5.4 La chn cu hnh hot ng Project:
nh ngha mt cu hnh hot ng ca chng trnh thit lp mc cc
ty chn xy dng project. Cc project c to ra vi 2 cu hnh mc nh l:
Debug v Release. Debug c dng g li chng trnh v Release to
to ra sn phm cui cng.
5.5 Thay i cu hnh hot ng ca project
Nh hnh sau:



Click vo Debug chn cu hnh hot ng ca project.
5.6 Add cu hnh hot ng mi cho project
- Bc 1: Chn ProjectConfiguration.
- Bc 2: Ca s Add Project Configuration xut hin.
- Bc 3: Khai bo tn ca cu hnh mi v chn la cc ty chn thch hp.
- Bc 4: Click OK ng add cu hnh mi...
65
5.7 Thay i tn s cho DSK.


5.8 im tm dng chng trnh khi chy (Breakpoint):
c dng nh du cc im dng khi thc thi chng trnh. N gip
chng ta chy v kho st ring tng on chng trnh. to im tm dng
chng trnh khi chy chng ta di chut ti im m chng ta mun chng trnh
s dng khi chy, click chut phi v chn Toggle Software Breakpoint nh
hnh di hoc n vo biu tng trn thanh cng c.

66
Khi gc mn hnh ti im nh du s xut hin du chm
nh hnh sau

Mun hy b im BreakPiont no th ta click p chut tri ln dng
lnh cha im y. Cn nu ta mun hu b tt c cc im BreakPoint th ta
click ln biu tng trn thanh cng c ca CCS.
5.9 im thm d ( Probe Point)
Trong CCS cch n gin nht truyn thng d liu gia host ( c th l
my tnh ni vi DSP ) v target ( DSP ) l dng Probe point. Chng ta s to ra
cc im ny bng cch di chut n v tr ta mun kho st qu trnh vo ra d
liu. Click chut phi v chn Toggle Software Probe point nh hnh v sau
hoc click ln biu tng trn thanh cng c ca CCS.
67


Khi y gc mn hnh s xut hin du hiu nh hnh di y.


Mun hy mt im Probe Point ta click chut phi ln v tr cha im
y v la chn nh hnh di. Cn nu mun hy tt c cc im Probe Point
th ta click ln biu tng trn thanh cng c ca CCS.
68



Mt hn ch khi s dng Probe point kho st qu trnh truyn thng
gia target v host l n ch cho php chng ta vo ra cc file hex nh dng l
file.dat
5.10 Ca s quan st hot ng ca chng trnh ( Watch Window )
Ca s ny kt hp vi Break point s cho chng ta quan st c cc
kt qu ca chng trnh khi n tm dng. Gi s xem kt qu ca mt bin
gane ti im chng trnh dng ta se khai bo gain vo trong ca s Watch1
nh hnh sau
69

Qua ca s ny chng ta cng c th bit kt qu cc gi tr ca mt
mng. Chng ta cng c th thay i gi tr tm thi ca bin khai bo mt cch
tm thi, y l Gain bng cch cho gi tr mi ti min Value. Khi chng
trnh s tip tc chy vi gi tr mi ca Gain l gi tr va khai bo.
5.11 Kt lun
Chng ny trnh by mt cch c bn qu trnh lm vi phn mm CCS t
vic to mt project mi ti vic s dng mt s cc cng c n gin thc
hin vic truyn thng gia host v target hoc kho st chng trnh ti cc
im ngt. chng sau chng ta s hiu r hn v cc cng c ny cng nh
lm quen v s dng cc cng c khc ca CCS qua vic thc hin mt s cc v
d n gin.











70
Chng 6. Bt u CCS vi mt s ng dng n gin
6.1 Gii thiu
chng trc chng ta bit cc bc c bn to mt chng trnh
cng vi cc cng c c bn m chng ta c th dng xy dng chng trnh
ca chng ta. chng ny chng ta s hiu r hn v chng thng qua cc v
d c th sau.
6.2 Chng trnh Led
Cch d nht bt u vi CCS l chy cc ng dng n gin vi DSK.
V d v n LED l v d d nht ta lm quen vi mi trng pht trin v
cu hnh cho DSK. Trc tin chng ta s copy th mc led theo ng dn
c:\ti\examples\dsk6416\bsl\ sang mt th mc khc lm vic m khng s lm
thay i chng trnh gc hin c. y ti chng trnh led th mc E:\Ny
luu\Dien tu vien thong\Do an tot nghiep\Tot nghiep\Cac chuong trinh\led.
- Khi chy n s nhp nhy n led#0 l 2.5 ln / 1s
- Thay i DIP Switch 3 s thay i trng thi ca Led#3.
thc hin chng trnh ta thc hin cc bc sau:
- M Project Open v chn file led.pjt trong ng dn E:\Ny
luu\Dien tu vien thong\Do an tot nghiep\Tot nghiep\Cac chuong
trinh\led.
- Click ReBuild All l biu tng trn thanh cng c bin
dch li chng trnh led ca chng ta. Chng ta se thy CCS
bo li. l do chng ta coppy chng trnh sang Folder khc
lm thay i ng dn tham chiu ti mt s file.h v file th
vin dsk6416bsl.lib ca chng trnh. sa li ny chng ta
vo folder C:\ti\c6000\dsk6416\include coppy cc file
dsk6416.h, dsk6416_led.h, dsk6416_dip.h v vo ng dn
C:\ti\c6000\dsk6416\lib coppy fle dsk6416bsl.lib vo folder
cha chng trnh led ca chng ta. y l cc file m CCS
cung cp sn cho chng ta. Trong c cc nh ngha cng nh
71
mt s lnh c CCS h tr chng ta dng trong chng
trnh m khng cn vit li. Sau khi coppy cc file ny chng
ta cn thay i li cc ng dn ti chng nh sau. Click Build
Opption nh hnh di.














72
- Ca s Build Opption xut hin. Trong Tab Compiler chn
PreProcessor Include Search Path ta nhp ng dn ti
folder cha Project ca chng ta l E:\Ny luu\Dien tu vien
thong\Do an tot nghiep\Tot nghiep\Cac chuong trinh\led nh
hnh sau








73
Chn Tab Linker chn Basic v trong Library Search Path ta
khai bo li ng dn nh hnh sau.


Click Ok kt thc vic khai bo li ng dn.
- Click ReBuid All bin dch li chng trnh. Ln ny chng
trnh c bin dch thnh cng.
- Chn File Load Program. Mt hp thoi m ra, chn file
led.out trong ng dn /debug/led.out.
- Chn Debug Run chy chng trnh. Led#0 bt u nhp
nhy.
- Chuyn DIP Switch #3 ln v xung ta s thy Led#3 thay i
trng thi theo.
- dng chng trnh ta chn Debug Halt.



74
xem code ca on chng trnh trn ta kick p vo file led.c. Ca s
cha on m ngun s xut hin cho chng ta lm vic nh hnh di.



Code ca chng trnh ny c vit trong ph lc 1.
6.2.1 M t v chng trnh led.c
Bt u bng hm main(). u tin ta gi hm DSK6416_init() v n
c to trong th vin BSL ( Board Support Library ). Th vin ny gip chng
ra d dng s dng cc thnh phn ca bo mch DSK. DSK6416_init() c gi
ra trc cc hm BSL khc. Cc hm trong th vin ny bt u bng DSK6416.
Cc hm ny trong th vin c tn l dsk6416bsl.lib.
6.2.2 Thay i chng trnh led.
Ta thay i tc nhp nhy ca n led bng cch thay i hm nh sau.
/* To nhp nhy vi thi gian sng v tt 200ms */
75
DSK6416_waitusec(200000);
Thnh: /* To nhp nhy vi thi gian sng v tt 100ms */
DSK6416_waitusec(100000);
Sau khi sa li chng trnh ta thc hin cc bc sau:
- Chn File Save lu chng trnh va thay i.
- Thc hin bin dch li chng trnh bng cch chn
Project Build.
- Ti li file led.out bng cch chn File Load Program
v chn /debug/led.out.
- Chn Debug Run chy chng trnh.
- Mun dng chng trnh li th chn Debug Halt.
6.3 Chng trnh hello.pjt
Chng trnh ny ch n gin hin th dng ch Hello World. u
tin chng ta s coppy folder hello1 theo ng dn C:\Program
Files\CCStudio_v3.1\tutorial\sim64xx sang mt v tr khc nhm trnh nhng
thay i khi lm vic. y ti coppy vo folder E:\Ny luu\Dien tu vien
thong\Do an tot nghiep\Tot nghiep\Cac chuong trinh. Sau chng ta m project
hello.pjt. S c mt thng bo hin ra nh hnh sau

Thng bo ny yu cu chng ta chn li ng dn cho file th vin
rts6400.lib. cho nhng ln khai bo sau c d dng vi vic tm kim v tr
file ny chng ta s coppy n t folder C:\Program
Files\CCStudio_v3.1\C6000\cgtools\lib vo folder ca chng ta v chn ng
dn vo folder ny.
Bin dch li chng trnh. Load file hello.out v cho chy chng ta s c
kt qu nh hnh sau.
76

Code ca chng trnh ny c vit ph lc 2.
6.4 V d vi chng trnh Maxminmath
Vi v d ny chng ta s bit cch t to cho mnh mt file th vin
( file.lib ) thc hin mt s chc nng no . Cch tham chiu vo file th vin
ny s dng cc hm chc nng vo chng trnh chnh ca chng ta. Cc
bc thc hin v d ny l.
- Bc 1: To ra folder MaxminMath cha chng trnh ca chng
ta.
- Bc 2: To cc file testapp.c v maxminvalue.c vi code c
cho ph lc 3. Trong maxminvalue cha hai hm l
minimumValue() v maximumvalue.c().
- Bc 3: To Project mi vi tn l maxminlibrary v chn dng
file c to ra l .lib nh hnh sau
77


Click Finish.
- Bc 4: Add file rts6400.lib, maximumvalue.c vo chng trnh.
- Bc 5: Click ReBuild All. File maximumvalue.lib c to ra
trong forlder \MaxminMath\maxminlibrary\Debug.
n y ta to ra c mt file th vin. File th vin ny c cha
on chng trnh tm gi tr ln nht ca mng. By gi chng ta s tin
hnh xy dng mt chng trnh v n s tham chiu n file th vin va c
to ra s dng hm chc nng maximumvalue() ca n. Cc bc khi to
- Bc 1: To project mi vi tn l mainapplication.pjt vi Project
Type l .out.
- Bc 2: Add file testapp.c v rts6400.lib vo chng trnh.
- Bc 3: ReBuild All chng trnh. S c thng bo li. Nguyn
nhn l do trong file testapp.c ta c gi cc hm maximumValue()
v minimumValue() trong th vin maximumvalue.lib nhng ta
cha Add n vo Project. By gi ta cn phi Add n vo chng
trnh ca chng ta.
- Bc 4: Load file mainapplication.out v chy th. Chng ta se c
kt qu hin ra nh hnh sau.
78

6.5 Chng trnh SineWave
V d ny thc hin vic truyn thng mc n gin gia host
v target bng cch dng Break Point v Probe Point. Chng trnh ny thc
hin np file sine.dat t my tnh vo trong DSP. D liu nhn c s c
DSP x l ( y ch n gin l nhn cc gi tr nhn c vi hng s gain = 5
) sau ta truyn kt qu ngc li cho my tnh. Kt qu ca qu trnh x l ny
s c lu li trn my tnh di dng file l bigSine.dat. Thc hin v d ny
thng qua cc bc sau:
- Bc 1: Click Open Project vo ng dn C:\Program
Files\CCStudio_v3.1\tutorial\sim64xx. M file sinewave.pjt.
- Bc 2: ReBuild All chng trnh v load file sinewave.out va
c to ra.
- Bc 3: M file ngun sine.c v nh du im Probe Point ti
dng dataIO() trong hm main() nh hnh sau
79


- Bc 4: Click File File I/O. Ca s File I/O xut hin nh hnh
di.


- Bc 5: Click Add File. Ca s File Input xut hin. Chng ta
chn ng dn ti folder sinewave v m file sine.dat.
- Bc 6: Click Add Probe Point ca s Break/Probe Ponts c
m ra nh hnh sau
80


Click chut ln dng sine.c line 30. trong trng Probe Point.
Trong trng Connect To chn FILE IN: E:\..\sine.dat nh hnh trn.
Click Replace v sau Click OK.
- Bc 7: Trong hp thoi FILE I/O ti trng Address g vo
currentBuffer.input v ti trng Length g vo s 100 nh hnh
di. Click OK.

- Bc 8: Click File File I/O. Click Tab File Output. Add file
bigsine.dat. Click Add Probe Point. Trong Probe Point click ln
81
sine.c line 30. trong trng Probe Point. Trong trng Connect
To chn FILE IN: E:\..\bigsine.dat. Click ln phm Add ta s c kt
qu nh hnh di.


- Bc 9: Trong hp thoi File I/O ti trng Address g
currentBuffer.output v ti trng Length g 100. Kt qu nh
hnh di.


Click OK.
82
- Bc 10: Click Run chy chng trnh.
- Bc 11: Click Haft dng chng trnh. Kim tra li file
bigsine.dat ta s thy dung lng ca n tng ln.
- Bc 12: Click view Watch Window. Trong Tab Watch1 g
currentBuffer.input. Cho chy chng trnh chng ta s c bng
sau.




Chng ta c th thy ngay cc gi tr ca mng currentBuffer.input
(currentBuffer.output) cc gi tr u vo v u ra. Chng ta c th
thay i tm thi cc gi tr ny chy chng trnh ca chng
ta.Vic ny s khng nh hng g ti file sine.dat gc.
83
6.6 Kt lun
Chng ny gip chng ta lm quen vi vic xy dng mt chng trnh,
g li v load n v chy. Chng ta cng bit cch to mt file th vin, cch
dng chng trong chng trnh ca chng ta. Chng ta cn c th thc hin
truyn thng mc n gin gia my tnh v target thng qua im d probe
point.




Chng 7 DSP/BIOS
7.1 Gii thiu
DSP/BIOS l mt thit k cho cc ng dng yu cu ng b thi gian
thc, truyn thng gia host-to-target cng vi cc cng c phn tch thi gian
thc. DSP/BIOS cung cp nhiu on tuyn c mc u tin khc nhau, tru
tng ha phn cng v phn tch thi gian thc.
DSP/BIOS c ng gi di dng cc module v c th lin kt vo
trong ng dng ca chng ta. Cc ng dng kt hp vi cc hm chc nng ny
ca DSP/BIOS ( trc tip hoc gin tip ) v chng s c tham chiu ti trong
ng dng. Thm vo , cng c DSP/BIOS cho php ti u ha kch thc v
tc bng cch v hiu ha cc tnh nng m chng ta khng s dng.
Chng ta c th s dng DSP/BIOS o c phn tch qu trnh lm vic
bng cch kho st ( probeb), phc ha (traced), v hin th trong min thi gian
thc. Cc chng trnh s dng DSP/BIOS Configuration Tool s tn dng c
kh nng a phn tuyn ( multi threading ) ca DSP/BIOS.
DSP/BIOS c tch hp vi Code Composer Studio, v c h tr hon
ton bi Texas Instruments.
84
Cc i tng trong DSP/BIOS c th cu hnh trn giao din ca
DSP/BIOS. Do s lm gim kch thc ca on code v ti u ha cu
trc d liu bn trong. DSP/BIOS API chun ho vic lp trnh trn DSP
cho mt s thit b ca TI v cung cp mt s cc cng c pht trin lp trnh
s dng n gin nhng rt hiu qu. Cc cng c ny lm gim yu cu v
thi gian lp trnh cho DSP. DSP/BIOS cung cp cc API chun , iu ny
cho php pht trin cc thut ton cung cp cc on code m cc on code
ny d dng c tch hp vo trong hm chc nng khc
7.2 Cc thnh phn ca DSP/BIOS
- DSP/BIOS API: Chng trnh bng ngn ng C hoc Assembly c
th c gi ra t 150 hm DSP/Bios API.
- DSP/BIOS Configuration: Bng cng c ny cho php bn khi to
v cu hnh cho DSP/Bios dng cho chng trnh ca bn.
- DSP/BIOS Analysis Tools: Ca s ny cho php bn c ci nhn tng
qut v hot ng thi gian thc.Vi d, chy ca s Graph s hin th
th hot ng ca cc on tuyn.
7.2.1 DSP/BIOS API
DSP/BIOS c thit k cho cc ng dng yu cu iu phi thi gian
thc v s ng b, truyn thng gia target-host hoc cng c thi gian thc.
DSP/BIOS cung cp nhiu module vi cc mc u tin khc nhau, cc cng
c cu hnh.
Cc chng trnh ng dng s dng DSP/BIOS bng cch gi ti API. Tt
c cc module cung cp bi DSP/BIOS c th gi ra bng ngn ng C. Di
y l mt s cc module thuc API quan trng c dng ti trong chng
trnh:
HST Host channel manager
IDL Idle function manager
LOG Event log manager
HWI Hardware interrupt manager
LCK Resource lock manager
85
MBX Mailbox manager
PIP Buffered pipe manager
PRD Periodic function manager
RTDX Real-time data exchange settings
SIO Stream I/O manager
SWI Software interrupt manager
TSK Multitasking manager
Bng 7.1 Cc module trong API c s dng trong chng trnh


7.2.2 DSP/BIOS Configuration
DSP/BIOS configuration cho php chng ta khi to v cu hnh cc c tnh
ca Dsp/Bios s dng cho chng trnh ca chng ta.
86

7.2.3 DSP/BIOS Analysis Tools
Cc cng c phn tch h tr cho mi trng CCS bng cch cho php
phn tch tnh thi gian thc ca cc ng dng DSP/BIOS. Ta c th gim st
trc quan mt ng dng DSP khi n ang chy vi s nh hng ln tnh thi
gian thc ca cc ng dng l nh nht. DSP/BIOS analysis tools c a vo
trong DSP/BIOS menu, th hin nh trong hnh di y:

87

Khc vi cc cng c debug truyn thng, cc cng c trn c m rng
thc thi chng trnh, iu ny yu cu chng trnh pha target phi cha cc
lnh thi gian thc. Bng vic s dng cc API v cc i tng, ngi pht
trin s t ng o c pha target bt gi v ti li cc thng tin thi gian
thc ln cho host thng qua DSP/BIOS analysis tools ca Code Composer
Studio.

88
7.3 Mt s v d
7.3.1 V d 1 Hellobios.pjt
chng trc ta lm vic vi v d hello.pjt, y l chng trnh
in ra li cho Hello World. v d ny ta s vit li v d in ra li cho Hello
World bng cch s dng cc hm DSP/BIOS API. Cc bc khi to chng
trnh ny nh sau:
- Bc 1: To project mi c tn l hellobios.pjt.
- Bc 2: To mt file cu hnh DSP/BIOS mi vi tn l
hellobios.cdb bng cch click vo File New DSP/BIOS
configuration. Ca s New hin ra. Chn dsk6416.cdb ( loi
DSK m chng ta lm vic ) v lick OK.


Ca s file DSP/BIOS s hin ra cho chng ta lm vic. Lu li file vi
tn l hellobios.cdb chng ta s c giao din nh hnh sau.
89


Add file hellobios.cdb va to ra vo project hellobios.pjt ca chng ta.
M rng project hellobios.pjt bn tri mn hnh lm vic s thy trong mc
DSP/BIOS xut hin file hellobios.cdb cn Generated Files s xut hin ba file
hellobioscfg.cmd, hellobioscfg.s62 v hellobios_c.c, ba file ny t ng c to
ra khi ta to file cu hnh hellobios.cdb .
90


- Bc 3: To ra file ngun hellobios.c vi on m c cho
trong ph lc 5. Add file ny vo chng trnh hellobios.pjt.
- Bc4: Click p ln file hellobios.cdb. M phn vng
Intrumentation. Click chut phi ln LOG-Event Log Manager
chn Insert LOG to ra mt i tng LOG nh hnh sau.

91
i tn i tng LOG mi ny thnh trace nh hnh sau.

- Bc 5: Rebiuld chng trnh. Load file hellobios.out va c
to ra. Nu chng ta ang cm dsk6416 vi my tnh th chng
trnh s c np v chy. Nhng nu chng ta ch m phng trn
phn mm th s c bo li. Nguyn nhn l do trong file cu hnh
hellobios.cdb t ng mc nh cho vic s dng RTDX cho
vic truyn thng host target thng qua cng kt ni USB theo
chun JTAG. chng trnh bin dch m khng c li chng
ta s sa li cu hnh RTDX nh sau. Click chut phi ln RTDX
v chn Properties nh hnh sau.

Mt ca s hin ra, trong trng RTDX Mode ta chn l Simulator nh hnh
di.
92

Rebuil All li ton b chng trnh. Load file hellobios.out v chy th.
- Bc 6: xem kt qu ca chng trnh. Click DSP/BIOS
Message Log.

Ca s Message Log hin ra, trn c dng ch Hello World nh hnh sau.

7.3.2 V d 2 Ledprd.pjt
Chng trnh ny s bt n led 3 sng nu nh cng tc s 3 c n,
ng thi nhp nhy n led 1.Cc bc thc hin chng trnh sau.
- Bc 1: To project mi c tn l ledprd.pjt.
93
- Bc 2: To file cu hnh ledprd.cdb v khai bo cc thuc cc
i tng PRD_blinkLED0 v PRD_blinkLED1 nh hnh di.

Khai bo cc thuc tnh ca cc i tng ny nh cc hnh sau.

Cu hnh cho RTDX ca ledprd.cdb nh trong v d trc.
- Bc 3: To file ngun ledprd.c vi code trong ph lc 6.
- Bc 4. Coppy cc file dsk6416.h, dsk6416_led.h, dsk6416_dip.h
vo th mc cha chng trnh ca chng ta. V chn li ng
dn cho cc file nh cc v d trc lm. ReBuild All v
load chng trnh chy.
94
7.3.3 Chng trnh x l tn hiu volume thc hin bng DSP
Chng trnh ny c s dng mt ngt mm gi hm x l
processing_SW. Hm ny thc hin vic sau: khi c d liu t my tnh truyn
ti, n s c ghi tm thi vo b m inp_input. Khi b m y n s to ra
mt ngt mm gi hm processing_SW(). ( iu ny thc hin bi hm
DataIO() ). Hm ny s l lung d liu nhn c v ghi n vo b m
inp_output.Trong hp thuc tnh ca n th priority l th t u tin ca ngt
tng ng. Thuc tnh mailbox dng iu khin ngt mm. y mi khi n
c gi tr bng 0 th ta s thc hin chc nng (function ) ca ngt ny. Do
maibox =10 nn chc nng ca ngt mm ny s c thc hin mt ln c sau
10ms.
Ch : Chng trnh ny nu c dng nhn lin tc cc gi d liu t
my tnh gi ti, sau x l trong hm processing ri truyn d liu i th
khng c v vic nhn d liu l lin tc trong khi qu trnh x l d liu ch
xy ra sau 10 chu k xung. iu ng ngha vi vic l c mt phn d liu
tng ng vi 9 chu k xung b mt di ( Nguyn nhn chnh l do ta chn
mailbox=10. c th truyn c d liu lin tc ta phi chn mailbox=1 hoc
l s dng cc lnh khc gi trc tip ngt mm ).
v d ny vic truyn thng gia my tnh v DSP c thc hin qua
im probe point. Probe point l mt phng thc cho php truyn thng gia
my tnh v DSP mc n gin. Cc chng sau s trnh by cc k thut
truyn thng linh hot v thng c s dng trong thc t.
Cc bc thc hin v d ny l :
- Bc 1: To project volume.pjt. To file volume.cdb vi cu hnh
nh cc hnh v sau.
95

Trong ta khai bo thm i tng Log trace nh v d trc.
Ngt mm processing_SWI c khai bo cc thuc tnh nh sau.

Trong RTDX ta l simulator.
Add file cu hnh volume.cdb vo project ca chng ta.
- Bc 2: To file ngun volume.c, volume.h v load.asm. Trong
file volume.h cha cc nh ngha v khai bo cc hng s c
96
dng trong chng trnh ca chng ta. Cn file load.asm c vit
di dng ngn ng assemply, n thc hin chc load(). Code ca
cc chng trnh ny c trong ph luc 7. Add cc file ny vo
chng trnh volume.pjt.
- Bc 3: Coppy cc file th vin v sa li ng dn cho chng
trnh. ReBuil All v load chng trnh chy.
7.4 Kt lun
chng ny gip chng ta c ci nhn tng quan v DSP/BIOS. Cch
to ra mt file cu hnh, cch s dng mt s cc cng c c h tr bi
DSP/BIOS. Chng ta cng t xy dng cho mnh c mt s cc ng dng n
gin. So snh vi cc chng trnh c vit thng thng chng ta thy c
rng chng trnh vit qua DSP/BIOS cho php chng ta gim c ng k kch
c ca chng trnh.
97
Chng 8 K thut truyn thng
8.1 Gii thiu
Mt vn quan trng khi xy dng cc ng dng trn DSP l s
truyn thng gia chng nh th no? Cch xy dng cc chng trnh cho php
thc hin qu trnh truyn thng gia cc DSP vi nhau. Chng ny s gip
chng ta hiu r hn v iu
8.2 iu phi truyn thng vi b m Ping pong
mc cao th mch iu khin EDMA c tn hiu audio t McBSP v
lu n vo b nh m. D liu nhn c c lu trong hai b m logic
cnh nhau l Ping v Pong. Ban u d liu n s c lu trong b m Ping.
Khi n y th d liu ti s c gi ti b m Pong, trong khi DSP s x l
d liu trong b m Ping m khng s n b ghi ln. Khi m Pong y th
Ping Pong s c cu hnh ngc li. Nu ch c mt b m c dng th
Dsp s x l tt c d liu trn b m trong khong thi gian t khi b m y
cho n khi mu tn hiu tip theo c nhn. Khi c hai b m c dng th
Dsp s c nhiu thi gian hn x l lung d liu nhn c v iu ny s
gip cho h thng gn vi thi gian thc hn. Tng t ta cng c hai b m
Ping Pong tch bit cho qu trnh truyn d liu.
Nh vy l ta c tt c 4 b m tch bit. 2 Ping v 2 Pong. Trong
1 cp Ping Pong cho nhn v mt truyn.
Int16 gBufferRcvPing[BUFFSIZE]; // Transmit PING buffer
Int16 gBufferRcvPing[BUFFSIZE]; // Transmit PONG buffer
Int16 gBufferRcvPong[BUFFSIZE]; // Receive PING buffer
Int16 gBufferRcvPong[BUFFSIZE]; // Receive PONG buffer
8.3 S dng lin kt EDMA ( Linked EDMA transfers )
Khi EDMA kt thc pha Ping v cn chuyn sang pha Pong. Con tr
ngun v ch cn phi c tr ti v tr b m mi. Khi lin kt truyn c
dng, a ch mi c th c lu tr trong cu trc cu hnh kt ni ( links
98
configuration structure ) v c t ng np vo bi mch iu khin EDMA
khi hon thnh qu trnh truyn. Vic cu hnh li cng c th c qun l bi
Dsp bng cc ngt mm v kt ni truyn ny s c b i khi kt thc ngt
mm trc khi mu tn hiu tip theo c nhn tn hiu audio c lin tc.
Trong mt ng dng, khi chng trnh chy, cc module DSP/BIOS ring
r s thc hin khi to qu trnh cu hnh vi cng c cu hnh DSP/BIOS. Hm
chnh c gi ti v thc hin cc on chng trnh khc. Trong v d ny
main() thc hin khi to v bt u EDMA truyn d liu. Khi hm main kt
thc, iu khin c chuyn cho Dsp/Bios phc v cc ngt hoc cc on
chng trnh c bn cn thit. Khi khng c cng vic g c thc thi th on
chng trnh rng c thc hin. Ngt EDMA s c dnh quyn u tin
trong vng on chng trnh rng
8.4 c im ca lung d liu truyn:
Tn hiu vo theo 2 knh l tri v phi. D liu nhn c trong mi
frame gm 2 phn: 16 bit t knh tri v 16 bt tip sau l knh phi. Cc
khung c nhn tc tc mc nh bi Dsp l 48 kHz
99
.


8.5 EDMA kt hp vi McBSP :
S dng EDMA v McBSP qun l b nh m khng c s can thip t
Dsp.
McBSP1 ( L mt cng ni tip ) c dng cu hnh v iu khin
AIC23. AIC23 s nhn lin tip cc lnh thng qua McBSP1 cu hnh cc
thng s nh l ln, tc mu v nh dng ca mu tn hiu.
McBSP2 l cng ni tip 2 chiu. EDMA s cu hnh cho cc mu d liu
truyn thng trn McBSP2. Khi McBSP2 nhn d liu n s c lu vo vng
b nh m ch s l. Trong qu trnh truyn EDMA gi data ngc li
McBSP2.
100
Trong qu trnh x l tn hiu. Khi mt b m Ping hoc Pong y th
EDMA s to ra mt ngt. Ngt ny s thc hin vic cu hnh li cho b m
tip theo trc khi mu tn hiu tip theo c nhn. EDMA to ra lin kt
truyn ny trong mt khong thi gian gii hn.EDMA s t ng lin kt ti
cu hnh tip theo khi mt qu trnh cu hnh hon thnh.
8.6 Hot ng ca chng trnh:
Khi chng trnh chy th module DSP/BIOS c gi ra trc tin
thc hin cu hnh cho h thng. Sau th on chng trnh main() s c
thc hin s l cc on chng trnh ca ngi s dng. Trong v d Dsp.app
m ta s thc hin sau y th n thc hin chy ng dng bng vic khi to v
bt u chy EDMA truyn d liu. Khi hm main kt thc th iu khin
c chuyn hon ton cho DSP/BIOS phc v cc ngt hoc cc on
chng trnh c bn cn thit.
Ngt thng trnh Edma_Hwi() c gi ra khi mt b m y. N gm
bin trng thi PingOrPong ch ra rng b m ang c dng n l b m
Ping hay l Pong. Edma_Hwi() s chuyn trng thi b m sang b m tip
theo v gi ngt mm (SWI) processBuffer x l tn hiu audio data.
8.7 Cu hnh EDMA ( EDMA configuration manager):
8.7.1 Thm i tng cu hnh EDMA:

101


C ti a 16 i tng cu hnh c th c s dng cng mt
lc.
8.7.2 nh dng trng a ch ( Specifying Address Formats)
a ch ngun v ch c thit lp theo mt trong 4 cch sau:
Numeric, Extern Declaration Object (Extern Decl. Obj.), Users Header file, and
McBSP handle.
- Numeric: a ch kiu hexa.
- Extern Declaration Object ( Cc i tng nh ngha
ngoi ): s dng cch ny chng ta tin hnh theo cc bc
sau:
- B1: Khai bo tn k hiu cn dng mc CSL Extern
Declaration.Chng hn y ta dng tn l Ping.
102





- B2: Khai bo cc thuc tnh ca i tng Ping tng
ng:
103


Trong ping in trong mc Symbol Name chnh l tn ca
i tng c nh ngha.
- B3: Khai bo a vo cu hnh EDMA nh hnh sau :


104
- Ch : i tng ping s dng y phi c nh
ngha t nht l mt ln trong on chng trnh ca chng
ta nu khng chng trnh s b li khi ta bin dch.
- Users Header file: K t c nh ngha trong file header
c th c s dng nh l mt a ch ch hoc a ch ngun.
Khi Users Header file c la chn th trng Enter full
address s c dng ti. dng cch ny ta cn tun theo cc
bc sau:
- B1: To ra mt file.h chng hn file myfile.h sau:
// myfile.h
#define BUFFSIZE 256
#define myESIZE 0x0004 //element size of 4 bytes
Uint32 myBuffer[BUFFSIZE];
- B2: Khai bo cu hnh c th s dng file.h ny nh
hnh :

105


- B3: S dng trong cu hnh EDMA :

106
8.7.3 McBSP handle (DRR) or (DXR):
Cho php thanh ghi truyn v nhn McBSP c cu hnh nh l a ch
ch hoc a ch ngun. Cng ni tip McBSP thng c dng nh l ngun
hoc ch cho qu trnh truyn EDMA. V d, nu b ADC c kt ni ti mt
McBSPs, EDMA c th c dng chuyn cc mu tn hiu s vo trong b
nh trong chip x l. Trong trng hp ny, a ch ngun EDMA cn c
thit lp l a ch thanh ghi nhn McBSP ( DRR ). Thuc tnh qun l b nh
McBSP c cung cp
s dng thuc tnh qun l b nh McBSP ta thc hin theo cc bc sau:
- B1: Ch nh McBSP bng cch click chut phi ln mt cng
McBSP ( Tm thy di cy MsBSP Resource Manager CSL tree
) v chn Properties. Click Open McBSP port v nh ngha tn
qun l b nh trong text box tng ng. Click OK lu li s
thay i v close.
- B2: M i tng cu hnh EDMA kt hp vi McBSP.
- B3: Chn tab Source hoc Destination ca cu hnh EDMA.
- B4: Nu cu hnh l a ch ngun, chn McBSP handle ( DRR )
t trng nh dng a ch ngun.Tng t i vi a ch ch.
- B5: Khi nh dang qun l b nh McBSP c chn, trng
Enter Handle Name s c dng. Nhp tn qun l chn trong
cc tn c trc bc 1.
Ch : Tn qun l b nh c dng trong trng Enter Handle Name
phi ng chnh xc vi tn McBSP nu khng s xy ra li khi bin dch.
V d:
Thc hin theo qu trnh ADC->McBSP ->DMA nh m t v qun l b
nh McBSP (DRR) m t trn.
- Step 1 : M cng MCBSP v nh ngha truy qun l b nh.M t
nh cc hnh di.

107





108
- Steps 2-5: M cu hnh EDMA tab Source, chn dng qun l
b nh McBSP v nhp tn qun l b nh.



8.7.4 S khung truyn v ch s khung ( Transfer Count and Index Setting )
Bao gm Frame count ( Thanh ghi m s khung truyn ) v element count (
Thanh ghi m cc element c truyn ).
Gi tr thanh ghi count c th c thit lp bng 2 cch:
- C1: Gi tr dng Hexa. Gi tr ny c th khai bo gin tip trn
tab Advanced ca EDMA configuration.
- C2: Users Header file:
Ch :
- Header file c th c tham chiu di CSL Extern Declaration.
- K t phi c nh ngha trong chng trnh nu khng s c li
khi bin dch.
109
- Nu bn tham chiu file header trong nhng file C khc, phi cn
thn khi nh ngha cc bin ton cc nhiu ln.#IFDEF c th c
s dng ngn chn li ny.
8.7.5 Thit lp s khung truyn s dng file header (Transfer Count
Register Setting using the Users Header File)
S dng k t t file header c th rt tin li. V d, header file c th c
nh ngha mt k t chng hn nh BUFFSIZE trong file header nh sau:
// myfile.h
#define BUFFSIZE 256
#define myESIZE 0x0004 //element size of 4 bytes
Uint32 myBuffer[BUFFSIZE];
File ny ging file header myfile.h m ta to ra t trc.
Trong v d ny, gi tr BUFFSIZE c cu hnh cho thnh phn element count
ca EDMA configuration. Cu hnh EDMA s truyn s BUFFSIZE cho
element.

110

Ngoi ra v d ny cng nh ngha myESIZE thit lp ch s element index (
EIX )( N m t khong cch m con tr s di chuyn sau mi ln truyn ).



Transfer Count page/tab: FRAME counter ( FC ) khng c dng ti
(NULL); ELEMENT counter (EC) c thit lp l BUFFSIZE.
Index page/tab: Element index c thit lp l mySIZE.
8.7.6 Thit lp a ch lin kt ( Link address setting)
Gi tr thanh ghi reload/link c th c thit lp bng 2 cch khc nhau: table
number v table handle:
- Table Number: S dng bng s chuyn dng Reload/Link.
111
- Table Handle: ng hn l bng s chuyn dng hardcode,
tn bng qun l b nh ( Table Handle ) chuyn dng c t
danh sch drop-down, nh hnh di.
8.7.7 Thit lp bng Table Number:
Cc bng s c dng trong phm vi t 0 n 18. Bng 0 c a ch l
0X01A00630. Mt khc, thc t c 20 bng nhng hai bng u tin ( c a ch
l 0X01A0060 v 0X01A00618 ) l c dnh ring v ngi s dng khng
can thip vo chng. (Hm EDMA_allocaTable() s cho chng ta cc thng tin
chi tit v bng table Number m chng ta s dng )
Ta s dng Table Number trong cu hnh EDMA nh sau:



Thit lp gi tr thanh ghi Reload/Relink bng cch la chn bng Table
Handle: Tin hnh theo hai bc sau:
- B1: To bng Reload/Relink nh hnh sau:
112



Rename tn Table handle.
Khai bo thuc tnh ca bng Table handle va to nh hnh sau:


113

- B2: T hp thoi cu hnh ca EDMA ta khai bo nh sau:


8.7.8 Cu hnh EDMA bng cc lnh trong file ngun.
Chng ta cng c th cu hnh EDMA bng cc lnh trong file ngun (
file.c ) ca chng trnh. Chng ta s hc cch cu hnh ny thng qua v d mu
sau y.

EDMA_Config gEdmaConfigXmt ={
EDMA_FMKS(OPT, PRI, HIGH) | // Mc u tin l High
EDMA_FMKS(OPT, ESIZE, 16BIT) | // Kch thc mt mu truyn l 16 bt
EDMA_FMKS(OPT, 2DS, NO) | // 2 dimensional source?
EDMA_FMKS(OPT, SUM, INC) | // Dng update a ch ngun l INC
EDMA_FMKS(OPT, 2DD, NO) | // 2 dimensional dest
EDMA_FMKS(OPT, DUM, NONE) | // Dng update a ch ch l None
EDMA_FMKS(OPT, TCINT, YES) | // C dng ngt EDMA khng ? Yes
EDMA_FMKS(OPT, TCC, OF(0)) | // C truyn TCC
EDMA_FMKS(OPT, LINK, YES) | // Cho php lin kt cc tham s.
EDMA_FMKS(OPT, FS, NO), // S dng ng b khung ?
114

(Uint32)&gBufferXmtPing, // a ch ngun.

EDMA_FMK (CNT, FRMCNT, NULL) | // S khung truyn mi ln
EDMA_FMK (CNT, ELECNT, BUFFSIZE), // S element truyn mi ln

EDMA_FMKS(DST, DST, OF(0)), // a ch ch

EDMA_FMKS(IDX, FRMIDX, DEFAULT) | // Ch s khung
EDMA_FMKS(IDX, ELEIDX, DEFAULT), // Ch s element

EDMA_FMK (RLD, ELERLD, NULL) | // Reload element
EDMA_FMK (RLD, LINK, NULL) // Reload link
};
y l cu hnh cho truyn d liu cn nhn c th c cu hnh nh on
code sau:

EDMA_Config gEdmaConfigRcv ={
EDMA_FMKS(OPT, PRI, HIGH) | // Priority
EDMA_FMKS(OPT, ESIZE, 16BIT) | // Element size
EDMA_FMKS(OPT, 2DS, NO) | // 2 dimensional source?
EDMA_FMKS(OPT, SUM, NONE) | // Src update mode
EDMA_FMKS(OPT, 2DD, NO) | // 2 dimensional dest
EDMA_FMKS(OPT, DUM, INC) | // Dest update mode
EDMA_FMKS(OPT, TCINT, YES) | // Cause EDMA interrupt?
EDMA_FMKS(OPT, TCC, OF(0)) | // Transfer complete code
EDMA_FMKS(OPT, LINK, YES) | // Enable link parameters?
EDMA_FMKS(OPT, FS, NO), // Use frame sync?

EDMA_FMKS(SRC, SRC, OF(0)), // Src address

EDMA_FMK (CNT, FRMCNT, NULL) | // Frame count
EDMA_FMK (CNT, ELECNT, BUFFSIZE), // Element count

115
(Uint32)&gBufferRcvPing, // Dest address

EDMA_FMKS(IDX, FRMIDX, DEFAULT) | // Frame index value
EDMA_FMKS(IDX, ELEIDX, DEFAULT), // Element index value

EDMA_FMK (RLD, ELERLD, NULL) | // Reload element
EDMA_FMK (RLD, LINK, NULL) // Reload link
};
8.8 McBSP ( Multichannel Buffered Serial Port )
McBSP bao gm McBSP1 v McBSP2. Trong McBSP1 ( L mt cng
ni tip ) c dng cu hnh v iu khin AIC23. AIC23 s nhn lin tip
cc lnh thng qua McBSP1 cu hnh cc thng s nh l ln, tc mu
v nh dng ca mu tn hiu. McBSP2 l cng ni tip 2 chiu. EDMA s cu
hnh cho cc mu d liu truyn thng trn McBSP2. Khi McBSP2 nhn d liu
n s c lu vo vng b nh m ch s l. Trong qu trnh truyn EDMA
gi data ngc li McBSP2.
Ngi ta c th cu hnh cho McBSP thng qua hai cch:
- Cch 1: Cu hnh da vo h tr ca cng c McBSP configuration
manager y l mt cng c cho php ta cu hnh McBSP gin tip
trn file cu hnh thng qua cc la chn theo giao din nh hnh sau
116

- Cch 2: Cu hnh thng qua cc on m trong file ngun nh l on
cu hnh mu di y.

MCBSP_Config mcbspCfg2 ={
MCBSP_FMKS(SPCR, FREE, NO) |
MCBSP_FMKS(SPCR, SOFT, NO) |
MCBSP_FMKS(SPCR, FRST, YES) |
MCBSP_FMKS(SPCR, GRST, YES) |
MCBSP_FMKS(SPCR, XINTM, XRDY) |
MCBSP_FMKS(SPCR, XSYNCERR, NO) |
MCBSP_FMKS(SPCR, XRST, YES) |
117
MCBSP_FMKS(SPCR, DLB, OFF) |
MCBSP_FMKS(SPCR, RJUST, RZF) |
MCBSP_FMKS(SPCR, CLKSTP, DISABLE) |
MCBSP_FMKS(SPCR, DXENA, OFF) |
MCBSP_FMKS(SPCR, RINTM, RRDY) |
MCBSP_FMKS(SPCR, RSYNCERR, NO) |
MCBSP_FMKS(SPCR, RRST, YES),

MCBSP_FMKS(RCR, RPHASE, SINGLE) |
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RCOMPAND, MSB) |
MCBSP_FMKS(RCR, RFIG, NO) |
MCBSP_FMKS(RCR, RDATDLY, 0BIT) |
MCBSP_FMKS(RCR, RFRLEN1, OF(1)) |
MCBSP_FMKS(RCR, RWDLEN1, 16BIT) |
MCBSP_FMKS(RCR, RWDREVRS, DISABLE),

MCBSP_FMKS(XCR, XPHASE, SINGLE) |
MCBSP_FMKS(XCR, XFRLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XWDLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XCOMPAND, MSB) |
MCBSP_FMKS(XCR, XFIG, NO) |
MCBSP_FMKS(XCR, XDATDLY, 0BIT) |
MCBSP_FMKS(XCR, XFRLEN1, OF(1)) |
MCBSP_FMKS(XCR, XWDLEN1, 16BIT) |
MCBSP_FMKS(XCR, XWDREVRS, DISABLE),

MCBSP_FMKS(SRGR, GSYNC, DEFAULT) |
MCBSP_FMKS(SRGR, CLKSP, DEFAULT) |
MCBSP_FMKS(SRGR, CLKSM, DEFAULT) |
MCBSP_FMKS(SRGR, FSGM, DEFAULT) |
MCBSP_FMKS(SRGR, FPER, DEFAULT) |
MCBSP_FMKS(SRGR, FWID, DEFAULT) |
118
MCBSP_FMKS(SRGR, CLKGDV, DEFAULT),

MCBSP_MCR_DEFAULT,
MCBSP_RCERE0_DEFAULT,
MCBSP_RCERE1_DEFAULT,
MCBSP_RCERE2_DEFAULT,
MCBSP_RCERE3_DEFAULT,
MCBSP_XCERE0_DEFAULT,
MCBSP_XCERE1_DEFAULT,
MCBSP_XCERE2_DEFAULT,
MCBSP_XCERE3_DEFAULT,

MCBSP_FMKS(PCR, XIOEN, SP) |
MCBSP_FMKS(PCR, RIOEN, SP) |
MCBSP_FMKS(PCR, FSXM, EXTERNAL) |
MCBSP_FMKS(PCR, FSRM, EXTERNAL) |
MCBSP_FMKS(PCR, CLKXM, INPUT) |
MCBSP_FMKS(PCR, CLKRM, INPUT) |
MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT) |
MCBSP_FMKS(PCR, DXSTAT, DEFAULT) |
MCBSP_FMKS(PCR, FSXP, ACTIVEHIGH) |
MCBSP_FMKS(PCR, FSRP, ACTIVEHIGH) |
MCBSP_FMKS(PCR, CLKXP, FALLING) |
MCBSP_FMKS(PCR, CLKRP, RISING)
};
on m trn cu hnh cho McBSP2. cu hnh cho McBSP1 ta c th
dng on m nh sau.

MCBSP_Config mcbspCfg1 ={
MCBSP_FMKS(SPCR, FREE, NO) |
MCBSP_FMKS(SPCR, SOFT, NO) |
MCBSP_FMKS(SPCR, FRST, YES) |
MCBSP_FMKS(SPCR, GRST, YES) |
119
MCBSP_FMKS(SPCR, XINTM, XRDY) |
MCBSP_FMKS(SPCR, XSYNCERR, NO) |
MCBSP_FMKS(SPCR, XRST, YES) |
MCBSP_FMKS(SPCR, DLB, OFF) |
MCBSP_FMKS(SPCR, RJUST, RZF) |
MCBSP_FMKS(SPCR, CLKSTP, NODELAY) |
MCBSP_FMKS(SPCR, DXENA, OFF) |
MCBSP_FMKS(SPCR, RINTM, RRDY) |
MCBSP_FMKS(SPCR, RSYNCERR, NO) |
MCBSP_FMKS(SPCR, RRST, YES),

MCBSP_FMKS(RCR, RPHASE, DEFAULT) |
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RCOMPAND, DEFAULT) |
MCBSP_FMKS(RCR, RFIG, DEFAULT) |
MCBSP_FMKS(RCR, RDATDLY, DEFAULT) |
MCBSP_FMKS(RCR, RFRLEN1, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN1, DEFAULT) |
MCBSP_FMKS(RCR, RWDREVRS, DEFAULT),

MCBSP_FMKS(XCR, XPHASE, SINGLE) |
MCBSP_FMKS(XCR, XFRLEN2, OF(0)) |
MCBSP_FMKS(XCR, XWDLEN2, 8BIT) |
MCBSP_FMKS(XCR, XCOMPAND, MSB) |
MCBSP_FMKS(XCR, XFIG, NO) |
MCBSP_FMKS(XCR, XDATDLY, 1BIT) |
MCBSP_FMKS(XCR, XFRLEN1, OF(0)) |
MCBSP_FMKS(XCR, XWDLEN1, 16BIT) |
MCBSP_FMKS(XCR, XWDREVRS, DISABLE),

MCBSP_FMKS(SRGR, GSYNC, FREE) |
MCBSP_FMKS(SRGR, CLKSP, RISING) |
MCBSP_FMKS(SRGR, CLKSM, INTERNAL) |
120
MCBSP_FMKS(SRGR, FSGM, DXR2XSR) |
MCBSP_FMKS(SRGR, FPER, OF(0)) |
MCBSP_FMKS(SRGR, FWID, OF(19)) |
MCBSP_FMKS(SRGR, CLKGDV, OF(99)),

MCBSP_MCR_DEFAULT,
MCBSP_RCERE0_DEFAULT,
MCBSP_RCERE1_DEFAULT,
MCBSP_RCERE2_DEFAULT,
MCBSP_RCERE3_DEFAULT,
MCBSP_XCERE0_DEFAULT,
MCBSP_XCERE1_DEFAULT,
MCBSP_XCERE2_DEFAULT,
MCBSP_XCERE3_DEFAULT,

MCBSP_FMKS(PCR, XIOEN, SP) |
MCBSP_FMKS(PCR, RIOEN, SP) |
MCBSP_FMKS(PCR, FSXM, INTERNAL) |
MCBSP_FMKS(PCR, FSRM, EXTERNAL) |
MCBSP_FMKS(PCR, CLKXM, OUTPUT) |
MCBSP_FMKS(PCR, CLKRM, INPUT) |
MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT) |
MCBSP_FMKS(PCR, DXSTAT, DEFAULT) |
MCBSP_FMKS(PCR, FSXP, ACTIVELOW) |
MCBSP_FMKS(PCR, FSRP, DEFAULT) |
MCBSP_FMKS(PCR, CLKXP, FALLING) |
MCBSP_FMKS(PCR, CLKRP, DEFAULT)
};
8.9 Cu hnh cho khi Codec AIC23
s dng khi codec ny trong truyn thng ta cng cn phi cu hnh
cho n. Chng ta s cu hnh cho khi codec ny bng on m sau.

121
DSK6416_AIC23_Config config ={ \
0x0017, /* 0 DSK6416_AIC23_LEFTINVOL Left line input channel volume */ \
0x0017, /* 1 DSK6416_AIC23_RIGHTINVOL Right line input channel volume */\
0x01f9, /* 2 DSK6416_AIC23_LEFTHPVOL Left channel headphone volume */ \
0x01f9, /* 3 DSK6416_AIC23_RIGHTHPVOL Right channel headphone volume */
\
0x0011, /* 4 DSK6416_AIC23_ANAPATH Analog audio path control */ \
0x0000, /* 5 DSK6416_AIC23_DIGPATH Digital audio path control */ \
0x0000, /* 6 DSK6416_AIC23_POWERDOWN Power down control */ \
0x0043, /* 7 DSK6416_AIC23_DIGIF Digital audio interface format */ \
0x0001, /* 8 DSK6416_AIC23_SAMPLERATE Sample rate control */ \
0x0001 /* 9 DSK6416_AIC23_DIGACT Digital interface activation */ \
};
8.10 Mt s v d
8.10.1 Tone.pjt
V d ny thc hin vic gi mt tn hiu sine ra ng line out ca cc
DSP. Tn hiu sine ny c to ra t bn trong chng trnh ca chng ta.
Chng ta xy dng chng trnh ny thng qua cc bc sau:
- Bc 1: To ra project vi tn l tone.pjt.
- Bc 2: To file cu hnh tone.cdb. Chng ta khng cn thay i thuc
tnh gi t file ny ( ch c trng RTDX l chng ta phi la chn l
J TAG hay simulator ph thuc vic chng ta ang lm vic trc tip
trn DSK hay l ang lm vic vi phn mm m phng.) Add file ny
vo chng trnh ca chng ta.
- Bc 3: To file tone.c vi code cho ph lc 8. Add file ny vo
chng trnh ca chng ta.
- Bc 4: Coppy cc file th vin. Chn li ng dn v ReBuild All
chng trnh. Load file tone.out v chy th. Nu chng ta ang lm
vic vi DSK6416, khi cm loa vo ng mic out ca DSK chng ta
s thy ting r r. iu y cho thy chng trnh ca chng ta lm
vic tt.
122
8.10.2 Dsp_app
Chng trnh ny thc hin nhn lung d liu vo qua ng line input
ca codec AIC23 v chy kt qu trn ng line output ca codec. N thc hin
chy ng dng bng vic khi to v bt u chy EDMA truyn d liu. Khi
hm main kt thc th iu khin c chuyn hon ton cho DSP/BIOS phc
v cc ngt hoc cc on chng trnh c bn cn thit.Ngt thng trnh
Edma_Hwi() c gi ra khi mt b m y. N gm bin trng thi
PingOrPong ch ra rng b m ang c dng n l b m Ping hay l
Pong. Edma_Hwi() s chuyn trng thi b m sang b m tip theo v gi
ngt mm (SWI) processBuffer x l tn hiu audio data. Tng ng vi qu
trnh truyn nhn th cc n led trn DSK6416 cng nhp nhy. Ngoi ra
chng trnh cn thay i tc load khi ta thay i trng thi ca cng tc 1(
dip 1). Cc bc thc hin v d ny nh sau.
- Bc 1: to ra chng trnh dsk_app.pjt
- Bc 2: to file cu hnh dsk_app.cdb v khai bo cc i tng nh
sau:
PRD_blinkLED0.


PRD_load

123

Ngt mm processBufferSwi



124
Ngt cng HWI_INT8





Add file cu hnh ny vo chng trnh ca chng ta.
- Bc 3: To file ngun dsk_app.c, aic23.c v aic23.h, trong
dsk_app cha chng trnh chnh cn aic23.c ch n gin nh l mt
hm chc nng khi to AIC23 cho qu trnh truyn thng cn
125
aic23.h nh ngha mt s cc cu trc, hng s dng trong file
aic23.c vi code ca cc file ny c cho ph lc
- Bc 4: ReBuild All chng trnh. Load file dsk_app.out v chy th.
chy th chng trnh ny chng ta c th ly tn hiu vo line input ca
DSK t ng line ca my tnh. Cho ng line out ca DSK ny cm vo
ng line input ca mt DSK khc v chng ta s cho tn hiu t ng line
ouput ca DSK th hai ny qua loa. Khi chng ta ng thi chy mt file nhc
trn my tnh v chy cc chng trnh dsk_app ny trn c hai DSK chng ta s
nghe c nhc loa. Tn hiu nhc chng ta nghe c loa chc chn l s
khng th c cht lng nh file nhc gc. y l do b nh hng bi nhiu, do
suy hao trn ng trn hoc l do qu trnh x l tn hiu cha c ti u trn
DSP gy ra.
8.11 Kt lun
Chng ny cho chng ta hiu r qu trnh truyn thng thc hin gia
cc DSP nh th no. Cch xy dng chng trnh thc hin qu trnh truyn
thng. Trong chng ny chng ta cng bit c cch cu hnh cc thnh phn
nh EDMA, McBSP cn thit s dng trong chng trnh ca chng ta.







126
Chng 9 Truyn thng gia host v target
RTDX (Real-Time Data Exchange)
9.1 Gii thiu
Chng trc chng ta hiu v xy dng cc chng trnh thc hin
c qu trnh truyn thng gia cc DSP. chng ny chng ta s hiu thm
v cch truyn thng gia DSP ( target ) vi my tnh ( host ). T y xy dng
mt s chng trnh thc hin qu trnh truyn thng ny.
9.2 Chng trnh ng dng trn target (Target Application)
RTDX cho php chng trnh DSP truyn thng gia thit b DSP v my
ch (my tnh) trong cc ng dng ca DSP.
Hnh di m t dng d liu truyn gia target v host. Khi truyn d liu
gia target ti host th knh output s c m trn target. Khi d liu c ghi
ti knh ny th thc cht l n c ghi ti ghi ti mt b m c thit lp
trong th vin RTDX target. B m ny s gi ti host bi th vin RTDX
thng qua giao tip JTAG. Trn my tnh host d li c nhn v c vit ti
b m hoc l ti mt file no . Mt ng dng trn host c th s dng d
liu trong b m s dng th vin RTDX host gi ra.
gi d liu t host ti target, target phi m knh input. Target s yu cu
d liu t knh input v th vin RTDX target s gi yu cu ny thng qua giao
tip JTAG ti th vin host. Mt ng dng trn host s vit d liu ti b m
host v th vin RTDX host ( RTDX host library) s gi d liu ti target thng
qua giao tip JTAG.

Hnh 9.1 Dng d liu gia RTDX host v target.
127
C 2 cch RTDX nhn nhn d liu t ng dng target application:
- Dng lin tc- Trong cch ny d liu s c ghi ti b m mt ln v
lin tc vit ti ng dng target. S dng cch ny nu chng ta mun lin
tc gi v nhn d liu hoc khng cn lu d liu ti file.
- Dng khng lin tc- Cch ny dng vit d liu ti mt file trn host.
N c th c dng vit mt lng d liu khng gii hn ti file.
cu hnh RTDX ta m RTDX Configuration Tool bng cch la chn
Tools->RTDX->Configuration Control. N s m ca s hin th cc thit lp
cho RTDX.
thay i cc ci t bn phi chc chn rng RTDX c v hiu
ha. Right click trn ca s v chn Property Page. y bn c th la chn
kch thc ca b m.
Cc bc cn thit to v tr trong ng dng target cho vic nhn v gi
data t host:
- Tham chiu ti file header rtdx.h.
- Cng b knh vo v ra ton cc cho vic truyn v nhn d liu. Cc
knh l cc cu trc d liu c cng b trong cc lnh sau. Knh name l
input v c th c tn khc.

RTDX_CreateInputChannel( name );
RTDX_CreateOutputChannel( name );

- Khi chy target. C mt cp c khi chy trn target. Nu s dng
DSP/BIOS configuration tool th c hai s t ng xy ra. Mt khc mc chn
th hai s chi xy ra sau khi hm main() ny thot.
- Mt s kin c chy ng dng trn target nh k gi chc nng
RTDX_poll gi dng d liu gi host v target. Nu cng c cu
hnh dng thit lp n ln cho bn. Ngt cng HWI
HWI_RESERVED1 c s dng gi chc nng RTDX_poll trn
chu k c s.
128
- Trn C6x RTDX s dng ngt. Do NMI v cc ngt ton cc phi
c cho php.
- Cho php knh c v ghi s dng cc hm sau

RTDX_enableInput
RTDX_enableOutput

- c v vit knh RTDX s dng mt trong cc hm sau. Hm
RTDX_read c mt khi v RTDX_readNB l chc nng oc cc d liu
khng dng khi. Chc nng RTDX_read trn thc t ch i trong vng
lp cho n khi vic c hon thnh. N s khng l nguyn nhn thc
hin nhp trng thi TSK_BLOCKED.

RTDX_read
RTDX_readNB
RTDX_write

- V hiu ha knh sau khi dng. Chc nng ny s v hiu ha knh input
hoc l output.
RTDX_disableInput
RTDX_disableOutput
- Chu trnh ny s c th hin trong on code sau trong ngt mm
SWI s c thit lp truyn d liu ti host. Trong v d ny cc s t
nhin s c gi ti host mt ln. V d ny ta tha nhn rng cng c cu
hnh c s dng thit lp DSP/Bios v do target khng cn phi khi
chy.

/* create a global output channel */
RTDX_CreateOutputChannel( ochan );

void funSWI()
{
int data =10; /* data to send to host */
129
int status;

/* enable the output channel */
RTDX_enableOutput( &ochan );

/* send the data to the host */
status =RTDX_write( &ochan, &data, sizeof(data) );

/* check the status of the write operation */
if ( status ==0 ) {
puts("ERROR: RTDX_write failed!\n" );
exit(-1 );
}

/* disable the channel after use */
RTDX_disableOutput( &ochan );
}


on chng trnh ti tng t dng ngt mm SWI nhn cc s
nguyn t host.

/* create a global input channel */
RTDX_CreateInputChannel( ichan );

void funSWI()
{
int data;
int status;

/* enable the input channel */
RTDX_enableInput( &ichan );

/* send the data to the host */
status =RTDX_read( &ichan, &data, sizeof(data) );

130
/* check the status of the read operation */
if ( status !=sizeof(data) ) {
puts("ERROR: RTDX_read failed!\n" );
exit(-1 );
}

/* use the value of the read data here */

/* disable the channel after use */
RTDX_disableInput( &ichan );
}

Cc hm chc nng c dng trong on chng trnh trn.
RTDX_sizeofinput c thit k dng dng chung vi RTDX_readNB
sau khi vic c hon thnh. Hm ny s tr li kch thc thc t ca cc
thnh phn c c t knh d liu.
RTDX_channelBusy cng c dng chung vi RTDX_readNB. N cho
chng ta gi tr ch ra rng knh truyn thc t ang c dng hay l khng.
- RTDX_isInputEnabled and RTDX_isOutputEnabled kim tra xem
knh d c cho php cha.
9.3 Chng trnh ng dng trn host (Host Application basics)
thc hin vic truyn v nhn d liu gia host v target ta cn vit
thm mt chng trnh trn host. y ta s xy dng mt ng dng n gin
vit bng ngn ng VB thc hin vic truyn nhn d liu gia target v host.
Xy dng ng dng trn host c th truyn v nhn d liu t target nh sau:
nh ngha v tham chiu tr li cho RTDX. Mt s hm tr li cho chng
ta cc thng tin trng thi nh on code sau c th c s dng trong cc
nh gi cc thng tin.

Const Success =&H0 ' Method call is valid
Const Failure =&H80004005 ' Method call failed
Const ENoDataAvailable =&H8003001E ' No data was available.
' However, more data may be
131
' available in the future
Const EEndOfLogFile =&H80030002 ' No data was available.
' The end of the log file has
' been reached.

Cng b cc bin ca cc dng i tng.

Dimrtdx As Object

To i tng RTDX COM

Set rtdx =CreateObject("RTDX")

M knh cho c v ghi ti

status =rtdx.Open("ochan", "R")
status =rtdx.Open("ichan", "W")

c v ghi d liu t knh.
- ReadSAI1, ReadSAI2, ReadSAI4, ReadSAF4, ReadSAF8, ReadSAI2V,
ReadSAI4V, Read c thng ip v v in kt qu trong VB
SAFEARRAY
- ReadI1, ReadI2, ReadI4, ReadF4, ReadF8 - c s nguyn hoc d liu
floating-point t knh d liu
- Write Vit d liu t SAFEARRAY ti host.
- WriteI1, WriteI2, WriteI4, WriteF4, WriteF8 Vit d liu ti target.
- Xa knh c v ghi d liu t i tng RTDX c m.
status =rtdx.Close()
Gii phng tham chiu ti i tng RTDX ti rtdx c m.
Set rtdx =Nothing
on code sau l ng dng nhn d liu l mt s nguyn mt ln. Trong
vng lp knh c c v trng thi c tr li kim tra quyt nh kt
qu ca vic c.
132

Const Success =&H0 ' Method call is valid
Const Failure =&H80004005 ' Method call failed
Const ENoDataAvailable =&H8003001E ' No data was available.
' However, more data may be
' available in the future.
Const EEndOfLogFile =&H80030002 ' No data was available
' The end of the log file has
' been reached.

Sub main()
Dimrtdx As Object 'COM object
Dimdata As Long
Dimstatus As Long

'If an error occurs then go to the following function
On Error GoTo Error_Handler
'Create the COM object
Set rtdx =CreateObject("RTDX")
'Open the COM object
status =rtdx.Open("ochan", "R")

'Check the status of the open function
If status <>Success Then
Debug.Print "Opening of channel ochan failed"
GoTo Error_Handler
End If

Do
'Read an integer fromthe RTDX input channel
status =rtdx.ReadI4(data)

'Check the status of the read
Select Case (status)
Case Success
Debug.Print "Value " & data & " was received fromthe target"
Case ENoDataAvailable
133
Case EEndOfLogFile
Debug.Print "End of log file has been detected"
Case Failure
Debug.Print "ReadI4 returned failure"
Exit Do
Case Else
Debug.Print "Unknown return code"
Exit Do
End Select
Loop Until status =EEndOfLogFile

'close the input channel
status =rtdx.Close()
'Release the reference to the RTDX COM object
Set rtdx =Nothing
Exit Sub

Error_Handler:
Debug.Print "Error in COM method call"
Set rtdx =Nothing
End Sub
9.4 Pht trin ng dng vi VB
Visual Basic c thit k pht trin cc ng dng ny. Cc s kin
xy ra khi c mt ci g c khi s bi hnh ng ca ngi s dng, bng
thng ip t h thng hoc cc ng dng khc, hoc s kin t ng dng ca
chnh bn. Cc on m khc nhau c s thi hnh ph thuc vo s kin xy
ra. ng dng ca bn s qun l s kin ging nh mt ai click vo nt bm.
Trong project VB on chng trnh m bn s dng l cc modules biu
mu
( form modules ). Modules biu mu ( m rng ca tn file l .frm ) c th
bao gm cc m t v nguyn bn ca biu mu v cc chc nng ca n, bao
gm c cch thit lp cc thuc tnh ca chng. Chng c th cn bao gm cc
cng b biu mu mc ( form level ) ca hng s, bin, v cc th tc.
Qu trnh khi to d n RTDX c th tun t theo cc bc sau
134
9.4.1 Phn 1
Trong phn ny bn s to ra cc ng dng VB n gin m khng giao
tip vi RTDX. Vic ny ging nh vic to mt ng dng VB bnh thng. ng
dng ny s c nt n ( button ) v khi bn n nt bm ny th n s vit mt
on vn bn trong textbox.
Bt u VB v chn Standard EXE. N s m project mi vi mu
mc nh.
Lu project ca bn li. N s thc hin lu hai file. Ta tm gi chng l
vb1.frm v vb1.vbp.
Click ln button . N c dng thm command button. Trn form
click v r thm command button.
Thay i cc thuc tnh ca button nh sau:
- (Name): Print
- Caption:Print
By gi bn to ra mt text box bng cch click vo trn thanh cng
c ca VB. Gi v ko r n vo form.
Vi textbox bn thay i cc thuc tnh ca n nh sau:
- (Name): TextPrint
- Text: Default Text
By gi bn click p ln button. N s a bn ti ca s m bn s
vit mt on chng trnh qun l s kin click trn button. t tn cho th
tc ny l Print_Click bt ngun t tn ca i tng l Print v n qun l s
kin click.
Trong ca s son lnh, gc tri pha trn mn hnh ta ko thanh menu
xung, chn i tng khc v gc trn bn phi ta chn s kin qun l
trong on m ca chung ta.
Trong hm Print_Click ta thm cc on m vo thay i vn bn trong
text box. N s lm cng vic bng on m sau:

TextPrint.Text ="Printed Text"
135

Ch rng tn i tng, TextPrint, c c l do chng ta thay i
cc thuc tnh ca text.
Chy ng dng VB v kim tra cc chc nng vit.
9.4.2 Phn 2
Trong phn ny bn s to ng dng VB truyn thng vi ng dng
trn target thng qua RTDX. ng dng VB s c 2 button v khi n s gi cc s
khc nhau ti target.ng dng trn target s in gi tr nhn c bi i tng
Log.
u tin ta khi to ng dng VB.
Bt u VB v chn Standard EXE. N s m project mi vi form mc
nh.
Lu project ca bn li. N s lu hai file v ta gi l vb2.frm v vb2.vbp.
Thm 2 command button trn form ca bn vi cc thnh phn nh sau:
- (Name): Command1
- Caption: 1
- (Name): Command2
- Caption: 2
Trong trng (General):(Declarations) thm on m cho trng thi ca
hng s v cc bin khc. on m c th l:

Option Explicit ' Require all variables to be explicitly declared

'--------------------------------------------------------------------------
' RTDX Return Status
'--------------------------------------------------------------------------
Const Success =&H0 ' Method call is valid
Const Failure =&H80004005 ' Method call failed
Const ENoDataAvailable =&H8003001E ' No data currently available.
Const EEndOfLogFile =&H80030002 ' End of transmission

'--------------------------------------------------------------------------
136
' Variable Declarations
'--------------------------------------------------------------------------
Dimrtdx As Object ' Holds the rtdx object
Dimbufferstate As Long ' Holds the number of bytes xmitted
' or pending xmission
Dimstatus As Long ' RTDX Function call return status
Hm th nht c thi hnh khi project c bt u l Form: Load.
Trong hm ny chng ta cho vo on m cho vic khi to knh RTDX. Gi
knh l HtoTchan cho knh host ti target.

'If an error occurs then go to the following function
On Error GoTo Error_Handler
'Create the COM object
Set rtdx =CreateObject("RTDX")
'Open the COM object
status =rtdx.Open("HtoTchan", "R")

'Check the status of the open function
If status <>Success Then
Debug.Print "Opening of channel HtoTchan failed"
GoTo Error_Handler
End If
Error_Handler: ' All errors should be handled here
Debug.Print "Error in Form_Load"
Set rtdx =Nothing
End ' Force programtermination
End Sub
Hm cui cng c thi hnh l chc nng g b form. Trong hm ny
in vo on m sau.
status =rtdx.Close() ' Close rtdx
Set rtdx =Nothing ' Free memory reserved for rtdx obj
Trong hm Click ca command1 in vo mt on m, chng s c
thc thi khi ta click ln button command1. Khi button ny c click n s gi
mt s nguyn 4 byte l s 1 ti target khi m button 1 c click. on m
lm vic ny nh sau:
137
DimData As Long

Data =1
status =rtdx.WriteI4(Data, bufferstate)

If status =Success Then
Debug.Print "Value " & Data & " was sent to the target"
Else
Debug.Print "WriteI4 failed"
End If
in vo chc nng Click ca button Command2 mt on m v n s
c thc thi khi button ny c click. Hm ny thc hin gi s nguyn 4 byte
l s 2 ti target khi m button command2 c click. Thay i on m trn
gi s 2 ti target.
By gi ta phi to ra on m trn target.
To mt project mi vi tn l rtdxab.
To file cu hnh DSP/BIOS mi. Lu li vi tn l rtdxab.cdb v add n
vo trong project ca chng ta. Chng ta cng phi add c file rtdxabcfg.cmd vo
project.
La chn RTDX cho m phng hay l dng chun giao tip JTAG khi
lm vic trc tip vi DSK. To i tng Log tn l trace. Khi to thuc tnh
length l 512 v b m vng ( circular buffer ).
To mt tc v task tn l monitorTSK, n s gi hm funmonitorTSK.
To file main.c v trong hm main c chc nng in ti i tng trace
thng bo chng trnh bt u chy. Add file ny vo project ca chng ta.
To knh vo ton cc vi tn l HtoTchan.
RTDX_CreateInputChannel( HtoTchan );
Trong file main.c to hm cho TSK funmonitorTSK. in vo hm on
m
- Cho php knh u vo
- Add vng lp v hn s dng RTDX_read c d liu t knh v
sau in kt qu nu status bng kch thc ca d liu ( int ).
- on m nh sau
138
int data;
int status;

/* enable the input channel */
RTDX_enableInput( &HtoTchan );

/* receive an integer fromthe host */
while(1)
{
status =RTDX_read( &HtoTchan, &data, sizeof(data) );


if ( status !=sizeof(data) ) {
LOG_printf(&trace,"ERROR: RTDX_read failed!\n" );
exit( -1 );
} else
LOG_printf(&trace,"Value sent =%d",data);

}
Build v load project.
S dng qun l Log Message xem xt kt qu.
Cho php RTDX c dng bng cch vo Tools->RTDX->Configuration
Control v nh du l Enable RTDX.
Chy ng dng trn target. Mt iu cn ch l ta phi khi chy ng dng
trn target trc ng dng trn host. Nu chng trnh VB trn host c bt u
trc th c th lm cho knh khng c khi to.
Chy ng dng trn VB.
Click trn cc button vi ln. Chc chn bn s khng thy chuyn g xy ra.
Tuy nhin nu bn dng qu trnh x l li v m ca s LOG th s thy n
update cc gi tr m bn va click hin ln trn ca s. Nguyn nhn l do
RTDX_read ch i trong vng lp nhn d liu. Do tc v rng s khng
nhn chy v gi d liu ti LOG_print.
139
9.4.3 Phn 3
Trong phn ny chng ta s thay i cc chng trnh phn trc s
dng RTDX_readNB v l do l tc v task ng nu d liu cha sn sng. iu
ny cho php tc v rng ( idle task) hoc cc tc v khc c thc thi.
Copy file main.c trn ti file mi l mainNB.c. G b file main.c v thm
vo file mainNB.c.
Thay i on m trong hm funmonitorTSK nh sau:
int data;
int status;
int busystatus=0;

/* enable the Host to Target channel */
RTDX_enableInput( &HtoTchan );

/* receive an integer fromthe host */
while(1)
{
/* check to see if the channel is busy before the read */
if (busystatus ==0)
{
/* Print the data if something was actually read */
if (RTDX_sizeofInput(&HtoTchan) ==sizeof(data))
{
LOG_printf(&trace,"Value sent =%d",data);
}
status =RTDX_readNB( &HtoTchan, &data, sizeof(data) );
}

/* get the status of the channel */
busystatus =RTDX_channelBusy(&HtoTchan);

/* If the channel is busy then sleep for a time */
/* This is done so that other tasks will have time to run */
if (busystatus ==1)TSK_sleep(1);

140
}
on m dud kim tra trng thi (status) ca RTDX c. Nu n
khng bn th hm TDX_sizeofInput c s dng xem c bao nhiu d liu
c c. Nu s lng chnh xc c c th gi tr s c in ra. Sau y
knh c c li. Tip theo knh s c c v bin trng thi busystatus c
kim tra. Nu trng thi l bn th tc v (task) s c ng trong mt thi gian
ngn. Thi gian ny c thit lp rt ngn.
Build v load chng trnh chy.
S dng qun l LOG xem xt qu trnh lm vic.
Cho php RTDX.
Chy ng dng trn target.
Chy ng dng VB trn host.
Click ln button vi ln. Ln ny bn s thy kt qu c in ra ngay. Nu
bn chy m phng th tr c th l khng c ngha bi n rt chm so vi
thi gian thc.
9.4.4 Phn 4
Trong phn ny bn s thay i cc chng trnh c sn n lm vic
c vi d liu trong min thi gian thc t khi CODEC.
9.4.5 Kt lun
Chng ny cho chng ta hiu c qu trnh truyn thng gia host v
target thng qua RTDX, xy dng chng trnh c phn target v host thc
hin qu trnh ny.







141
TI LIU THAM KHO

[1] cheng-xiang-Wang, Nguyn Vn c, B sch k thut thng tin s,Tap
1: Cc bi tp Matlab v thng tin v tuyn ,Nxb Khkt 2004
[2] Nguyn Vn c, B sch k thut thng tin s, Tp 2: L thuyt v cc
ng dng ca k thut OFDM, Nxb KHKT H Ni, 2006.
[3]N.V.c,D.N.Chin,B sch k thut thng tin s,Tp 4: Thng tin v
tuyn,Nxb KHKT,2007.
[4] http://ti.com (Truy cp ln cui l ngy 10/5/2008)
[5] http://www.diendandientu.net ( Truy cp ln cui ngy 10/5/2008 )
[6] Cng cc ti liu i km trong a phn mm CCS ( Code composer Studio)
l cc file help.



















142
Ph lc 1

/*
* Copyright 2003 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
* ========led.c ========
*
* This example blinks LED #0 at a rate of about 2.5 times per second using
* the LED module of the the 6416 DSK Board Support Library. The example
* also reads the state of DIP switch #3 and lights LED #3 if the switch
* is depressed or turns it off if the switch is not depressed.
*
* The purpose of this example is to demonstrate basic BSL usage as well
* as provide a project base for your own code.
*
* Please see the 6416 DSK help file under Software/Examples for more
* detailed information.
*/

/*
* DSP/BIOS is configured using the DSP/BIOS configuration tool. Settings
* for this example are stored in a configuration file called led.cdb. At
* compile time, Code Composer will auto-generate DSP/BIOS related files
* based on these settings. A header file called ledcfg.h contains the
* results of the autogeneration and must be included for proper operation.
* The name of the file is taken from led.cdb and adding cfg.h.
*/
#include "ledcfg.h"
143

/*
* The 6416 DSK Board Support Library is divided into several modules, each
* of which has its own include file. The file dsk6416.h must be included
* in every program that uses the BSL. This example also includes
* dsk6416_led.h and dsk6416_dip.h because it uses the LED and DIP modules.
*/
#include "dsk6416.h"
#include "dsk6416_led.h"
#include "dsk6416_dip.h"


/*
* main() - Main code routine, initializes BSL and runs LED application
*/

void main()
{
/* Initialize the board support library, must be first BSL call */
DSK6416_init();

/* Initialize the LED and DIP switch modules of the BSL */
DSK6416_LED_init();
DSK6416_DIP_init();

while(1)
{
/* Toggle LED #0 */
DSK6416_LED_toggle(0);

/* Check DIP switch #3 and light LED #3 accordingly, 0 =switch pressed */
144
if (DSK6416_DIP_get(3) ==0)
/* Switch pressed, turn LED #3 on */
DSK6416_LED_on(3);
else
/* Switch not pressed, turn LED #3 off */
DSK6416_LED_off(3);

/* Spin in a software delay loop for about 200ms */
DSK6416_waitusec(200000);
}
}

















145
Ph lc 2
/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)" */
/****************************************************************
***********/
/* */
/* H E L L O . C */
/* */
/* Basic C standard I/O from main. */
/* */
/* */
/****************************************************************
***********/

#include <stdio.h>
#include "hello.h"

#define BUFSIZE 30

struct PARMS str =
{
2934,
9432,
213,
146
9432,
&str
};


/*
* ========main ========
*/
void main()
{
#ifdef FILEIO
int i;
char scanStr[BUFSIZE];
char fileStr[BUFSIZE];
size_t readSize;
FILE *fptr;
#endif

/* write a string to stdout */
puts("hello world!\n");

#ifdef FILEIO
/* clear char arrays */
for (i =0; i <BUFSIZE; i++) {
scanStr[i] =0 /* deliberate syntax error */
fileStr[i] =0;
}

/* read a string from stdin */
scanf("%s", scanStr);

147
/* open a file on the host and write char array */
fptr =fopen("file.txt", "w");
fprintf(fptr, "%s", scanStr);
fclose(fptr);

/* open a file on the host and read char array */
fptr =fopen("file.txt", "r");
fseek(fptr, 0L, SEEK_SET);
readSize =fread(fileStr, sizeof(char), BUFSIZE, fptr);
printf("Read a %d byte char array: %s \n", readSize, fileStr);
fclose(fptr);
#endif
}















148
Ph lc 3

Testapp.c

#include <stdio.h>
int main()
{
int test_data[] ={ 7, 13, 3, 25, 64, 15 };
int max_value =maximumValue(test_data, 6);
int min_value =minimumValue(test_data, 6);
// call library functions
printf( "The maximum value in the data is %d\n", max_value );
printf( "The minimum value in the data is %d\n", min_value );
return 0;
}

minimumvalue.c

int minimumValue( int [],int);
// Requires: array_size equals the number of elements in the array, array_size >0
// Returns: The minimum value contained in the integer array
int minimumValue( int values[], int array_size)
{
int minimum_value;
int i =0;
minimum_value =values[0];
for (i =0; i <array_size; i++)
{
if (values[i] <minimum_value)
minimum_value =values[i];
}
149
return minimum_value;
}

maximumvalue.c

int maximumValue( int [], int);
// Requires: array_size equals the number of elements in the array, array_size >0
// Returns: The maximum value contained in the integer array
int maximumValue( int values[], int array_size)
{
int maximum_value;
int i =0;
maximum_value =values[0];
for (i =0; i <array_size; i++)
{
if (values[i] >maximum_value)
maximum_value =values[i];
}
return maximum_value;
}











150
Ph lc 4

//
****************************************************************
// Description: This application uses Probe Points to obtain input
// (a sine wave). It then takes this signal, and applies a gain
// factor to it.
// Filename: Sine.c
//
****************************************************************

#include <stdio.h>
#include "sine.h"

// gain control variable
int gain =INITIALGAIN;

// declare and initalize a IO buffer
BufferContents currentBuffer;

// Define some functions
static void processing(); // process the input
and generate output
static void dataIO(); // dummy function
to be used with ProbePoint

void main()
{
puts("SineWave example started.\n");

while(TRUE) // loop forever
{
/* Read input data using a probe-point connected to a host file.
Write output data to a graph connected through a probe-point. */
151
dataIO();

/* Apply the gain to the input to obtain the output */
processing();
}
}

/*
* FUNCTION: Apply signal processing transform to input signal
* to generate output signal
* PARAMETERS: BufferContents struct containing input/output arrays
of size BUFFSIZE
* RETURN VALUE: none.
*/
static void processing()
{
int size =BUFFSIZE;

while(size--){
currentBuffer.output[size] =currentBuffer.input[size] * gain; // apply gain
to input
}
}

/*
* FUNCTION: Read input signal and write processed output signal
* using ProbePoints
* PARAMETERS: none.
* RETURN VALUE: none.
*/
static void dataIO()
{
/* do data I/O */
return;
}
152
Ph lc 5

/* HELLOBIOS.C */

#include <std.h>
#include <log.h>

#include "hellobioscfg.h"

/* ========main ========*/
Void main()
{
LOG_printf(&trace, "hello world!");

/* fall into DSP/BIOS idle loop */
return;
}









153
Ph lc 6

/*
* Copyright 2002 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
* ========ledprd.c ========
*
* This example blinks LED #0 at a rate of about 4 times per second using
* the LED module of the the 6416 DSK Board Support Library. The example
* also reads the state of DIP switch #3 and lights LED #3 if the switch
* is depressed or turns it off if the switch is not depressed.
*
* When the program is run, DSP/BIOS initializes itself and calls the main()
* function. Main() initializes the BSL then exits and returns control back
* to DSP/BIOS. The real work is done inside blinkLED0() which is a
DSP/BIOS
* periodic thread that is run every 125ms.
*
* A second thread named blinkLED1() is also included that blinks LED #1
* asynchronously with blinkLED0() to demonstrate DSP/BIOS multitasking.
* It is not enabled by default but can be added by creating a new periodic
* thread entry for it in the DSP/BIOS scheduler.
*
* Please see the 6416 DSK help file under Software/Examples for more
* detailed information.
*/

/*
154
* DSP/BIOS is configured using the DSP/BIOS configuration tool. Settings
* for this example are stored in a configuration file called ledprd.cdb. At
* compile time, Code Composer will auto-generate DSP/BIOS related files
* based on these settings. A header file called ledprdcfg.h contains the
* results of the autogeneration and must be included for proper operation.
* The name of the file is taken from ledprd.cdb and adding cfg.h.
*/
#include "ledprdcfg.h"

/*
* The 6416 DSK Board Support Library is divided into several modules, each
* of which has its own include file. The file dsk6416.h must be included
* in every program that uses the BSL. This example also includes
* dsk6416_led.h and dsk6416_dip.h because it uses the LED and DIP modules.
*/
#include "dsk6416.h"
#include "dsk6416_led.h"
#include "dsk6416_dip.h"


/*
* blinkLED0() - Blink LED #0 and set LED #3 based on the state of DIP switch
* #3. If the switch is down, the LED is turned on. If the
* switch is up, the LED is turned off.
*
* blinkLED0 is a periodic thread that is called every 200ms
* from the DSP/BIOS scheduler. It is configured in the
* DSP/BIOS configuration file (ledprd.cdb) under Scheduling
* -->PRD -->PRD_blinkLED0. Right click PRD_blinkLED0 and
* select Properties to view its settings.
*/
155

void blinkLED0()
{
/* Toggle LED #0 */
DSK6416_LED_toggle(0);

/* Check DIP switch #3 and light LED #3 accordingly, 0 =switch pressed */
if (DSK6416_DIP_get(3) ==0)
/* Switch pressed, turn LED #3 on */
DSK6416_LED_on(3);
else
/* Switch pressed, turn LED #3 off */
DSK6416_LED_off(3);
}


/*
* blinkLED1() - Blink LED #1.
*
* blinkLED1 is a periodic thread that can be called from the
* DSP/BIOS scheduler. By default, it is not active. To make
* it active, create a new PRD entry called PRD_blinkLED1 in
* the DSP/BIOS configuration file (ledprd.cdb) under
* Scheduling -->PRD. Right click PRD_blinkLED1 and select
* properties to configure it. Change the function field to
* _blinkLED1 and the period field to 100 to make blinkLED1()
*/

void blinkLED1()
{
/* Toggle LED #1 */
156
DSK6416_LED_toggle(1);
}


/*
* main() - Initialize BSL then drop into DSP/BIOS idle loop
*/

void main()
{
/* Initialize the board support library, must be first BSL call */
DSK6416_init();

/* Initialize the LED and DIP switch modules of the BSL */
DSK6416_LED_init();
DSK6416_DIP_init();
}







157
Ph lc 7

File volume.c

/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)" */
/****************************************************************
***********/
/* */
/* V O L U M E . C */
/* */
/* Audio gain processing using CLK ISR as data source, and a software */
/* interrupt for processing routine. */
/* */
/****************************************************************
***********/

#include <std.h>

#include <log.h>
#include <swi.h>

#include "volumecfg.h"

158
#include "volume.h"

/* Global declarations */
Int inp_buffer[BUFSIZE]; /* processing data buffers */
Int out_buffer[BUFSIZE];

Int gain =MINGAIN; /* volume control variable */
Uns processingLoad =BASELOAD; /* processing routine load value */

/* Functions */
extern Void load(Uns loadValue);

Int processing(Int *input, Int *output);
Void dataIO(Void);


/*
* ========main ========
*/
Void main()
{
LOG_printf(&trace,"volume example started\n");

/* fall into DSP/BIOS idle loop */
return;
}

/*
* ========processing ========
*
* FUNCTION: Called from processing_SWI to apply signal processing
159
* transform to input signal.
*
* PARAMETERS: address of input and output buffers.
*
* RETURN VALUE: TRUE.
*/
Int processing(Int *input, Int *output)
{
Int size =BUFSIZE;

while(size--){
*output++=*input++* gain;
}

/* additional processing load */
load(processingLoad);

return(TRUE);
}

/*
* ========dataIO ========
*
* FUNCTION: Called from timer ISR to fake a periodic hardware interrupt that
* reads in the input signal and outputs the processed signal.
*
* PARAMETERS: none.
*
* RETURN VALUE: none.
*/
Void dataIO()
160
{
/* do data I/O */

SWI_dec(&processing_SWI); /* post processing_SWI software interrupt */
}




File load.asm


;
; Copyright 2003 by Texas Instruments Incorporated.
; All rights reserved. Property of Texas Instruments Incorporated.
; Restricted rights to use, duplicate or disclose this code are
; granted through contract.
;
;
; "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)"
;
; ========load.asm ========
;
; C-callable interface to assembly language utility functions for the
; volume example.


.global _load

.text

161
N .set 1000

;
; ========_load ========
; This function simulates a load on the DSP by executing N * loopCount
; instructions, where loopCount is the input parameter to load().
;
; void _load(int loopCount)
;
; The loop is using 8 instructions. One instruction for sub, nop and
; b, plus nop 5. The extra nop added after sub is to make the number
; of instructions in the loop a power of 2.
;
_load:

mv a4, b0 ; use b0 as loop counter
[!b0] b lend
mvk N,b1
mpy b1,b0,b0
nop
shru b0,3,b0 ; (loop counter)=(#loops)/8

loop:
sub b0,1,b0
nop
[b0] b loop
nop 5
lend: b b3
nop 5 ; return

.end
162
File volume.h



/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DSP/BIOS 4.90.270 01-13-05 (barracuda-o07)" */
/*
* ========volume.h ========
*
*/

#ifndef __VOLUME_H
#define __VOLUME_H

#ifndef TRUE
#define TRUE 1
#endif

#define BUFSIZE 0x64

#define FRAMESPERBUFFER 10

#define MINGAIN 1
#define MAXGAIN 10

163
#define MINCONTROL 0
#define MAXCONTROL 2000

#define BASELOAD 1

#endif /* __VOLUME_H */

























164
Ph lc 8

/*
* Copyright 2002 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
* ========tone.c ========
*
* This example uses the AIC23 codec module of the 6416 DSK Board Support
* Library to generate a 1KHz sine wave on the audio outputs for 5 seconds.
* The sine wave data is pre-calculated in an array called sinetable. The
* codec operates at 48KHz by default. Since the sine wave table has 48
* entries per period, each pass through the inner loop takes 1 millisecond.
* 5000 passes through the inner loop takes 5 seconds.
*
* Please see the 6416 DSK help file under Software/Examples for more
* detailed information.
*/

/*
* DSP/BIOS is configured using the DSP/BIOS configuration tool. Settings
* for this example are stored in a configuration file called tone.cdb. At
* compile time, Code Composer will auto-generate DSP/BIOS related files
* based on these settings. A header file called tonecfg.h contains the
* results of the autogeneration and must be included for proper operation.
* The name of the file is taken from tone.cdb and adding cfg.h.
*/
#include "tonecfg.h"

165
/*
* The 6416 DSK Board Support Library is divided into several modules, each
* of which has its own include file. The file dsk6416.h must be included
* in every program that uses the BSL. This example also includes
* dsk6416_aic23.h because it uses the AIC23 codec module.
*/
#include "dsk6416.h"
#include "dsk6416_aic23.h"

/* Length of sine wave table */
#define SINE_TABLE_SIZE 48

/* Codec configuration settings */
DSK6416_AIC23_Config config ={ \
0x0017, /* 0 DSK6416_AIC23_LEFTINVOL Left line input channel volume
*/ \
0x0017, /* 1 DSK6416_AIC23_RIGHTINVOL Right line input channel
volume */\
0x00d8, /* 2 DSK6416_AIC23_LEFTHPVOL Left channel headphone
volume */ \
0x00d8, /* 3 DSK6416_AIC23_RIGHTHPVOL Right channel headphone
volume */ \
0x0011, /* 4 DSK6416_AIC23_ANAPATH Analog audio path control */
\
0x0000, /* 5 DSK6416_AIC23_DIGPATH Digital audio path control */ \
0x0000, /* 6 DSK6416_AIC23_POWERDOWN Power down control */
\
0x0043, /* 7 DSK6416_AIC23_DIGIF Digital audio interface format */ \
0x0081, /* 8 DSK6416_AIC23_SAMPLERATE Sample rate control */
\
0x0001 /* 9 DSK6416_AIC23_DIGACT Digital interface activation */ \
166
};

/* Pre-generated sine wave data, 16-bit signed samples */
Int16 sinetable[SINE_TABLE_SIZE] ={
0x0000, 0x10b4, 0x2120, 0x30fb, 0x3fff, 0x4dea, 0x5a81, 0x658b,
0x6ed8, 0x763f, 0x7ba1, 0x7ee5, 0x7ffd, 0x7ee5, 0x7ba1, 0x76ef,
0x6ed8, 0x658b, 0x5a81, 0x4dea, 0x3fff, 0x30fb, 0x2120, 0x10b4,
0x0000, 0xef4c, 0xdee0, 0xcf06, 0xc002, 0xb216, 0xa57f, 0x9a75,
0x9128, 0x89c1, 0x845f, 0x811b, 0x8002, 0x811b, 0x845f, 0x89c1,
0x9128, 0x9a76, 0xa57f, 0xb216, 0xc002, 0xcf06, 0xdee0, 0xef4c
};


/*
* main() - Main code routine, initializes BSL and generates tone
*/

void main()
{
DSK6416_AIC23_CodecHandle hCodec;
Int16 msec, sample;

/* Initialize the board support library, must be called first */
DSK6416_init();

/* Start the codec */
hCodec =DSK6416_AIC23_openCodec(0, &config);

/* Generate a 1KHz sine wave for 5 seconds */
for (msec =0; msec <5000; msec++)
{
167
for (sample =0; sample <SINE_TABLE_SIZE; sample++)
{
/* Send a sample to the left channel */
while (!DSK6416_AIC23_write(hCodec, sinetable[sample]));

/* Send a sample to the right channel */
while (!DSK6416_AIC23_write(hCodec, sinetable[sample]));
}
}

/* Close the codec */
DSK6416_AIC23_closeCodec(hCodec);
}


















168
Ph lc 9


Chng trnh dsk_app.c

/*
* Copyright 2003 by Spectrum Digital Incorporated.
* All rights reserved. Property of Spectrum Digital Incorporated.
*/

/*
* ========dsk_app.c ========
*
* Version 1.00
*
* This example digitally processes audio data from the line input on the
* AIC23 codec and plays the result on the line output. It uses the McBSP
* and EDMA to efficiently handle the data transfer without intervention from
* the DSP.
*
* Data transfer
*
* Audio data is transferred back and forth from the codec through McBSP2,
* a bidirectional serial port. The EDMA is configured to take every 16-bit
* signed audio sample arriving on McBSP2 and store it in a buffer in memory
* until it can be processed. Once it has been processed, the EDMA
* controller sends the data back to McBSP2 for transmission.
*
* A second serial port, McBSP1 is used to control/configure the AIC23. The
* codec receives serial commands through McBSP1 that set configuration
* parameters such as volume, sample rate and data format.
169
*
* In addition to basic EDMA transfers, this example uses 2 special
* techniques to make audio processing more convenient and efficient:
*
* 1) Ping-pong data buffering in memory
* 2) Linked EDMA transfers
*
* Applications with single buffers for receive and transmit data are
* very tricky and timing dependent because new data constantly overwrites
* the data being transmitted. Ping-pong buffering is a technique where two
* buffers (referred to as the PING buffer and the PONG buffer) are used for
* a data transfer instead of only one. The EDMA is configured to fill the
* PING buffer first, then the PONG buffer. While the PONG buffer is being
* filled, the PING buffer can be processed with the knowledge that the
* current EDMA transfer won't overwrite it. This example uses ping-pong
* buffers on both transmit and receive ends for a total of four buffers.
*
* The EDMA controller must be configured slightly differently for each
* buffer. When a buffer is filled, the EDMA controller generates an
* interrupt. The interrupt handler must reload the configuration
* for the next buffer before the next audio sample arrives. An EDMA
* feature called linked transfers is used to make this event less time
* critical. Each configuration is created in advance and the EDMA
* controller automatically links to the next configuration when the
* current configuration is finished. An interrupt is still generated,
* but it serves only to signal the DSP that it can process the data.
* The only time constraint is that all the audio data must be processed
* before the the active buffer fills up, which is much longer than the
* time between audio samples. It is much easier to satisfy real-time
* constraints with this implementation.
*
170
* Program flow
*
* When the program is run, the individual DSP/BIOS modules are initialized
* as configured in dsk_app1.cdb with the DSP/BIOS configuration tool. The
* main() function is then called as the main user thread. In this example
* main() performs application initialization and starts the EDMA data
* transfers. When main exits, control passes back entirely to DSP/BIOS
* which services any interrupts or threads on an as-needed basis.
*
* The edmaHwi() interrupt service routine is called when a buffer has been
* filled. It contains a state variable named pingOrPong that indicates
* whether the buffer is a PING or PONG buffer. dmaHwi switches the buffer
* state to the opposite buffer and calls the SWI thread processBuffer to
* process the audio data.
*
* Other Functions
*
* The example includes a few other functions that are executed in the
* background as examples of the multitasking that DSP/BIOS is capable of:
*
* 1) blinkLED() toggles LED #0 every 500ms if DIP switch #0 is depressed.
* It is a periodic thread with a period of 500 ticks.
*
* 2) load() simulates a 20-25% dummy load if DIP switch #1 is depressed.
* It represents other computation that may need to be done. It is a
* periodic thread with a period of 10ms.
*
* Please see the 6416 DSK help file under Software/Examples for more
* detailed information on this example.
*/

171
/*
* DSP/BIOS is configured using the DSP/BIOS configuration tool. Settings
* for this example are stored in a configuration file called dsk_app.cdb.
* At compile time, Code Composer will auto-generate DSP/BIOS related files
* based on these settings. A header file called dsk_appcfg.h contains the
* results of the autogeneration and must be included for proper operation.
* The name of the file is taken from dsk_app.cdb and adding cfg.h.
*/
#include "dsk_appcfg.h"

/*
* These are include files that support interfaces to BIOS and CSL modules
* used by the program.
*/
#include <std.h>
#include <swi.h>
#include <log.h>
#include <c6x.h>
#include <csl.h>
#include <csl_edma.h>
#include <csl_irq.h>
#include <csl_mcbsp.h>

/*
* The 6416 DSK Board Support Library is divided into several modules, each
* of which has its own include file. The file dsk6416.h must be included
* in every program that uses the BSL. This example also uses the
* DIP, LED and AIC23 modules.
*/
#include "dsk6416.h"
#include "dsk6416_led.h"
172
#include "dsk6416_dip.h"
#include "dsk6416_aic23.h"

/* Function prototypes */
void initIrq(void);
void initMcbsp(void);
void initEdma(void);
void copyData(Int16 *inbuf, Int16 *outbuf, Int16 length);
void processBuffer(void);
void edmaHwi(void);

/* Constants for the buffered ping-pong transfer */
#define BUFFSIZE 1000
#define PING 0
#define PONG 1

/*
* Data buffer declarations - the program uses four logical buffers of size
* BUFFSIZE, one ping and one pong buffer on both receive and transmit sides.
*/
Int16 gBufferXmtPing[BUFFSIZE]; // Transmit PING buffer
Int16 gBufferXmtPong[BUFFSIZE]; // Transmit PONG buffer

Int16 gBufferRcvPing[BUFFSIZE]; // Receive PING buffer
Int16 gBufferRcvPong[BUFFSIZE]; // Receive PONG buffer

EDMA_Handle hEdmaXmt; // EDMA channel handles
EDMA_Handle hEdmaReloadXmtPing;
EDMA_Handle hEdmaReloadXmtPong;
EDMA_Handle hEdmaRcv;
EDMA_Handle hEdmaReloadRcvPing;
173
EDMA_Handle hEdmaReloadRcvPong;

MCBSP_Handle hMcbsp2; // McBSP2 (codec data) handle

Int16 gXmtChan; // TCC codes (see initEDMA())
Int16 gRcvChan;

extern far SWI_Obj processBufferSwi; // SWI object

extern far LOG_Obj logTrace; // LOG object for LOG_printf


/*
* EDMA Config data structure
*/

/* Transmit side EDMA configuration */
EDMA_Config gEdmaConfigXmt ={
EDMA_FMKS(OPT, PRI, HIGH) | // Priority
EDMA_FMKS(OPT, ESIZE, 16BIT) | // Element size
EDMA_FMKS(OPT, 2DS, NO) | // 2 dimensional source?
EDMA_FMKS(OPT, SUM, INC) | // Src update mode
EDMA_FMKS(OPT, 2DD, NO) | // 2 dimensional dest
EDMA_FMKS(OPT, DUM, NONE) | // Dest update mode
EDMA_FMKS(OPT, TCINT, YES) | // Cause EDMA interrupt?
EDMA_FMKS(OPT, TCC, OF(0)) | // Transfer complete code
EDMA_FMKS(OPT, LINK, YES) | // Enable link parameters?
EDMA_FMKS(OPT, FS, NO), // Use frame sync?

(Uint32)&gBufferXmtPing, // Src address

174
EDMA_FMK (CNT, FRMCNT, NULL) | // Frame count
EDMA_FMK (CNT, ELECNT, BUFFSIZE), // Element count

EDMA_FMKS(DST, DST, OF(0)), // Dest address

EDMA_FMKS(IDX, FRMIDX, DEFAULT) | // Frame index value
EDMA_FMKS(IDX, ELEIDX, DEFAULT), // Element index value

EDMA_FMK (RLD, ELERLD, NULL) | // Reload element
EDMA_FMK (RLD, LINK, NULL) // Reload link
};

/* Receive side EDMA configuration */
EDMA_Config gEdmaConfigRcv ={
EDMA_FMKS(OPT, PRI, HIGH) | // Priority
EDMA_FMKS(OPT, ESIZE, 16BIT) | // Element size
EDMA_FMKS(OPT, 2DS, NO) | // 2 dimensional source?
EDMA_FMKS(OPT, SUM, NONE) | // Src update mode
EDMA_FMKS(OPT, 2DD, NO) | // 2 dimensional dest
EDMA_FMKS(OPT, DUM, INC) | // Dest update mode
EDMA_FMKS(OPT, TCINT, YES) | // Cause EDMA interrupt?
EDMA_FMKS(OPT, TCC, OF(0)) | // Transfer complete code
EDMA_FMKS(OPT, LINK, YES) | // Enable link parameters?
EDMA_FMKS(OPT, FS, NO), // Use frame sync?

EDMA_FMKS(SRC, SRC, OF(0)), // Src address

EDMA_FMK (CNT, FRMCNT, NULL) | // Frame count
EDMA_FMK (CNT, ELECNT, BUFFSIZE), // Element count

(Uint32)&gBufferRcvPing, // Dest address
175

EDMA_FMKS(IDX, FRMIDX, DEFAULT) | // Frame index value
EDMA_FMKS(IDX, ELEIDX, DEFAULT), // Element index value

EDMA_FMK (RLD, ELERLD, NULL) | // Reload element
EDMA_FMK (RLD, LINK, NULL) // Reload link
};

/* McBSP codec data channel configuration */
MCBSP_Config mcbspCfg2 ={
MCBSP_FMKS(SPCR, FREE, NO) |
MCBSP_FMKS(SPCR, SOFT, NO) |
MCBSP_FMKS(SPCR, FRST, YES) |
MCBSP_FMKS(SPCR, GRST, YES) |
MCBSP_FMKS(SPCR, XINTM, XRDY) |
MCBSP_FMKS(SPCR, XSYNCERR, NO) |
MCBSP_FMKS(SPCR, XRST, YES) |
MCBSP_FMKS(SPCR, DLB, OFF) |
MCBSP_FMKS(SPCR, RJ UST, RZF) |
MCBSP_FMKS(SPCR, CLKSTP, DISABLE) |
MCBSP_FMKS(SPCR, DXENA, OFF) |
MCBSP_FMKS(SPCR, RINTM, RRDY) |
MCBSP_FMKS(SPCR, RSYNCERR, NO) |
MCBSP_FMKS(SPCR, RRST, YES),

MCBSP_FMKS(RCR, RPHASE, SINGLE) |
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RCOMPAND, MSB) |
MCBSP_FMKS(RCR, RFIG, NO) |
MCBSP_FMKS(RCR, RDATDLY, 0BIT) |
176
MCBSP_FMKS(RCR, RFRLEN1, OF(1)) |
MCBSP_FMKS(RCR, RWDLEN1, 16BIT) |
MCBSP_FMKS(RCR, RWDREVRS, DISABLE),

MCBSP_FMKS(XCR, XPHASE, SINGLE) |
MCBSP_FMKS(XCR, XFRLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XWDLEN2, DEFAULT) |
MCBSP_FMKS(XCR, XCOMPAND, MSB) |
MCBSP_FMKS(XCR, XFIG, NO) |
MCBSP_FMKS(XCR, XDATDLY, 0BIT) |
MCBSP_FMKS(XCR, XFRLEN1, OF(1)) |
MCBSP_FMKS(XCR, XWDLEN1, 16BIT) |
MCBSP_FMKS(XCR, XWDREVRS, DISABLE),

MCBSP_FMKS(SRGR, GSYNC, DEFAULT) |
MCBSP_FMKS(SRGR, CLKSP, DEFAULT) |
MCBSP_FMKS(SRGR, CLKSM, DEFAULT) |
MCBSP_FMKS(SRGR, FSGM, DEFAULT) |
MCBSP_FMKS(SRGR, FPER, DEFAULT) |
MCBSP_FMKS(SRGR, FWID, DEFAULT) |
MCBSP_FMKS(SRGR, CLKGDV, DEFAULT),

MCBSP_MCR_DEFAULT,
MCBSP_RCERE0_DEFAULT,
MCBSP_RCERE1_DEFAULT,
MCBSP_RCERE2_DEFAULT,
MCBSP_RCERE3_DEFAULT,
MCBSP_XCERE0_DEFAULT,
MCBSP_XCERE1_DEFAULT,
MCBSP_XCERE2_DEFAULT,
MCBSP_XCERE3_DEFAULT,
177

MCBSP_FMKS(PCR, XIOEN, SP) |
MCBSP_FMKS(PCR, RIOEN, SP) |
MCBSP_FMKS(PCR, FSXM, EXTERNAL) |
MCBSP_FMKS(PCR, FSRM, EXTERNAL) |
MCBSP_FMKS(PCR, CLKXM, INPUT) |
MCBSP_FMKS(PCR, CLKRM, INPUT) |
MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT) |
MCBSP_FMKS(PCR, DXSTAT, DEFAULT) |
MCBSP_FMKS(PCR, FSXP, ACTIVEHIGH) |
MCBSP_FMKS(PCR, FSRP, ACTIVEHIGH) |
MCBSP_FMKS(PCR, CLKXP, FALLING) |
MCBSP_FMKS(PCR, CLKRP, RISING)
};

/* Codec configuration settings */
DSK6416_AIC23_Config config ={ \
0x0017, /* 0 DSK6416_AIC23_LEFTINVOL Left line input channel volume
*/ \
0x0017, /* 1 DSK6416_AIC23_RIGHTINVOL Right line input channel
volume */\
0x01f9, /* 2 DSK6416_AIC23_LEFTHPVOL Left channel headphone
volume */ \
0x01f9, /* 3 DSK6416_AIC23_RIGHTHPVOL Right channel headphone
volume */ \
0x0011, /* 4 DSK6416_AIC23_ANAPATH Analog audio path control */
\
0x0000, /* 5 DSK6416_AIC23_DIGPATH Digital audio path control */ \
0x0000, /* 6 DSK6416_AIC23_POWERDOWN Power down control */
\
0x0043, /* 7 DSK6416_AIC23_DIGIF Digital audio interface format */ \
178
0x0001, /* 8 DSK6416_AIC23_SAMPLERATE Sample rate control */
\
0x0001 /* 9 DSK6416_AIC23_DIGACT Digital interface activation */ \
};


/* --------------------------- main() function -------------------------- */
/*
* main() - The main user task. Performs application initialization and
* starts the data transfer.
*/
void main()
{
/* Initialize Board Support Library */
DSK6416_init();

/* Initialize LEDs and DIP switches */
DSK6416_LED_init();
DSK6416_DIP_init();

/* Clear buffers */
memset((void *)gBufferXmtPing, 0, BUFFSIZE * 4 * 2);

AIC23_setParams(&config); // Configure the codec

initMcbsp(); // Initialize McBSP2 for audio transfers

IRQ_globalDisable(); // Disable global interrupts during setup

initEdma(); // Initialize the EDMA controller

179
initIrq(); // Initialize interrupts

IRQ_globalEnable(); // Re-enable global interrupts
}


/* ------------------------Helper Functions ----------------------------- */

/*
* initMcbsp() - Initialize the McBSP for codec data transfers using the
* configuration define at the top of this file.
*/
void initMcbsp()
{
/* Open the codec data McBSP */
hMcbsp2 =MCBSP_open(MCBSP_DEV2, MCBSP_OPEN_RESET);

/* Configure the codec to match the AIC23 data format */
MCBSP_config(hMcbsp2, &mcbspCfg2);

/* Start the McBSP running */
MCBSP_start(hMcbsp2, MCBSP_XMIT_START | MCBSP_RCV_START |
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 220);
}


/*
* initIrq() - Initialize and enable the DMA receive interrupt using the CSL.
* The interrupt service routine for this interrupt is edmaHwi.
*/
void initIrq(void)
180
{
/* Enable EDMA interrupts to the CPU */
IRQ_clear(IRQ_EVT_EDMAINT); // Clear any pending EDMA interrupts
IRQ_enable(IRQ_EVT_EDMAINT); // Enable EDMA interrupt
}


/*
* initEdma() - Initialize the DMA controller. Use linked transfers to
* automatically transition from ping to pong and visa-versa.
*/
void initEdma(void)
{
/* Configure transmit channel */
hEdmaXmt =EDMA_open(EDMA_CHA_XEVT2, EDMA_OPEN_RESET);
// get hEdmaXmt handle and reset channel
hEdmaReloadXmtPing = EDMA_allocTable(-1); // get
hEdmaReloadXmtPing handle
hEdmaReloadXmtPong = EDMA_allocTable(-1); // get
hEdmaReloadXmtPong handle

gEdmaConfigXmt.dst =MCBSP_getXmtAddr(hMcbsp2); // set the
desination address to McBSP2 DXR

gXmtChan =EDMA_intAlloc(-1); // get an open TCC
gEdmaConfigXmt.opt |=EDMA_FMK(OPT,TCC,gXmtChan); // set TCC
to gXmtChan

EDMA_config(hEdmaXmt, &gEdmaConfigXmt); // then configure
the registers
181
EDMA_config(hEdmaReloadXmtPing, &gEdmaConfigXmt); // and the
reload for Ping

gEdmaConfigXmt.src =EDMA_SRC_OF(gBufferXmtPong); // change
the structure to have a source of Pong
EDMA_config(hEdmaReloadXmtPong, &gEdmaConfigXmt); // and
configure the reload for Pong

EDMA_link(hEdmaXmt,hEdmaReloadXmtPong); // link the regs to
Pong
EDMA_link(hEdmaReloadXmtPong,hEdmaReloadXmtPing); // link Pong
to Ping
EDMA_link(hEdmaReloadXmtPing,hEdmaReloadXmtPong); // and link
Ping to Pong

/* Configure receive channel */
hEdmaRcv =EDMA_open(EDMA_CHA_REVT2, EDMA_OPEN_RESET);
// get hEdmaRcv handle and reset channel
hEdmaReloadRcvPing = EDMA_allocTable(-1); // get
hEdmaReloadRcvPing handle
hEdmaReloadRcvPong = EDMA_allocTable(-1); // get
hEdmaReloadRcvPong handle

gEdmaConfigRcv.src =MCBSP_getRcvAddr(hMcbsp2); // and the
desination address to McBSP2 DXR

gRcvChan =EDMA_intAlloc(-1); // get an open TCC
gEdmaConfigRcv.opt |=EDMA_FMK(OPT,TCC,gRcvChan); // set TCC
to gRcvChan

182
EDMA_config(hEdmaRcv, &gEdmaConfigRcv); // then configure
the registers
EDMA_config(hEdmaReloadRcvPing, &gEdmaConfigRcv); // and the
reload for Ping

gEdmaConfigRcv.dst =EDMA_DST_OF(gBufferRcvPong); // change the
structure to have a destination of Pong
EDMA_config(hEdmaReloadRcvPong, &gEdmaConfigRcv); // and
configure the reload for Pong

EDMA_link(hEdmaRcv,hEdmaReloadRcvPong); // link the regs to
Pong
EDMA_link(hEdmaReloadRcvPong,hEdmaReloadRcvPing); // link Pong
to Ping
EDMA_link(hEdmaReloadRcvPing,hEdmaReloadRcvPong); // and link
Ping to Pong

/* Enable interrupts in the EDMA controller */
EDMA_intClear(gXmtChan);
EDMA_intClear(gRcvChan); // clear any possible spurious
interrupts

EDMA_intEnable(gXmtChan); // enable EDMA interrupts
(CIER)
EDMA_intEnable(gRcvChan); // enable EDMA interrupts
(CIER)

EDMA_enableChannel(hEdmaXmt); // enable EDMA channel
EDMA_enableChannel(hEdmaRcv); // enable EDMA channel

/* Do a dummy write to generate the first McBSP transmit event */
183
MCBSP_write(hMcbsp2, 0);
}


/*
* copyData() - Copy one buffer with length elements to another.
*/
void copyData(Int16 *inbuf, Int16 *outbuf, Int16 length)
{
Int16 i =0;

for (i =0; i <length; i++) {
outbuf[i] =inbuf[i];
}
}


/* ---------------------- Interrupt Service Routines -------------------- */

/*
* edmaHwi() - Interrupt service routine for the DMA transfer. It is
* triggered when a complete DMA receive frame has been
* transferred. The edmaHwi ISR is inserted into the interrupt
* vector table at compile time through a setting in the DSP/BIOS
* configuration under Scheduling -->HWI -->HWI_INT8. edmaHwi
* uses the DSP/BIOS Dispatcher to save register state and make
* sure the ISR co-exists with other DSP/BIOS functions.
*/
void edmaHwi(void)
{
static Uint32 pingOrPong =PING; // Ping-pong state variable
184
static Int16 xmtdone =0, rcvdone =0;

/* Check CIPR to see which transfer completed */
if (EDMA_intTest(gXmtChan))
{
EDMA_intClear(gXmtChan);
xmtdone =1;
}
if (EDMA_intTest(gRcvChan))
{
EDMA_intClear(gRcvChan);
rcvdone =1;
}

/* If both transfers complete, signal processBufferSwi to handle */
if (xmtdone && rcvdone)
{
if (pingOrPong==PING)
{
SWI_or(&processBufferSwi, PING);
pingOrPong =PONG;
} else
{
SWI_or(&processBufferSwi, PONG);
pingOrPong =PING;
}
rcvdone =0;
xmtdone =0;
}
}

185

/* ------------------------------- Threads ------------------------------ */

/*
* processBuffer() - Process audio data once it has been received.
*/
void processBuffer(void)
{
Uint32 pingPong;

/* Get contents of mailbox posted by edmaHwi */
pingPong = SWI_getmbox();

/* Copy data from transmit to receive, could process audio here */
if (pingPong ==PING) {
/* Toggle LED #3 as a visual cue */
DSK6416_LED_toggle(3);

/* Copy receive PING buffer to transmit PING buffer */
copyData(gBufferRcvPing, gBufferXmtPing, BUFFSIZE);
} else {
/* Toggle LED #2 as a visual cue */
DSK6416_LED_toggle(2);

/* Copy receive PONG buffer to transmit PONG buffer */
copyData(gBufferRcvPong, gBufferXmtPong, BUFFSIZE);
}
}

/*
* blinkLED() - Periodic thread (PRD) that toggles LED #0 every 500ms if
186
* DIP switch #0 is depressed. The thread is configured
* in the DSP/BIOS configuration tool under Scheduling -->
* PRD -->PRD_blinkLed. The period is set there at 500
* ticks, with each tick corresponding to 1ms in real
* time.
*/
void blinkLED(void)
{
/* Toggle LED #0 if DIP switch #0 is off (depressed) */
if (!DSK6416_DIP_get(0))
DSK6416_LED_toggle(0);
}


/*
* load() - PRD that simulates a 20-25% dummy load on a 600MHz 6416 if
* DIP switch #1 is depressed. The thread is configured in
* the DSP/BIOS configuration tool under Scheduling -->PRD
* PRD_load. The period is set there at 10 ticks, which each tick
* corresponding to 1ms in real time.
*/
void load(void)
{
volatile Uint32 i;

if (!DSK6416_DIP_get(1))
for (i =0; i <64000; i++);
}



187
File AIC23.c


/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/

/*
* ========aic23.c ========
*
* AIC23 codec driver implementation specific to the
* Spectrum Digital DSK6416 board.
*/

#include "dsk_appcfg.h"

#include <aic23.h>

#include <csl.h>
#include <csl_mcbsp.h>

static void aic23Rset(MCBSP_Handle hMcbsp, Uint16 regnum, Uint16 regval);

/* CSL handle to the McBSP1. The McBSP is used as the control channel in
SPI*/
static MCBSP_Config mcbspCfg1 ={
MCBSP_FMKS(SPCR, FREE, NO) |
188
MCBSP_FMKS(SPCR, SOFT, NO) |
MCBSP_FMKS(SPCR, FRST, YES) |
MCBSP_FMKS(SPCR, GRST, YES) |
MCBSP_FMKS(SPCR, XINTM, XRDY) |
MCBSP_FMKS(SPCR, XSYNCERR, NO) |
MCBSP_FMKS(SPCR, XRST, YES) |
MCBSP_FMKS(SPCR, DLB, OFF) |
MCBSP_FMKS(SPCR, RJ UST, RZF) |
MCBSP_FMKS(SPCR, CLKSTP, NODELAY) |
MCBSP_FMKS(SPCR, DXENA, OFF) |
MCBSP_FMKS(SPCR, RINTM, RRDY) |
MCBSP_FMKS(SPCR, RSYNCERR, NO) |
MCBSP_FMKS(SPCR, RRST, YES),

MCBSP_FMKS(RCR, RPHASE, DEFAULT) |
MCBSP_FMKS(RCR, RFRLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN2, DEFAULT) |
MCBSP_FMKS(RCR, RCOMPAND, DEFAULT) |
MCBSP_FMKS(RCR, RFIG, DEFAULT) |
MCBSP_FMKS(RCR, RDATDLY, DEFAULT) |
MCBSP_FMKS(RCR, RFRLEN1, DEFAULT) |
MCBSP_FMKS(RCR, RWDLEN1, DEFAULT) |
MCBSP_FMKS(RCR, RWDREVRS, DEFAULT),

MCBSP_FMKS(XCR, XPHASE, SINGLE) |
MCBSP_FMKS(XCR, XFRLEN2, OF(0)) |
MCBSP_FMKS(XCR, XWDLEN2, 8BIT) |
MCBSP_FMKS(XCR, XCOMPAND, MSB) |
MCBSP_FMKS(XCR, XFIG, NO) |
MCBSP_FMKS(XCR, XDATDLY, 1BIT) |
MCBSP_FMKS(XCR, XFRLEN1, OF(0)) |
189
MCBSP_FMKS(XCR, XWDLEN1, 16BIT) |
MCBSP_FMKS(XCR, XWDREVRS, DISABLE),

MCBSP_FMKS(SRGR, GSYNC, FREE) |
MCBSP_FMKS(SRGR, CLKSP, RISING) |
MCBSP_FMKS(SRGR, CLKSM, INTERNAL) |
MCBSP_FMKS(SRGR, FSGM, DXR2XSR) |
MCBSP_FMKS(SRGR, FPER, OF(0)) |
MCBSP_FMKS(SRGR, FWID, OF(19)) |
MCBSP_FMKS(SRGR, CLKGDV, OF(99)),

MCBSP_MCR_DEFAULT,
MCBSP_RCERE0_DEFAULT,
MCBSP_RCERE1_DEFAULT,
MCBSP_RCERE2_DEFAULT,
MCBSP_RCERE3_DEFAULT,
MCBSP_XCERE0_DEFAULT,
MCBSP_XCERE1_DEFAULT,
MCBSP_XCERE2_DEFAULT,
MCBSP_XCERE3_DEFAULT,

MCBSP_FMKS(PCR, XIOEN, SP) |
MCBSP_FMKS(PCR, RIOEN, SP) |
MCBSP_FMKS(PCR, FSXM, INTERNAL) |
MCBSP_FMKS(PCR, FSRM, EXTERNAL) |
MCBSP_FMKS(PCR, CLKXM, OUTPUT) |
MCBSP_FMKS(PCR, CLKRM, INPUT) |
MCBSP_FMKS(PCR, CLKSSTAT, DEFAULT) |
MCBSP_FMKS(PCR, DXSTAT, DEFAULT) |
MCBSP_FMKS(PCR, FSXP, ACTIVELOW) |
MCBSP_FMKS(PCR, FSRP, DEFAULT) |
190
MCBSP_FMKS(PCR, CLKXP, FALLING) |
MCBSP_FMKS(PCR, CLKRP, DEFAULT)
};

/*
* ========AIC23_setParams ========
*
* This function takes a pointer to the object of type AIC23_Params,
* and writes all 11 control words found in it to the codec. Prior
* to that it initializes the codec if this is the first time the
* function is ever called.
* The 16-bit word is composed of register address in the upper 7 bits
* and the 9-bit register value stored in the parameters structure.
*/
Void AIC23_setParams(AIC23_Params *params)
{
Int i;
MCBSP_Handle hMcbsp;

/* open and configure McBSPs */
hMcbsp =MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET);
MCBSP_config(hMcbsp, &mcbspCfg1);

/*
* Initialize the AIC23 codec
*/

/* Start McBSP1 as the codec control channel */
MCBSP_start(hMcbsp, MCBSP_XMIT_START |
MCBSP_SRGR_START | MCBSP_SRGR_FRAMESYNC, 100);

191
/* Reset the AIC23 */
aic23Rset(hMcbsp, AIC23_RESET, 0);

/* Assign each register */
for (i =0; i <AIC23_NUMREGS; i++) {
aic23Rset(hMcbsp, i, params->regs[i]);
}
}


/*
* ========aic23Rset ========
* Set codec register regnum to value regval
*/
static Void aic23Rset(MCBSP_Handle hMcbsp, Uint16 regnum, Uint16 regval)
{
/* Mask off lower 9 bits */
regval &=0x1ff;

/* Wait for XRDY signal before writing data to DXR */
while (!MCBSP_xrdy(hMcbsp));

/* Write 16 bit data value to DXR */
MCBSP_write(hMcbsp, (regnum <<9) | regval);

/* Wait for XRDY, state machine will not update until next McBSP clock */
while (MCBSP_xrdy(hMcbsp));
}



192

File aic.h



/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DDK 1.00.00.02 01-20-03 (ddk-a14)" */
/*
* ========aic23.h ========
*
* Header file for the AIC23 codec driver implementation specific to the
* Spectrum Digital EVM5509 board. It contains
* control word bit-definition macros and declaration of public functions.
*/

#ifndef AIC23_
#define AIC23_

#include <std.h>

#include <csl.h>

/*
* AIC23 Control registers
*
193
* There are 10 control registers (+the reset reg.) on AIC23, each 9 bits wide.
* The address of a control register is 7 bits wide: together,
* the address of a register and its content form a 16-bit control word,
* the address occupying the uppermost 7 bits and the content lowermost 9.
*/
#define AIC23_NUMREGS 10
#define AIC23_RESET 15

/*
* A macro that let us define 9-bit register values as array of zeroes/ones
*/
#define AIC23_9BITWORD( b8, b7, b6, b5, b4, b3, b2, b1, b0 ) \
((Uns)( 1*(b0) + 2*(b1) + 4*(b2) + 8*(b3) + \
16*(b4) +32*(b5) +64*(b6) +128*(b7) +256*(b8) ))

#define AIC23_REG0_DEFAULT \
AIC23_9BITWORD( /* REG 0: left input ch. volume control */ \
0, /* simultaneous left/right volume: disabled*/ \
0, /* left line input mute: disabled */ \
0,0, /* reserved */ \
1,0,1,1,1 /* left line input volume: 0 dB */ \
)

#define AIC23_REG1_DEFAULT \
AIC23_9BITWORD( /* REG 1: right input ch. volume control*/ \
0, /* simultaneous right/left volume: disabled*/ \
0, /* right line input mute: disabled */ \
0,0, /* reserved */ \
1,0,1,1,1 /* right line input volume: 0 dB */ \
)

194
#define AIC23_REG2_DEFAULT \
AIC23_9BITWORD( /* REG 2: left ch. headphone volume control*/ \
1, /* simultaneous left/right volume: enabled */ \
1, /* left channel zero-cross detect: enabled */ \
1,1,1,1,0,0,1 /* left headphone volume: 0 dB */ \
)

#define AIC23_REG3_DEFAULT \
AIC23_9BITWORD( /* REG 3: right ch. headphone volume ctrl */ \
1, /* simultaneous right/left volume: enabled */ \
1, /* right channel zero-cross detect: enabled*/ \
1,1,1,1,0,0,1 /* right headphone volume: 0 dB */ \
)

#define AIC23_REG4_DEFAULT \
AIC23_9BITWORD( /* REG 4: analog audio path control */ \
0, /* reserved */ \
0,0, /* sidetone attenuation: 6 dB */ \
0, /* sidetone: disabled */ \
1, /* DAC: selected */ \
0, /* bypass: off */ \
0, /* input select for ADC: line */ \
0, /* microphone mute: disabled */ \
1 /* microphone boost: enabled */ \
)

#define AIC23_REG5_DEFAULT \
AIC23_9BITWORD( /* REG 5: digital audio path control */ \
0,0,0,0,0, /* reserved */ \
0, /* DAC soft mute: disabled */ \
0,0, /* deemphasis control: 48khz */ \
195
0 /* ADC high-pass filter: disabled */ \
)

#define AIC23_REG6_DEFAULT \
AIC23_9BITWORD( /* REG 6: power down control */ \
0, /* reserved */ \
0, /* device power: on (i.e. not off) */ \
0, /* clock: on */ \
0, /* oscillator: on */ \
0, /* outputs: on */ \
0, /* DAC: on */ \
0, /* ADC: on */ \
0, /* microphone: on */ \
0 /* line input: on */ \
)

#define AIC23_REG7_DEFAULT \
AIC23_9BITWORD( /* REG 7: digital audio interf. format ctrl*/ \
0,0, /* reserved */ \
1, /* master/slave mode: master */ \
0, /* DEC left/right swap: disabled */ \
0, /* no delay before transmitting MSB */ \
0,0, /* input bit length: 16 bit */ \
1,1 /* data format: DSP format */ \
)

#define AIC23_REG8_8KHZ \
AIC23_9BITWORD( /* REG 8: sample rate control */ \
0, /* reserved */ \
0, /* clock output divider: 1 (MCLK) */ \
0, /* clock input divider: 1 (MCLK) */ \
196
0,0,1,1,0, /* sampling rate: ADC 8kHz DAC 8kHz */ \
1 /* clock mode select (USB/normal): USB */ \
) \

#define AIC23_REG8_32KHZ \
AIC23_9BITWORD( /* REG 8: sample rate control */ \
0, /* reserved */ \
0, /* clock output divider: 1 (MCLK) */ \
0, /* clock input divider: 1 (MCLK) */ \
0,1,1,0,0, /* sampling rate: ADC 32kHz DAC 32kHz */ \
1 /* clock mode select (USB/normal): USB */ \
)

#define AIC23_REG8_44_1KHZ \
AIC23_9BITWORD( /* REG 8: sample rate control */ \
0, /* reserved */ \
0, /* clock output divider: 1 (MCLK) */ \
0, /* clock input divider: 1 (MCLK) */ \
1,0,0,0,1, /* sampling rate: ADC 44.1kHz DAC 44.1kHz */ \
1 /* clock mode select (USB/normal): USB */ \
)

#define AIC23_REG8_48KHZ \
AIC23_9BITWORD( /* REG 8: sample rate control */ \
0, /* reserved */ \
0, /* clock output divider: 1 (MCLK) */ \
0, /* clock input divider: 1 (MCLK) */ \
0,0,0,0,0, /* sampling rate: ADC 48kHz DAC 48kHz */ \
1 /* clock mode select (USB/normal): USB */ \
)

197
#define AIC23_REG8_96KHZ \
AIC23_9BITWORD( /* REG 8: sample rate control */ \
0, /* reserved */ \
0, /* clock output divider: 1 (MCLK) */ \
0, /* clock input divider: 1 (MCLK) */ \
0,1,1,1,0, /* sampling rate: ADC 96kHz DAC 96kHz */ \
1 /* clock mode select (USB/normal): USB */ \
)

#define AIC23_REG8_DEFAULT AIC23_REG8_48KHZ

#define AIC23_REG9_DEFAULT \
AIC23_9BITWORD( /* REG 9: digital interface activation */ \
0,0,0,0,0,0,0,0, /* reserved */ \
1 /* active */ \
)

/*
* Codec registers are kept in an object of the structure below.
*/
typedef struct AIC23_Params {
Uns regs[ AIC23_NUMREGS ];
} AIC23_Params;

/*
* define an AIC23_DEFAULTPARAMS with 10 default register values
*/
#define AIC23_DEFAULTPARAMS { \
AIC23_REG0_DEFAULT, \
AIC23_REG1_DEFAULT, \
AIC23_REG2_DEFAULT, \
198
AIC23_REG3_DEFAULT, \
AIC23_REG4_DEFAULT, \
AIC23_REG5_DEFAULT, \
AIC23_REG6_DEFAULT, \
AIC23_REG7_DEFAULT, \
AIC23_REG8_DEFAULT, \
AIC23_REG9_DEFAULT \
}

/*
* Declaration of public functions
*/

/*
* ========AIC23_init ========
*
* Initializes codec module variables, if any. (There are none.)
*/
extern Void AIC23_init();

/*
* ========AIC23_setParams ========
*
* This function takes a pointer to the object of type AIC23_Params,
* and writes all 11 control words found in it to the codec.
*/
extern Void AIC23_setParams(AIC23_Params *params);

#endif