Table 1: For conventional CMOS inverter Technology (nm) Total leakage power (nW) 70 8.1478 100 1.

8172 130 0.3635 180 0.2873

2: For forced NMOS transistor CMOS Technology (nm) 70 ## ## ##

Table 3: for forced PMOS transistor CMOS Technology (nm) Total leakage power (nW) 70 2.818 100 1.0102 130 0.2364 180 0.1278

Table 4: for force Technology (nm) 70 ## ## ##

power gating-Leakage power,

power gating

Techni

Power gating with PM

Power gating with NM SCCMOS with PMOS SCCMOS with NMOS

POWER GATING

SCCMOS

SLEEPY STACK

Product Type A

Comput Mobile Ha Digital H Automo

Enterpr

2: For forced NMOS transistor CMOS invertertional CMOS inverter Total leakage power (nW) 8.1478 0.1495 0.0897 0.0371

Table 4: for forced 2NMOS Total leakage power (nW) 0.5798 0.0761 0.0525 0.0112

SUMMARY OF ACTIVE MODE LEAKAGE CONTROL TECHNIQUES Technique Advantages Substantial leakage savings, Easeof Forced Stacking implementation, No need for controller design, Single threshold Sleepy Stack Lesser delay penalty compared to the Forced stacking method.

Power gating with stack

strong leakage savings in both operating modes

power gating-Leakage power,dynamic power and delay Technique LKG.PWr(pW) Base Pmos only Nmos only Nmos and Pmos

SUMMARY OF STANDBY MODE LEAKAGE CONTROL TECHNIQUES Technique Power gating with NMOS and PMOS sleep transistor Advantages Very high leakage power savings, Industry preferred technique

Power gating with PMOS sleep transistor Power gating with NMOS sleep transistor SCCMOS with NMOS PMOS and sleep transistors SCCMOS with PMOS sleep transistors SCCMOS with NMOS sleep transistors

delay penaltyis lesser as compared to 2 sleep transistors Lesser delay penalty compared to 2 sleep transistors.smaller sleep transistor as compared Best leakage power savings, single threshold easy to fabricate Lesser transistors, delay penalty compared to 2 sleep transistors.easy to sleep fabricaate Lesser delay penalty NMOS transistors size smaller than PMOS,easy to fabricaate

power gating-Leakage power,dynamic power, delay and power delay Technique Base Pmos only Nmos only Nmos and Pmos Base Pmos only Nmos only Nmos and Pmos LKG.PWr(pW) 30.12 33.54 26.12 4.55
30.12 28.35 25.72 3.15

Active Mode reduction-Leakage power,dynamic power, delay and power Technique Forced stacking sleepy stack power gating and stacking LKG.PWr(pW) 206.98 211.2 209

Power gating

Power gating

SCCMOS wi

SCCMOS wi

Product Type Application

Computing Mobile Handset Digital Home Automotive

Applications
Netbook, Smartbook,Tablet, EReader

Enterprise

Smart Phones , Feature Phones Set-Top-Box,DigitalTV, Blue Ray Player Navigation Laserjet Printers , Routers,Wireless Base Stations

ROL TECHNIQUES Limitations Increases circuit delay Lower leakage savings & comparable PDP static with respect to the forced stacking tecnique. Controler needed for sleep transistors,area penalty heavy delay penalty.Larger area fabricating dual threshold logic is a more compled process.

Dyn.Pwr(uW)

Delay(ps) PDP(static(1-2-21j) PDP(1-e-16J)

TROL TECHNIQUES Limitations sizing sleep transistors, controller design needed Increases circuit delay

lower leakage power savings compared to 2 sleep transistor structure lower leakage savingscontroller needed forpenalty sleep transistors. Large delay compled controller design order of magnitude lower leakage savings lower leakage power savings compared to 2 sleep transistorcircuits compled

wer, delay and power delay products Dyn.Pwr(uW) 7.23 7.445 6.955 7.16
7.23 7.44 6.998 7.1

Delay(ps) 77.8 81.412 84.37 88.9

77.8 81.364 83.65 88.04

PDP(stati PDP(1-e16J) c(1-2-21j) 23.4 2.73 2.203 0.404 23.4 2.306 2.151 0.277 5.62 6.06 5.85 6.36 5.62 6.05 583 6.25

c power, delay and power delay products Dyn.Pwr(uW) 7.35 7.56 7.15 Delay(ps) 79.72 79.47 90.2 PDP(stati PDP(1-ec(1-2-21j) 16J) 16.5 16.78 18.85 5.85 6 6.44

SUMMARY OF STANDBY MODE LEAKAGE CONTROL TECHNIQUES Technique Advantages Limitations sizing sleep Very high transistor leakage s, power controller savings, design Industry needed preferred Increases Power gating with NMOS and PMOS sleep techniqu circuit delay transistor e

delay penaltyis lesser as compare d to 2 sleep transistor s Power gating with PMOS sleep transistor Lesser delay penalty compare d to 2 sleep transistor s.smaller sleep transistor as compare d with PMOS case Power gating with NMOS sleep transistor

lower leakage power savings compare d to 2 sleep transistor structure

lower leakage savingsco ntroller needed for sleep transistor s.

Best leakage power savings, single threshold transistor SCCMOS with NMOS PMOS and sleep s, easy to transistors fabricate Large delay penalty compled controller design Lesser delay penalty compare d to 2 sleep transistor s.easy to fabricaat e Lesser delay penalty NMOS sleep transistor s size smaller than PMOS,ea sy to fabricaat e

SCCMOS with PMOS sleep transistors

order of magnitud e lower leakage savings lower leakage power savings compare d to 2 sleep transistor circuits compled controlle r.

SCCMOS with NMOS sleep transistors