CU HI N TP MN VI X L V VI IU KHIN

1. Vit CT chuyn d liu nh 40H (RAM ni) n nh 2000H (RAM ngoi). Bi lm: Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 128. c v ghi ram ngoi ta dng VK Atmega128 c chc nng h tr Ram ngoi. V iu khin c ghi ram ni ta cn phi set bit SRE ca thanh ghi MCUCR ln mc logic 1; Chng trnh lp trnh: #include <mega8.h> #define write_ram(addr,data) *((unsigned char *)(addr))=(data) // ghi d liu data vo RAM ti a ch addr #define read_ram(addr) *((unsigned char *)(addr)) // c Ram a ch addr void main (void) { char data; // mi nh cha 8 bit nn d liu dng char 8 bit data=read_ram(0x40); MCUCR=(1<<SRE); // Set bit SRE trong thanh ghi MCUCR c ghi Ram ngoi write_ram(0x2000,data); } 2. Vit CT chuyn d liu nh 2001H (RAM ngoi) vo nh 41H (RAM ni) Bi Lm: Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 128 c v ghi ram ngoi ta dng VK Atmega128 c chc nng h tr Ram ngoi. V iu khin c ghi ram ni ta cn phi set bit SRE ca thanh ghi MCUCR ln mc logic 1;

Chng trnh lp trnh: #include <mega128.h> #define write_ram(addr,data) *((unsigned char *)(addr))=(data) // ghi d liu data vo RAM ti nh c a ch addr #define read_ram(addr) *((unsigned char *)(addr)) void main (void) { MCUCR=(1<<SRE); // Set bit SRE trong thanh ghi MCUCR c ghi Ram ngoi char data; data=read_ram(0x2001); write_ram(0x41,data); } 3. Vit CT nhp d liu t PORTC vo nh 42H (RAM ni). Bi lm: Trong bi ny lp trnh trn phn mm codevisonAVR cho chip VK Atmega16. Chng trnh lp trnh: #include <mega16.h> #define write_ram(addr,data) *((unsigned char *)(addr))=(data) // ghi d liu data vo RAM ti a ch addr int main (void) { DDRC=0x00; // nh ngha PORTC l cng inport // Ly d liu t PORTC ghi vo nh c a write_ram(0x42,PORTC); ch 42h } 4. Cho mt chui d liu gm 20 byte lin tip trong RAM ni, bt u t a ch 20H. Hy vit CT ln lt xut cc d kiu ny ra PORTC. Bi lm:

Chng trnh lp trnh: #include <mega16.h> #define read_ram(addr) *((unsigned char *)(addr)) // c d liu Ram nh c a ch addr void main (void) { char i; DDRC=0xFF; for(i=0;i<20;i++) { PORTC=read_ram(32+i); // PORTC ly d liu ln lt t a ch 20h } } 5. Gi s PORTC c ni n mt thit b pht d liu (v d nh 8 nt nhn). Hy vit CT nhn lin tip 10 byte d liu t thit b pht ny v ghi vo 10 nh (RAM ni) lin tip bt u t nh 50H. Bi lm: Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 16 #include <mega16.h> #include <delay.h> #define read_ram(addr,data) *((unsigned char *)(addr))=(data) int main (void) { DDRC=0x00; char i; for(i=0;i<10;i++) { read_ram(80+i,PORTC); //50h +i delay_ms(500); } // nh ngha PORTC l outport

6. Vit CT to mt xung dng ( bit rng xtal l 12 MHz. Bi lm:

) ti chn P1.0 vi rng xung 1ms,

Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 16 to mt xung dng ti chn P1.0 hay PA.0 vi rng xung l 1ms ta s dng b nh thi Timer, trong bi ny tao s dng b nh thi TIMER0 ca Atmega 16; xc nh gi tr s ln trn v h s chia tn ta dng cng thc: n*p/Fclock=T( 0.001s); n: s ln trn p: l h s chia Fclock: tn s h thng 12.106 Hz Ta chn p=64( CS02=1 ) =>n=187. V yu cu ca bi ch to ra mt xung vung nn ta c chng trnh lp trnh nh sau: #include <mega16.h> #include < delay.h> int main(void) { DDRB=0xFF; PORTB.0=0x00; delay_ms(500); TCCR0=(1<<CS02); TCNT0=0; PORTB.0=0xFF; while(TCNT0<=187); PORTB.0 =~PORTB.0 delay_ms(500); } // H s chia l 64 trong Atmega 16 // Gi tr bt u ca Timer l 0 // Set PORTA.0 ln mc logic cao // i cho n khi TCNT0 n 187 ( tc 1ms) // Set bit PORTA.0 xung gi tr logic thp //nh ngha A l cng ra //Gi tr ban u cng A l 0 //Cho php Timer 0 ngt khi c trn

TIMSK=(1<<TOIE0);

7. Vit CT to chui xung vung c f = 100 KHz v c chu k lm vic D = 40% ti chn PORTC.2 (Xtal 12 MHz). Bi lm: Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 16 Ta dng b nh thi trong Atmega16 thc hin vic to xung vung nh yu cu bi. Chn Timer0 lm vic Xc nh cc gi tr theo cng thc sau: (256-TCNT0)*Prescaler = F/f; F: l tn s ca h thng f: l tn s cn thc hin Vi F= 12MHz; f=100KHz ta c (256-TCNT0)*Prescaler =120 Tuy nhin to ra c xung c chu k lm vic l D=40% th ta to ra 1 xung c chu k l 10 ln trn ca Timer0 trong 4 ln trn l xung cao cn 6 ln trn l xung thp. Do ta c 10*[(256-TCNT0)*Prescaler] =120 Prescaler=1 (CS00=1) v TCNT0=244 Chng trnh lp trnh nh sau: #include <mega16.h> char i=0; int main (void) { DDRC=0xFF; PORTC=0x00; TCCR0=(1<<CS00); TCNT0=244; TIMSK=(1<<TOIE0); #asm(sei); while (1); } interrupt [TIM0_OVF] void timer0_ovf_isr(void){ TCNT0=244; i++; // H c Prescaler =1 // Gi tr bt u m // Cho php Timer0 ngt khi trn // Cho php ngt ton cc // Vng lp v hn // PORTC l cng ra

if(i==10)i=0; if(i<4) PORTC.2 =1; } 8. Vit CT to chui xung vung c f = 10 KHz v c chu k lm vic D = 30% ti chn PORTC.3 (Xtal 24 MHz). Bi lm: Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 16 Ta dng b nh thi trong Atmega16 thc hin vic to xung vung nh yu cu bi. Chn Timer0 lm vic Xc nh cc gi tr theo cng thc sau: (256-TCNT0)*Prescaler = F/f; F: l tn s ca h thng f: l tn s cn thc hin Vi F= 24MHz; f=10KHz ta c (256-TCNT0)*Prescaler =2400 Tuy nhin to ra c xung c chu k lm vic l D=30% th ta to ra 1 xung c chu k l 10 ln trn ca Timer0 trong 3 ln trn l xung cao cn 7 ln trn l xung thp. Do ta c 10*[(256-TCNT0)*Prescaler] =2400 =>Prescaler=1 (CS00=1) v TCNT0=16 Chng trnh lp trnh nh sau: #include <mega16.h> char i=0; int main (void) { DDRC=0xFF; PORTC=0x00; TCCR0=(1<<CS00); TCNT0=16; TIMSK=(1<<TOIE0); #asm(sei); // 40% l chu k lm vic else PORTC.2 =~PORTC.2;

while (1); } interrupt [TIM0_OVF] void timer0_ovf_isr(void) { TCNT0=16; i++; if(i==10)i=0; if(i<3) PORTC.3=1; else } 9. Cho mt chui k t s di dng m ASCII trong RAM ni, di 20 byte, bt u t a ch 50H. Vit CT i cc k t s ny thnh m BCD. Bit rng m ASCII ca cc k t s l t 30H (s 0) n 39H (s 9). Bi lm: Trong bi ny lp trnh trn phn mm codevisionAVR cho chip VK Atmega 16. Ta bit rng m BCD ca cc s t 0-9 l: 0 1 2 3 4 5 6 7 8 9 0 1 2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 11 0000 11 0001 11 0010 (30h) // Chu k lm vic l 30% PORTC.3=~PORTC.3;

Trong khi m ASCII ca cc s t 0-9 l:

3 4 5 6 7 8 9

11 0011 11 0100 11 0101 11 0110 11 0111 11 1000 11 1001 (39h)

Ta nhn thy bin i m ASCII thnh m BCD ta ch cn ly gi tr ca m ASCII v AND vi 1111 V d: s 9 trong ASCII l 11 1001 v trong m BCD l 1001 vy c (11 1001) AND (1111) = 1001 Do vy ta c th vit chng trnh nh sau: #include <mega16.h> #define read_ram(addr) *((unsigned char *)(addr)) void main(void) { char *bcd,i=0; for(i=0;i<20;i++) { bcd[i]=(read_ram(50h+i)) &(0b1111); } } 10. Vit CT con mang tn DELAY500 c nhim v to tr 0,5ms dng Timer. (Xtal 6MHz). Bi lm: Trong bi ny lp trnh trn phn mm codevisonAVR cho chip VK Atmega 8. Ta s dng Timer0 trong Atmega8 nh thi cho hm tr. Vi n l s ln tng ca TCNT0 ta c (n*prescaler) =Xtal*t =6.106.0,5.10-3=3000. Ta chn Prescaler =32 tc (CS01=1 v CS00=1) => n=94; Vy nh thi 0,5ms vi tn s thch anh l 6Mhz th ta s dng timer0 vi h s chia 32 v gi tr TCNT0 tng thm n =94

Do vy ta c chng trnh lp trnh sau: #include <mega8.h> int main(void) { TCCR0=(1<<CS01)|(1<<CS00); // Chia tn 32 while(1){}; } int delay500(void) { TCNT0=0; while(TCNT0<94){}; // Tng TCNT0 n 94 th thot tng ng 0.5ms return 0; } 11. Dng CT con DELAY500 (bi 10) vit CT to sng vung f = 500Hz (D=25%) ti PORTC.2. Bi lm: Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 16 Vi tn s f =500Hz => chu k ca n l: T =1/f= 2ms. tha mn yu cu bi th PORTC.2 mc cao ng vi 1 ln delay500( 0,5ms) v mc thp vi 3 ln delay500(1,5ms). Do ta c chng trnh sau #include <mega16.h> void main(void) { DDRC=0xFF; PORTC=0x00; TCCR0=(1<<CS01)|(1<<CS00); // Chia tn 32 ln TIMER0 ca atmega128 while(1) { PORTC32=1; delay500(); PORTC.2=~PORTC.2; // Set PORTC.2 =1 // tr 0,5s // Set PORTC.2=0

delay500(); delay500(); delay500(); } } int delay500(void) { TCNT0=0; while(TCNT0<=94); return 0; } 12. Vit CT dng Timer to sng vung f = 4 KHz ti P1.5. (Xtal 12MHz). Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 16 Sng vung vi tn s f= 4KHz vy chu k ca n l: T=1/f =0,25ms. to c sng vung th mt na chu k P1.5 phi mc logic cao v na chu k cn li P1.5 phi mc logic thp. Do ta ch phi nh th mt khong thi gian l 0.125ms sau i trng thi ca P1.5 Dng Timer0 ta c: (256-TCNT0)*Prescaler = Xtal*T/2=12.106.0,125.10-3= 1500 Chn Prescaler=8 => TCNT0=68. Chng trnh lp trnh nh sau: #include <mega16.h> void main(void) { DDRA=0xFF; PORTA=0x00; TCCR0=(1<<CS01); TCNT0=69; TIMSK=(1<<TOIE0); asm(sei); while(1); } // 3 ln tr 0,5ms

interrupt [TIM0_OVF] void timer0_ovf_isr(void) { TCNT0=69; PORTA^=(1<<PA5); } 13. Vit CT c 1 chui data cha trong RAM ni t a ch 30H n 50H v xut ra 1 thit b (v d nh mn hnh tinh th lng LCD) c ni vi port ni tip ca VK (ch UART 8 bit, 9600 baud). Cho Xtal 12 MHz. Bi lm: Trong bi ny lp trnh trn phn mm AVR Studio cho chip VK Atmega 16. Khi bit tc BAUD ca truyn thng khng ng b ni tip ta s dng cng thc sau tnh ton gi tr thch hp gn cho thanh ghi UBRR UBRR = Xtal/(16*BAUD) -1 Vi iu kin u bai cho ta tnh c UBRR= 12.106/(16.9600) -1 = 77; Thanh ghi UBRR l thanh ghi 12 bit nn ph i gn gi tr UBRRH trc ri ti UBRRL #include <mega16.h> #include <delay.h> #define read_ram(addr) *((unsigned char *)(addr)) // Macro c ram char data[25] char i; int main (void) { for(i=0;i<32;i++) { data[i]=read_ram (48+i); } UBRRH=0; // Set tc truyn 9600 bps UBRRL=77; // vi tn s 12Mhx th UBRR=77 theo cng thc tnh trn UCSRA=0x00; UCSRB=(1<<TXEN); // Kch hot b pht d liu // c ln lt bt u t a ch 30h // T 30h n 50h c 32 nh // o gi tr khi xy ra ngt TIMER0

UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0); /* Set URESEL=1 bo rng chng ta khng mun truy cp thanh ghi UBRRH m l thanh ghi UCSRC. Set UCSZ1=1 v UCSZ0=1 chn ch truyn 8 bit */ while(1) { for(i=0;i<32;i++) { uart_transmit(i); delay_ms(100); } } } void uart_transmit(unsigned char d) { while(!(UCSRA &(1<<UDRE))); UDR=data[d]; } 14. Vit CT nhn 1 chui data t 1 thit b ngoi (v d nh my c m vch) ni vi VK qua port ni tip (ch UART 8 bit, 9600 baud) v ghi data vo RAM ni t a ch 40H. Bit rng chui data gm 20 byte v Xtal 12 MHz. Bi lm: Trong bi ny lp trnh trn phn mm AVR Studio cho chip VK Atmega 16. Khi bit tc BAUD ca truyn thng khng ng b ni tip ta s dng cng thc sau tnh ton gi tr thch hp gn cho thanh ghi UBRR UBRR = Xtal/(16*BAUD) -1 Vi iu kin u bai cho ta tnh c UBRR= 12.106/(16.9600) -1 = 77; Thanh ghi UBRR l thanh ghi 12 bit nn phi gn gi tr UBRRH trc ri ti UBRRL Chng trnh lp trnh nh sau: #include <mega16.h> #define read_ram(addr,data) *((unsigned char *)(addr))=(data) // i n khi UDR trng UDRE=1 // Truyn d liu lin tc 32 ln sau 100 ms

char i; int main (void) { UBRRH=0; // Set tc truyn 9600 bps UBRRL=77; // vi tn s 12Mhx th UBRR=77 theo cng thc tnh trn UCSRA=0x00; // Khng s dng nhn i tc v truyn thng a x l UCSRB=(1<<RXEN); // Kch hot b nhn d liu UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0); /* Set URESEL=1 bo rng chng ta khng mun truy cp thanh ghi UBRRH m l thanh ghi UCSRC. Set UCSZ1=1 v UCSZ0=1 chn ch truyn 8 bit */ while(1) { for(i=0;i<20;i++) { while(!(UCSRA & (1<<RXC))); // i qu trnh nhn kt thc ghiram(64+i,UDR); } } return 0; } 15. Vit CT dng ngt Timer to sng vung f=2 KHz ti PORTC.7. (Xtal 12MHz). Bi lm: Trong bi ny lp trnh trn phn mm CodevisonAVR cho chip VK Atmega 16 Sng vung vi tn s f= 2KHz vy chu k ca n l: T=1/f =0,5ms. to c sng vung th mt na chu k PORTC.7 phi mc logic cao v na chu k cn li PORTC.7 phi mc logic thp. Do ta ch phi nh th mt khong thi gian l 0.25ms sau i trng thi ca PORTC.7 Dng Timer0 ta c: (256-TCNT0)*Prescaler = Xtal*T/2=12.106.0,25.10-3= 3000 Chn Prescaler=32 => TCNT0=162. Chng trnh lp trnh nh sau: // Ghi vo Ram bt u t nh c a ch 40h // lp li 20 ln // Vng lp v hn

#include <mega16.h> int main (void) { DDRC=0xFF; PORTC=0x00; TCCR0=(1<<CS01)|(1<<CS00); // Chn Prescaler 32 trong Atmega128 TCNT0=162; TIMSK=(1<<TOIE0); asm(sei); while(1){}; return 0; } interrupt [TIM0_OVF] void timer0_ovf_isr(void) { TCNT0=162; PORTC.7^=1; } 16. Vit CT ly 1 chui data cha trong Ram ngoi bt u t a ch 0000H n a ch 00FFH v xut ra PORTC, mi ln xut cch nhau 500ms. S dng ngt Timer. Xtal 12MHz. Bi lm: Trong bi ny c lp trnh trn codevisonAVR cho VK Atmega128 h tr Ram ngoi. nh thi mi ln cch nhau 500 ms th phi s dng timer 16 bit. Ta s dng TIMER1. Xc nh gi tr ban u vo h s Prescaler ta dng cng thc sau: (65536-TCNT1)*Prescaler=Xtal*T Vi Xtal =12.106Hz v T=0,5s ta c: (65536-TCNT1)*Prescaler=12.106.0,5=6.106 Chn Prescaler =1024 ( CS12=1 v CS10=1 trong Atmega 128) do c TCNT1 = 65536 5859 = 59677 (E91Dh) Vy TCNT1H=0xE9; v TCNT1L=0x1D; // mi ln trn gi tr ban u c gn l 162 //o bit mi khi c ngt Timer0 // Gi tr m ban u // Cho php ngt TIMER0 khi xy ra trn // Cho php ngt ton cc //nh ngha PORTC l outport

#include <mega128.h> #define read_ram(addr) *((unsigned char *)(addr)) // Macro c d liu Ram char i=0; int main(void) { DDRC=0xFF; PORTC=0x00; TCCR1B=(1<<CS12)|(1<<CS10); TIMSK=(1<<TOIE1); TCNT1H=0xE9; TCNT1L=0x77; asm(sei); while(1){} } interrupt [TIM1_OVF] void timer1_ovf_isr(void) { TCNT1H=0xE9; TCNT1L=0x77; PORTC=read_ram(i); i++; } 17. Vit CT pht lin tc chui s t 0 n 9 ra port ni tip theo ch UART 8 bit, 9600 baud. S dng ngt serial. Xtal 12MHz. Bi lm: Trong bi ny lp trnh trn phn mm AVR studio cho chip VK Atmega 16 Khi bit tc BAUD ca truyn thng khng ng b ni tip ta s dng cng thc sau tnh ton gi tr thch hp gn cho thanh ghi UBRR UBRR = Xtal/(16*BAUD) -1 Vi iu kin u bai cho ta tnh c UBRR= 12.106/(16.9600) -1 = 77; // c ram t nh c a ch 0000h-00FFh // khi i =256 s trn v chuyn v gi tr 0 do char l 8 bit // Chia tn 1024 trong Atmega128 // Cho php ngt TIMER1 khi c trn // t gi tr m ban u l 59677 // vo thanh ghi TCNT1 16 bit // Cho php ngt ton cc

Thanh ghi UBRR l thanh ghi 12 bit nn phi gn gi tr UBRRH trc ri ti UBRRL #include <avr/io.h> #include <avr/interrupt.h> unsigned char i; ISR(USART0_TX_vect) { UDR0=i; if(++i>9) i=0; } int main (void) { UCSR0A=0x00; // Khng s dng nhn i tc v truyn thng a x l UCSR0B = (1<<TXEN0)|(1<<TXCIE0) ; // Cho php ngt serial khi truyn UCSR0C =(1<<UCSZ01)|(1<<UCSZ00); // Chn ch truyn 8 bit UBRR0H = 0; UBRR0L = 77; // Tc truyn l 9600 bps vi tn s thch anh l 12MHz sei(); while(1) {} } 18. Vit CT ch nhn data t 1 thit b ngoi gi n VK qua port ni tip (ch UART 8 bit, 9600 baud). Nu nhn c k t STX (02H) th bt sng LED, nu nhn c k t ETX (03H) th tt LED, bit rng LED c iu khin bng ng PC.3 (LED sng khi bit iu khin bng 1). S dng ngt serial. Xtal 12MHz. Bi lm: #include <avr/io.h> #include <avr/interrupt.h> int main(void){ DDRD=0x00; PORTD=0x00;

GICR=(1<<INT0); MCUCR=(1<<ISC01)|(1<<ISC00); UBRRH=0; UBRRL=71; UCSRA=0x00; UCSRB=(1<<TXEN); UCSRC=(1<<URSEL)|(1<<UCSZ0)|(UCSZ1); sei(); while(1){}; } ISR(INT0_vect) { while(!(UCSRA & (1<<RXC))){}; if(UDR==0x02)PORTC.3=1; if(UDR==0x03)PORTC.3=0; } 19. Vit CT ch nhn 1 xung cnh xung a vo chn ngt ngoi INT0, khi c xung th nhp data t PORTC v pht ra port ni tip ch UART 8 bit 9600 baud. Xtal 6MHz. Bi lm: #include <avr/io.h> #include <avr/interrupt.h> int main(void){ DDRD=0x00; PORTD=0x00; DDRC=0x00; PORTC=0x00; GICR=(1<<INT0); MCUCR=(1<<ISC01); // Xung canh xuong o TNT0

UBRRH=0; UBRRL=47; // toc do 9600 bps F= 7.3728 MHz UCSRA=0x00; UCSRB=(1<<TXEN); UCSRC=(1<<URSEL)|(1<<UCSZ0)|(UCSZ1); sei(); while(1){}; } ISR(INT0_vect) { while(!(UCSRA & (1<<UDRE))){}; UDR=PORTC; } 20. Vit CT m s xung a vo chn INT0 v iu khin relay thng qua chn PORTC.0 (relay ng khi PORTC.0 bng 1), ct s m vo nh 40H ca Ram ni, nu s m cha n 100 th ng relay, nu s m t 100 th ngt relay. Bi lm: #include <avr/io.h> #include <avr/interrupt.h> #define write_ram(addr,data) *((unsigned char *)(addr))=(data) char i=0; int main(void){ DDRD=0x00; PORTD=0x00; GICR=(1<<INT0); MCUCR=(1<<ISC01)|(1<<ISC00); // Xung canh xuong o TNT0 sei(); while(1){}; } ISR(INT0_vect)

{ i++; read_ram(0x40,i); if(i<100) PORTC=1; else PORTC=0; }