AMEYA R.

AGNIHOTRI
1534 Vista Club Circle, #302, Santa Clara, CA 95054 (614) 288-1472 ameya@cs.binghamton.edu http://www.cs.binghamton.edu/ameya

RESEARCH INTERESTS : Physical design challenges for Integrated Circuits The presence of billions of components makes todays integrated circuits one of the most complex man made systems. This makes the design process very challenging; strong algorithmic breakthroughs are necessary. My research interests span various aspects of the physical design challenges for current and next generation integrated circuits. The general area is also known as Computer-Aided Design (CAD) for Very Large Scale Integration (VLSI). My research has been published in well known international conferences, journals, books and one pending United States Patent. My work has close to 100 citations. Optimization techniques for solving intractable problems Many real world problems involve optimization (minimization/maxization) of an objective funtion subject to several constraints. I am interested in various optimization techniques (combinatorial/continuous) and their application to solve real world intractable problems. Design and analysis of algorithms. EDUCATION : Ph.D. in Computer ScienceAugust 2002 - May 2007 State University of New York at Binghamton, NY Dissertation : Combinatorial Optimization Techniques for VLSI Placement GPA: 4.0/4.0 M.S. in Computer ScienceAugust 2000 - August 2002 State University of New York at Binghamton, NY Thesis : Layer Balancing for VLSI Circuit Design. GPA: 3.8/4.0 B.E. in Electronics & TelecommunicationsAugust 1994 - June 1998 Government College of Engineering, Pune, India First class with Distinction WORK EXPERIENCE : Magma Design Automation, Santa Clara, CADecember 2006 - Present Senior Member of Technical Staff R & D Group Work involves design and development of techniques to improve Magmas state-of-the-art leading-edge physical design software tools for current and next generation Integrated Circuits. Underlying problems are large-scale, complex and need fast and high quality solutions. Solution quality directly effects the performance of the Integrated Circuits. Synopsys Inc., Hillsboro, ORApril 2005 - September 2005 Research Intern Advanced Technology Group

 Worked on a research project for the well-known and challenging buffering problem in physical design of Integrated Circuits. Implemented a methodology to detect post layout buffer-count and buffer-detours in Synopsyss state-of-the-art physical design tool IC Compiler. Developed incremental placement and routing algorithms to eliminate such instances and improve the layout. State University of New York at Binghamton, NYSummer 2004 - Summer 2005, Summer 2003/2002 Graduate Research Assistant Computer Science Department My research was related to the design and development of placement and routing algorithms for todays multi-million gates Integrated Circuits. Research in my group was funded by various companies and agencies including ACM SIGDA, IBM, Intel, National Science Foundation and Semiconductor Research Corporation. My research resulted in numerous publications which have close to 100 citations (listed below). Software developed by me as part of this research is among the state-of-the-art in the academic circle and is used by top universties in and outside United States to compare results. State University of New York at Binghamton, NYSpring 2001 - Spring 2004 Graduate Teaching Assistant Computer Science Department I was the Teaching Assistant for various graduate and undergraduate level courses including Design and Analysis of Algorithms, VLSI Algorithms and Operating Systems. Responsibilities included helping students with the projects, conducting lab sessions, setting and grading exams and projects. Tata Infotech Limited, Mumbai, IndiaOctober 1998 - June 2000 Systems Engineer Systems Integration Department Part of a team that developed a Property Management System for a US-based client. PUBLICATIONS : Patent A. R. Agnihotri, P. H. Madden, Standard Block Design: An Effective Approach for Large Scale Floorplanning, U.S. patent pending. Book Chapters A. R. Agnihotri, S. Ono, M. C. Yildiz, P. H. Madden, Large Scale Circuit Placement, High-Performance Energy-Efcient Microprocessor Design, Springer 2006 (Editors V. G. Oklobdzija, R. K. Krishnamurthy). A. R. Agnihotri, S. Ono, P. H. Madden, Placement for Power Optimization, Closing the POWER Gap between ASIC & Custom: Tools and Techniques for Low Power Design, Springer 2006 (Editors D. Chinnery, K. Keutzer). A. R. Agnihotri, P. H. Madden, Legalization and Detailed Placement, to appear in The Handbook of Algorithms for VLSI Physical Design Automation (Editors C. J. Alpert, D. P. Mehta, Sachin S. Sapatnekar). Journals A. R. Agnihotri, S. Ono, C. Li, M. C. Yildiz, A. Khatkhate, C.-K. Koh, P. H. Madden, Mixed Block Placement via Fractional Cut Recursive Bisection, IEEE Transactions on CAD, Vol 24, No. 5, pages 748-761, May 2005 (8 citations).

 Conferences A. R. Agnihotri, P. H. Madden, Fast Analytic Placement using Minimum Cost Flow, Asia South Pacic Design Automation Conference, Yokohama, Japan, January 2007 (Nominated for best paper award). A. R. Agnihotri, S. Ono, P. H. Madden, Recursive Bisection Placement : Feng Shui 5.0 Implementation Details, International Symposium on Physical Design, San Francisco, CA, April 2005 (17 citations). P. Ramachandran, A. R. Agnihotri, S. Ono, P. Damodaran, H. Srihari, P. H. Madden, Optimal Placement by Branch-and-Price, Asia South Pacic Design Automation Conference, Shanghai, China, January 2005 (1 citation). A. Khatkhate, C. Li, A. R. Agnihotri, M. C. Yildiz, S. Ono, C.-K. Koh, P. H. Madden, Recursive Bisection Based Mixed Block Placement, International Symposium on Physical Design, Phoenix, AZ, April 2004 (39 citations). A. R. Agnihotri, M. C. Yildiz, A. Khatkhate, A. Mathur, S. Ono, P. H. Madden, Fractional Cut : Improved Recursive Bisection Placement, International Conference on Computer Aided Design, San Jose, CA, November 2003 (32 citations). A. R. Agnihotri, P. H. Madden, Congestion Reduction in Traditional and New Routing Architectures, Great Lakes Symposium on VLSI, Washington DC, April 2003 (4 citations). TECHNICAL SKILLS : Programming Languages C, C++, Java, Perl, Haskell, Prolog, LINC, HTML, PL/SQL, JDBC, Lex/Flex/Bison Operating Systems Linux, Unix, Windows Tools Magma BlastFusion, Synopsys IC Compiler, Cadence QPlace/Warp-Route AWARDS/PROFESSIONAL ACTIVITIES : Best paper award nomination for my paper in the Proceedings of Asia and South Pacic Design Automation Conference 2007, a leading international conference in the eld of Design Automation of Integrated Circuits. (Only 9 papers selected out of over 400 submitted papers) Member of the Technical Program Committee of the 2008 International Symposium on Physical Design. 11 people from industry and 10 from academia have been selected to be on the committee. Reviewer for the following international journals: IEEE Transactions on Computer-Aided Design (TCAD). ACM Transactions on Design Automation of Electronic Systems (TODAES). IEEE Transactions on VLSI (TVLSI). Reviewer for the following international conferences/symposia: International Conference for Computer-Aided Design (ICCAD). International Symposium on Circuits and Systems (ISCAS). Design Automation Conference 2004/2003 : ACM/SIGDA University Booth Grant.

 International Conference for Computer-Aided Design 2004 : ACM/SIGDA CADAthlon grant. Professional Member of Association for Computing Machinery (ACM). Merit Certicate in Mathematics Olympiad Examination at All-India level in 1994. EXTRA CURRICULAR ACTIVITIES/HOBBIES : Table Tennis, National Level, India. Lawn Tennis, Ranked 25th in the central Ohio region for 2006. Played for my undergrad Cricket team. Golf, Sketching, watercolor painting.