CMOS

Digital Integrated Circuits

Analysis and Design

Chapter 3

MOS Transistor

The Metal Oxide Semiconductor (MOS) structure

The structure consists of three layer

The metal gate electrode The insulating oxide (SiO2) layer The p-type bulk semiconductor

The basic properties of the semiconductor

The mass action law:n p = ni2 Assume the substrate doping concentration N A ni2 then pn 0 , p p0 N A NA
2

Energy band diagram of a p-type silicon substrate

The Fermi potential F =

EF -Ei q n kT ln i q NA kT N D ln q ni

For a p-type semiconductor, Fp = For a n-type semiconductor, Fn =

The energy required for an electron to move from the Fermi level int o free space is called the work function qs = q + (Ec -EF )

Energy diagram of the combined MOS system

The equilibrium Fermi levels of the semiconductor (Si) substrate and the metal gate are at the same potential The bulk Fermi level is not significantly affected by the bending The surface Fermi level moves closer to the intrinsic Fermi level

Example 1

The MOS System under External Bias - accumulation

A negative voltage VG is applied to the gate electrode.

The holes in the p-type substrate are attracted to the semiconductoroxide surface The majority carrier concentration > the equilibrium hole concentration
The electron concentration (minority carrier) decreases as the negatively charged electron are pushed deeper into the substrate

The oxide electric field is directed towards the gate electrode Causing the energy bands bend up-ward near the surface
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The MOS System under External Bias depletion A small positive gate bias VG is applied to the gate electrode
The oxide electric field will be directed towards the substrate Causing the energy bands to bend downward near the surface The majority carrier (hole) will be repelled backed into the substrate
Leaving negatively charged fixed acceptor ions behind (depletion region)
dQ = q N A dx d s = x dQ q N A x = dx dx Si
xd

s
F

d s =

q NA x

Si

dx

s F =
xd =

2 q N A xd

Si

2 Si s F q NA

Q = q N A xd = 2q N A Si s F
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The MOS System under External Bias inversion

A further increase in the positive gate bias
Increasing surface potential Bthe downward bending of the energy bands will increase The mid-gap energy level Ei becomes smaller than the Fermi level EFp on the surface
The substrate semiconductor in this region become n-type The electron density is larger than the majority hole density Inversion layer, surface inversion Can be utilized for conducting current between two terminal of the MOS transistor The density of mobile electrons on the surface becomes equal to the density of holes in the bulk substrate Requiring the surface potential has the same magnitude, but the reverse polarity, as the bulk Fermi potential F Further increase gate voltage B electron concentration B but not to an increase of the depletion depth

The surface is said to be inverted

xdm =

2 Si 2F q NA

The physical structure of a n-channel enhancement-type MOSFET

MOS structure
polysilicon gate, thin oxide layer, semiconductor The current conducting terminals of the device
Conducting channel, channel length L, channel width W

Source, drain n+-region

The device structure is completely symmetrical with respect to the drain and source Controlling the current conduction between the source and the drain, using the electric field generated by the gate voltage as a control variable 9

The simple operation of this device

Circuit symbols for enhancement-type MOSFET

Enhancement-mode MOSFET
No conducting region at zero gate bias

Depletion-mode MOSFET
A conducting channel already exists at zero gate bias

The abbreviations used for device terminals are

G for the gate, D for the drain, S for the source, and B for the substrate

The small arrow always marks the source terminal

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Formation of a depletion region

For small gate voltage level

The majority carriers (holes) are repelled back into the substrate The surface of the p-type substrate is depleted Current conduction between S and D is not possible

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Formation of an inversion layer

As the gate-to-source voltage is further increased

The surface potential reaches -Fp B surface inversion will be established B conducting channel between S and D Allowing current flow, as log as there is a potential difference between S and D VGS<VT0 (threshold voltage)
Not sufficient to establish an inversion layer No current between S and D Electrons are attracted to the surface
Contributing to channel current conduction

VGS>VT0 (threshold voltage) Further increase gate voltage

Not affect the surface potential and the depletion region depth

12

The threshold voltage

Four physical components of VT0
The work function difference between gate and the channel
GC= F(substrate)- M for metal gate GC= F(substrate)- F(gate) for polysilicon gate

Compared with the p-MOSFET

The substrate Fermi potential F is negative in NMOS, positive in pMOS The depletion region charge densities QB0 and QB are negative in nMOS, positive in pMOS The substrate bias coefficient is positive in nMOS, negative in pMOS The substrate bias voltage VSB is positive in nMOS, negative in pMOS

The gate voltage component to change the surface potential

To change the surface potential by -2F

The gate voltage component to offset the depletion region charge

-QB/Cox
QB = 2q N A Si 2 F + VSB Cox =

ox
tox

The voltage component to offset the fixed charge in the gate oxide and in the silicon-oxide interface
-Qox/Cox V = 2 QB 0 Qox (no body effect) T0 GC F
VT = VT 0 + Cox Cox

Threshold voltage adjustment

Implanting p-type impurity B VT increased Implanting n-type impurity B VT decreased The amount of change in the threshold voltage
Shift qNI/Cox

2 F + VSB 2 F (with body effect) 2q N A Si Cox

where =

13

Example 2

14

Circuit symbols for n-channel depletion-type MOSFETs

Using selective ion implantation into the channel

The threshold voltage for nMOSFET can be made negative Having a conducting channel at VGS=0

15

Example 3

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MOSFET operation: linear region

The MOSFET consists
A MOS capacitor, two pn junction adjacent to the channel The channel is controlled to the MOS gate

The carrier (electron in nMOSFET)

Entering through source, controlling by gate, leaving through drain

To ensure that both p-n junctions are reverse-biased initially

The substrate potential is kept lower than the other three terminal potentials

When 0<VGS<VT0
G-S region depleted, G-D region depleted No current flow

When VGS>VT0
Conduction channel formed Capable of carrying the drain current As VDS=0
ID=0

As VDS>0 and small

ID proportional to VDS Flowing from S to D through the conducting channel The channel act as a voltage controlled resistor The electron velocity much lower than the drift velocity limit As VDSBthe inversion layer charge and the channel depth at the drain end start to decrease 17

MOSFET operation: saturation region

For VDS=VDSAT
The inversion charge at the drain is reduced to zero Pitch off point

For VDS>VDSAT
A depleted surface region forms adjacent to the drain As further increases VDS B this depletion region grows toward the source The channel-end remains essentially constant and equal to VDSAT The pitch-off (depleted) section
Absorbing most of the excess voltage drop, VDS-VDSAT A high-field forms between the channel-end of the drain boundary
Accelerating electrons, usually reaching the drift velocity limit 18

MOSFET current-voltage characteristics-gradual channel approximation (GCA)(1)

Considering linear mode operation
VS=VB=0, the VGS and VDS are the external parameters controlling the drain current ID VGS > VT0 (assume constant through the channel) to create a conducting inversion layer Defining
X-direction: perpendicular to the surface, pointing down into the substrate Y-direction: parallel to the surface
The y=0 is at the source end of the channel Channel voltage with respect to the source, Vc(y)

Assume the electric field Ey is dominant compared with Ex

QI(y)=-Cox[VGS-Vc(y)-VT0]

This assumption reduced Bthe current flow in the channel to the y-direction only

Let QI(y) be the total mobile electron charge in the surface inversion layer

19

MOSFET current-voltage characteristics-gradual channel approximation (GCA)(2)

Assumeing that all mobile electrons in the inversion layer has a constant surfacr mobility n dR = dy (mimus sign is due to the negative polarity of the inversion layer charge QI ) W n QI (y)

The electron surface mobility n dependents on the doping concentration of the channel region, and its magnitude is typically about one - half of that of the bulk electron mobility ID dVC = I D dR = dy W n QI (y)

I D dy = W n
0

VDS

QI ( y ) dVC

I D L = W n Cox ID =

VDS

(VGS VC VT 0 ) dVC

n Cox W

2 L ' k W 2 I D = 2 (VGS VT 0 )VDS VDS where k ' = nCox 2 L k W 2 I D = 2 (VGS VT 0 )VDS VDS where k = k ' 2 L

2 2 (VGS VT 0 )VDS VDS

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Example 4

21

MOSFET current-voltage characteristics-gradual channel approximation (GCA)-saturation region

For VDSVDSAT=VGS-VT0

I D ( sat ) =

n Cox W

2 C = n ox 2

L W 2 (VGS VT 0 ) L

2 (VGS VT 0 ) (VGS VT 0 ) (VGS VT 0 )

The drain current becomes a function only of VGS, beyond the saturation boundary
22

Channel length modulation

The inversion layer charge at the source end of the channel is QI (y = 0 ) = -Cox (VGS -VT 0 ) and the inversion layer charge at the drain end of the channel is QI (y = L) = -Cox (VGS -VT 0 VDS ) Note that at the edge of saturation , VDS = VDSAT = VGS -VT 0 The inversion layer charge at the drain end become very small QI (y = L) 0 The effective channel length L' = L-where is the length of the channel segment wi th QI = 0 I D(sat) = n Cox W 2 ' (VGS VT 0 ) L 2 1 C W n ox ' (VGS VT 0 )2 = L 1 L 2 L

I D(sat)

L VDS VDSAT L 1 VDS , channel length modulation coefficient L Assuming that DS << 1 We use 1 I D(sat) = n Cox W 2 (VGS VT 0 ) (1 + VDS ) L 2

23

Substrate bias effect

The discussion in the previous has been done under the assumption
The substrate potential is equal to the source potential, i.e. VSB=0

On the other hand

the source potential of an nMOS transistor can be larger than the substrate potential, i.e. VSB>0 VT (VSB ) = VT 0 + 2F + VSB 2F

I D (lin ) = I D ( sat )

n Cox W

2 C = n ox 2

L W 2 (VGS VT (VSB ) ) (1 + VDS ) L

2 2 (VGS VT (VSB ) )VDS VDS

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Current-voltage equation of n-, p-channel MOSFET

For n - channel MOSFET I D = 0, for VGS < VT I D ( lin ) =

n Cox W
2 L

2 for VGS VT 2 (VGS VT )VDS VDS

and VDS < VGS -VT I D ( sat ) =

n Cox W
2 L

(VGS VT ) (1 + VDS ) for VGS VT

2

and VDS VGS -VT For p - channel MOSFET I D = 0, for VGS > VT I D ( lin ) =

n Cox W
2 L

2 for VGS VT 2 (VGS VT )VDS VDS

and VDS > VGS -VT I D ( sat ) =

n Cox W
2 L

(VGS VT ) (1 + VDS ) for VGS VT

2

and VDS VGS -VT

25

Measurement of parameters- kn, VT0, and The VSB is set at a constant value
The drain current is measured for different values of VGS VDG=0
VDS>VGS-VT is always satisfied B saturation mode Neglecting the channel length modulation effect
kn kn 2 (V GS V T 0 ) , I D = (V GS V T 0 ) 2 2 Obtaining the parameters kn, VT0, and VT (VSB ) VT 0

I D ( sat ) =

2F + VSB 2F

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Measurement of parameters-
The voltage VGS is set to VT0+1 The voltage VDS is chosen sufficiently large (VDS>VGS-VT0) that the transistor operates in the saturation mode, VDS1, VDS2
ID(sat)-(kn/2)(VGS-VT0)2(1+VDS)
Since VGS=VT0+1BID2/ID1=(1+VDS2)/ (1+VDS1) Which can be used to calculate the channel length modulation coefficient This is in fact equivalent to calculating the slope of the drain current versus drain voltage curve in the saturation region
The slope is kn/2

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Example 5

28

MOSFET scaling and small-geometry effects

High density chip
The sizes of the transistors are as small as possible The operational characteristics of MOS transistor will change with the reduction of iys dimensions Full scaling (constant-field scaling) Constant-voltage scaling every two or three years The down-scaling factor S about 1.2 to1.5

There are two basic types of size-reduction strategies

A new generation of manufacturing technology replaces the previous one about The scaling of all dimensions by a factor of S>1 leads to the reduction of the area occupied by the transistor by a factor of S2

29

Full scaling (constant-field scaling)

To achieve this goal, all potentials must be scaled down proportionally, by the same scaling factor Assuming the surface mobility n is not significantly affected by the scaled doping density The gate oxide capacitance per unit area C 'ox =

ox
t
' ox

=S

ox
tox

= S Cox

The aspect ratio W/L unchanged the k n will also scaled by a factor of S The linear mode drain current
' kn ' ' '2 VT' VDS VDS I (lin) = 2 VGS 2 I D(lin) S kn 1 2 = 2 2 VGS VT VDS VDS = 2 S S The saturation mode drain current ' D

[ (

[ (
)
2

' kn ' VGS VT' 2 The power dissipation ' ID (sat) = ' ' VDS = P' = I D

S kn 1 VGS VT 2 S2

I D(sat) S

1 P I D VDS = 2 2 S S The significant reduction of the power dissipation is one of the most attractive features of full scaling The power density per unit area remaining virtually unchanged C g is scaled down by a factor of S the charge - up, and charge - down time improved A reduction of various parasitic capacitances abd resistances

30

Constant-voltage scaling
All dimensions of the MOSFETare reduced by a factor of S . The power supply voltage and the terminal voltages remained unchanged. The doping densities must be increased by a factor of S 2 in order to preserve the charge - field relations The gate oxide capacitance per unit area Cox is increased by a factor of S The transconductance parameter is also increased by S The linear mode drain current
' kn ' ' '2 VT' VDS VDS I (lin) = 2 VGS 2 S kn 2 = 2 (VGS VT ) VDS VDS = S I D(lin) 2 The saturation mode drain current ' D

[ (

' 2 kn S kn 2 ' VT' = (VGS VT ) = S I D(sat) I (sat) = VGS 2 2 The drain current density increased by a factor of S 3 ' D

The power dissipation

' ' P' = I D VDS = (S I D ) VDS = S P

The power density incresaed by a factor of S 3 To summarized, constant - voltage scaling may be preferred over full scaling in mamy practical cases because of the external voltage - level constraints. Disadv. increasing current density, power density electromigration, hot carrier degradation, oxide breakdown, and electrical over - stress

31

Short-channel effects A MOS transistor is called a short-channel device

If its channel length is on the same order of magnitude as the depletion region thickness of the S and D junction The effective channel length Leff S, D junction depth xj Two physical phenomena arise from short-channel effects
The limitations imposed on electron drift characteristics in the channel
The lateral electric field Ey increased, vd reached saturation velocity L I = W v q n( x) dx = W vd ( sat ) QI = W vd ( sat ) Cox VDSAT D ( sat ) d ( sat )
eff

No longer a quadratic function of VGS, virtually independent of the channel length The carrier velocity in the channel also a function of Ex Influence the scattering of carriers in the surface no no (eff ) = no = =
n

1 + Ex

1+

ox (VGS Vc ( y ) ) 1 + (VGS VT ) tox Si

The modification of the threshold voltage due to the shortening channel length

32

Short-channel effects-modification of VT
The n+ drain and source diffusion regions in p-type substrate induce a significant amount of depletion charge
The long channel VT, overetimates the depletion charge support by the gate voltage The bulk depletion region B asymmetric trapezoidal shape
A significant portion of the total depletion region charge is due the S and D junction depletion VT 0(short channel) = VT0 - VT0
L + LD QB 0 = 1 S 2 q Si N A 2F 2L xdS = kT N D N A 2 Si 2 Si 0 , xdD = (0 + VDS ), 0 = ln n2 q NA q NA q i
2 2

(x

2 + xdD ) = xdm + (x j + LD )

2 2 L2 D + 2 x j LD + xdm xdD 2 x j xdD = 0

2 2 1 + 2 xdD 1 LD = x j + x 2 x x x x x + 2 j dm dD j dD j xj 2x LS x j 1 + dS 1 xj x j 1 2x 2x VT 0 = 2 q Si N A 2F 1 + dD 1 + 1 + dS 1 Cox xj xj 2 L 33

Example 6 (1)

34

Example 6 (2)

35

Example 6 (3)

36

Narrow-channel effect
Channel width W on the same order of magnitude as the maximum depletion region thickness xdm The actual threshold voltage of such device is larger than that predicted by the conventional threshold voltage Fringe depletion region under field oxide V (narrow channel) = V + V T0 T0 T0

VT0 =

xdm 1 2q Si N A 2F Cox W

for depletion region modeled by quarter - circular arcs

37

Other limitations imposed by small-device geometries

The current flow in the channel are controlled by two dimensional electric field vector Subthreshold conduction
qDnWxc n0 kTr kT ( AVGS + BVDS ) I D ( subthreshold ) e e LB Punch-through
The gate voltage loses its control upon the drain current, and the current rises sharply Pinholes, oxide breakdown Drain-induced barrier lowering (DIBL) A nonzero drain current ID for VGS<VT0
q q

Gate oxide thickness tox scaled to tox/S, is restricted by processing difficulties

Hot-carrier effect

38

MOSFET capacitances
L=LM-2LD
L: the actual channel length LM: the mask length of the gate LD: the gate-drain, the gatesource overlap
On the order of 0.1m

39

Oxide related capacitance(1)

The gate electrode overlap capacitance
CGD(overlap)=CoxWLD CGS(overlap)=CoxWLD
With Cox=ox/tox

Both capacitance do not depend on the bias condition, they are voltage-independent

The capacitances result from the interaction between the gate voltage and the channel charge
Cut-off mode
Cgs=Cgd=0 Cgb=CoxWL

Linear mode
Cgb=0 CgsCgd (1/2) CoxWL

Saturation mode
Cgb= Cgd =0 Cgs (2/3) CoxWL
40

Oxide related capacitance(2)

The sum of all three voltage-dependent (distributed) gate oxide capacitances (Cgb+Cgs+Cgd)
A minimum value of 0.66CoxWL, in saturation mode A maximum value of CoxWL, in cut off and linear modes For simple hand calculation
The three capacitances can be considered to be in parallel A constant worst-case value of CoxW(L+2LD) can be used for the sum of MOSFET gate oxide capacitances

41

Junction capacitance(1)
The depletion region thickness xd = The built - in potential 0 = 2 Si N A + N D (0 V ) q N A ND

kT N A N D ln n2 q i N A ND N A ND The depletion region charge Q j = A q N +N xd = A 2 Si q N + N (0 V ) D A D A dQ j dV = A Si q N A N D 1 2 N A + N D 0 V

The junction capacitance C j = C j(V) = AC j 0 V 1 0

m

, the parameter m is grading coefficient

The zero bias junction capacitance per unit area C j 0 =

Si q N A N D 1 2 N A + N D 0

The equivalent large - signal capacitance can be defined as Ceq =

V2 Q Q j(V2 ) Q j (V1 ) 1 = = C j(V)dV V V2 V1 V2 V1 V1

V 1 m V 1 m 1 2 = 1 1 (V2 V ) (1 m ) 0 0 For the special case of abrupt pn - junctions A C j 0 0 Ceq = 2 A C j 0 0 V V 1 2 1 1 (V2 V ) 0 0 Ceq = A C j 0 K eq K eq = 2 0 0 V2 0 V1 V2 V1

42

Example 7

43

Junction capacitance(2)
The sidewalls of a typical MOSFET source or drain diffusion region are surrounded by a p + channel - stop implant, with a higher doping density than the substrate doping density N A Assume the sidewall doping density is given by N A(sw) , the zero - bias capacitance per unit area can be found as C j 0 sw N A(sw) N D 1 Si q = 2 N A(sw) + N D 0 sw

C jsw = C j 0 sw x j The sidewall voltage equivalence factor K eq ( sw) = 2 0 sw 0 sw V2 0 sw V1 V2 V1

The equivalent large - signal junction capacitance Ceq(sw) for a sidewall of length (perimeter) P can be Ceq(sw) = P C jsw K eq(sw)
44

Example 8 (1)

45

Example 8 (2)

46