DECLARATION

I hereby declare that this project report on Design and Implementation of VLSI Architecture for Piecewise Lifting Scheme DWT submitted in the department of Electronics and Communication Engineering (ECE), XXXXX Institute of Engineering and Technology, Hyderabad, in partial fulfillment of the requirement for the award of the degree of Master of Technology in XXXXX is a bonafide record of my own work carried out under the supervision of Mr.XXXX, Assistant Professor, XXXXX. Also, I declare that the matter embodied in this project work has not been submitted for the award of any degree/diploma of any other institution or university previously.

Station: Hyderabad, Date:

(Signature of the candidate) XXXXX

ACKNOWLEDGEMENT First and foremost I would like to express my immense gratitude towards my institution XXXX Institute of Engineering & Technology,

which helped me to attain profound technical skills in the field of VLSI System Design, thereby fulfilling my most cherished goal. I would like to thank my project guide Mr. XXX, Assistant professor, E.C.E Department of XXXX for his inspiration, adroit guidance and constructive criticism for successful completion of my degree. I convey my sincere thanks to Dr.XXXX Head of Electronics &Communication Department of VNRVJIET for his encouragement and cooperation. I am thankful to the principal Dr. XXXXX, XXXX, Hyderabad for giving me permission to carry out this project. I express my heartfelt gratitude towards Mr. XXXXX Associate Professor and Project coordinator, for their valuable guidance,

encouragement, inspiration. I would also like to thank all staff members and my co-students who were always there at the need of the hour and provided with all the help and facilities, which I required for the completion of my thesis. ii

XXXXXXX

ABSTRACT The discrete wavelet transform (DWT) plays a central role in a number of signal and image processing applications. Owing to its importance in real-time signal processing systems, its first hardware implementation has been proposed. Subsequently, significant research effort has been made to optimize DWT/IDWT implementation, like architectures based on the folded digit-serial approach and lowcomplexity architectures with a reduced number of multipliers. However, these hardware architectures do not adequately address the power and area consumption issues, which often are the two most important metrics in todays high-performance signal processing systems. The main power consuming operation in DWT/IDWT

computation is filtering, which requires a significant number of multiplications. The lifting scheme is a new algorithm proposed for the implementation of the wavelet transform. It can reduce the

computational complexity of DWT involved with the convolution implementation. Furthermore, the extra memory required to store the

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results of the convolution can also be reduced by in place computation of the wavelet coefficient with the lifting scheme. The lifting scheme consists of the following three steps associated with the lifting scheme based DWT for the one-dimensional signal Split, Predict and Update step. One of the elegant features of the lifting scheme is that the inverse transform is a mirror of the forward transform. In conventional Lifting Scheme based DWT, complete image is divided into two parts that is even and odd image pixels. One even and one odd image pixel leads to PREDICT and UPDATE steps. In Piecewise Lifting Scheme DWT, image is not divided into even and odd sections, but the complete image is windowed. Windowing technique is applied throughout the complete image so as to have equal number of pixels in each window. Number of windows formed depends on the percentage interpolation required to be calculated. Original image is divided in different windows of equal size. Then for each window lifting scheme procedure is applied. The project aims at implementation of an efficient VLSI Architectures for the design of Piecewise Lifting Scheme Algorithm. The main advantage of implementation using Hardware based wavelet algorithm is its inherent speed over software based methods. This speed is due to Flexibility of reconfigurability and reprogramability of FPGA. iv

This architecture is authorized in Verilog; Behavior simulation is done by using the Modelsim6.0.PAR Simulation can be done by using the synthesis Xilinx ISE 10.1.

INDEX List of contents Declaration Acknowledgement ii Abstract Contents List of Tables List of Figures 1. INTRODUCTION 1.1. Introduction to Wavelet Transforms 1.1.1. Wavelet Transforms 1.1.2. Continuous wavelet transforms 1.1.3. Discrete wavelet transforms 1.1.4. Multi resolution Analysis 1.1.5. Multi resolution filter banks 1.1.6. Applications of DWT 1.2. Introduction to Compression 1.2.1. Embedded zero tree wavelet algorithm 1.2.2. Set Partitioning In Hierarchical Trees Algorithm (SPIHT) v iii v ix x 01 02 02 04 05 07 09 11 13 13 14 i

1.3. Motivation 1.4. Objective 1.5. Thesis Organization 18 2. ALGORITHM DESCRIPTION 2.1. Lifting Scheme 2.2. Inverse Lifting Scheme 2.3. Piecewise Lifting scheme DWT 3. IMPLEMENTATION OF PIECEWISE LIFTING SCHEME DWT/IDWT 3.1. Piecewise Lifting Scheme 3.1.1. Flow chart for Piecewise Lifting Scheme DWT 3.1.2. Windowing 3.1.3. Lifting Scheme 3.2. Inverse Piecewise Lifting Scheme 3.2.1. Inverse Lifting Scheme 4. FPGA DESIGN FLOW 36 4.1. FPGA Design Flow 4.1.1. Design Entry 4.1.2. Functional simulation 4.1.3. Synthesizing and Optimizing 38 4.1.4. Design Implementation 4.1.5. Timing simulation after post PAR 4.1.6. Static Timing Analysis 4.1.7. Configuring the device by BitGen 4.2. Processes and Properties 4.2.1. Processes 42 vi

16 17

19 20 24 24 28 29 30 30 31 33 34

37 37 38

38 40 40 41 41

4.2.2. Properties 4.3. Synthesize Options 4.3.1. Optimization Effort 4.3.2. Power Reduction 4.3.3. Use Synthesis Constraints File 4.3.4. Keep Hierarchy 4.3.5. Global Optimization Goal 4.3.6. Generate RTL Schematic 4.3.7. Read Cores 4.4. Write Timing Constraints 4.4.1. Slices Utilization Ratio 4.4.2. LUT-FF Pairs Utilization Ratio 4.4.3. BRAM Utilization Ratio 4.5. Implementation Options 4.5.1. MAP Properties 4.5.2. Perform Timing-Driven Packing and Placement 46 4.5.3. MAP Effort Level 4.5.4. Extra Effort 4.6. Combinatorial Logic Optimization 4.7. Optimization Strategy 4.8. PAR Properties 4.8.1. Place and Route Effort Level (overall) 4.9. Xilinx Core Generator 4.9.1. Block Memory Generator 4.9.2. Memory Types 4.9.3. Configurable Width and Depth vii

42 42 42 43 43 43 44 45 45 45 45 46 46 46 46

47 48 49 49 50 50 51 51 52 52

4.9.4. Selectable Operating Mode per Port 4.9.5. Selectable Port Aspect Ratios 4.9.6. Optional Byte-Write Enable 4.9.7. Optional Pipeline Stages 4.9.8. Memory Initialization 4.9.9. COE files Generation 4.9.10. Memory editor 55 5. EXPERIMENTAL RESULTS 5.1. Simulation Results 5.2. MATLAB simulation 5.3. Synthesis Results 5.4. RTL Schematic 5.5. XILINX floor planner 5.6. FPGA Editor Routed Design

53 53 53 53 54 54

57 58 62 64 66 68 69

6. CONCLUSION AND FUTUREWORK 6.1. Conclusion 6.2. Future Work REFERENCES

72 73 73 74

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LIST OF TABLES Table No. No. 5.1 Device Utilization Summary of

Piecewise Lifting Scheme DWT 64

Name of the Table

Page

5.2

Device Utilization Summary of

Piecewise Lifting Scheme IDWT 65

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LIST OF FIGURES

Figure No. No 1.1 1.2 1.3 1.4 2.1 2.2 2.3

Figure Name

Page

Wavelet Transform Row - Column computation of Two-dimensional DWT Two-level Multi-resolution wavelet decomposition filter structure Two-level Multi-resolution wavelet reconstruction Forward Lifting Wavelet Transform Inverse lifting wavelet transforms Piecewise Application of Lifting Scheme DWT x

03 09 10 10 22 24 27

3.1 30 3.2 3.3 3.4 3.5 3.6 5.1 5.2 5.3 5.4 5.5 5.6 5.7 62 5.8 67 5.9 5.10 69 5.11 5.12

Flow chart for the Piecewise lifting scheme DWT Architecture for Split Module Architecture for Prediction Module Architecture for Update Module Architecture for Inverse Update Module Architecture for Inverse Predict Module Behavioral simulation results for the Split function Post route simulation results for the Split function Behavioral simulation results for the prediction and update function Post Route Simulation results for the Prediction and update function Behavioral simulation results for the inverse lifting scheme Post Route simulation results for the inverse lifting scheme cell image & its10% reduction using lifting RTL Schematic for Forward Lifting Scheme RTL Schematic for Inverse Lifting Scheme FPGA Floor plan design for the Piecewise Lifting Scheme DWT FPGA Editor Routed Design for Piecewise Lifting Scheme DWT Floor plan diagram showing the placement xi 71 71 67 61 61 60 60 59 58 31 32 33 34 35

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