Pseudo-CMOS: A Novel Design Style for Flexible Electronics

Tsung-Ching Huang , Kenjiro Fukuda , Chun-Ming Lo , Yung-Hui Yeh , Tsuyoshi Sekitani , Takao Someya , Kwang-Ting Cheng Dept. of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara, CA 93106-9560, USA. Email: ettrick@ece.ucsb.edu Quantum-Phase Electronics Center, School of Engineering, The University of Tokyo, Tokyo 113-8656, Japan Flexible Electronics Technology Division, EOL/ITRI, Chutung, Hsinchu 31040, Taiwan-R.O.C. Abstract
Flexible electronics have attracted much attention since they enable promising applications such as lowcost RFID tags and e-paper. Thin-lm transistors (TFTs) are considered as an ideal candidate to implement exible electronics on low-cost substrates. Most TFT technologies, however, have only mono-type either n- or p-type devices and thus modern design technologies for silicon-based electronics cannot be directly applied. In this paper, we propose a novel design style Pseudo-CMOS for exible electronics that uses only mono-type TFTs while achieving comparable performance with the complementary-type designs. The manufacturing cost and complexity can therefore be signicantly reduced while the circuit yield and reliability are also enhanced with the built-in capability of post-fabrication tuning. Some standard cells have been designed and fabricated in p-type organic and n-type InGaZnO (IGZO) TFT technologies which successfully verify the superiority of the proposed Pseudo-CMOS design style. To the best of our knowledge, this is the rst design solution that has proven superior performance for both types of TFT technologies.

Figure 1. Comparison of TFT technologies.

1. Introduction
Flexible electronics are emerging as an alternative to silicon electronics for applications such as lowcost RFID tags, sensors, e-paper, and exible displays [1], [2], [3], [4]. TFTs are considered as an ideal candidate to implement exible electronics, because of its compatibility with the low-temperature and lowcost processes on exible substrates. Most TFT technologies summarized in Figure 1, however, have only mono-type either n- or p-type devices, due to their material properties. Complementary TFT circuits

Figure 2. Pseudo-CMOS circuits based on (a) 2V SAM OTFTs on a silicon wafer, and (b) transparent IGZO TFTs on a plastic substrate.

implemented with either homogeneous [5], [6] or heterogeneous TFT technologies [7] usually need to incorporate signicantly slower and less reliable TFTs (e.g. n-type organic TFTs) or complex process integrations (e.g. organic and inorganic TFTs hybridization). This inevitably degrades the circuit performance, yield, and manufacturability. Furthermore, TFTs manufactured using low-cost printing methods, such as ink-jet print-

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ing and roll-to-roll imprinting, often suffer from large process variations and degradations, which result in signicant performance deviations and poor long-term reliability. A robust design solution to overcome these limitations and to be used as fundamental building blocks is therefore highly desirable. Conventional mono-type digital designs such as diodeload or resistive-load inverter designs often suffer from high static power consumption and poor noise margin due to their ratioed-logic nature. Several designs based on mono-type TFTs have been proposed to resolve this problem but can only be used under certain TFT technologies [1], [8]. A comprehensive design solution is still missing. In this paper, we propose a novel design style, called Pseudo-CMOS, that has the following key features: 1) using only mono-type TFTs, 2) including gate-level built-in post-fabrication tunability to compensate for process variations and device degradations, 3) applicability to either enhanced or depletion-mode TFTs, and 4) operability under a low supply voltage (as low as 2V). Three different sets of circuit samples have been designed, fabricated, and measured to evaluate and validate the proposed solution. These samples use: 1) p-type self-assembled-monolayer (SAM) OTFTs on a silicon wafer, 2) n-type transparent IGZO TFTs on a plastic substrate, and 3) IGZO TFTs on a glass substrate. Figure 2(a) shows fabricated Pseudo-CMOS circuits based on 2V SAM OTFTs and Figure 2(b) shows Pseudo-CMOS circuits based on IGZO TFTs on a polyimide plastic substrate. The organization for the rest of the paper is followed. Section 2 will illustrate the device characteristics and structures of SAM-organic and IGZO TFT technologies. Section 3 describes the Pseudo-CMOS design style and measurement results based on p-type SAM OTFTs, including a comparison with other existing designs . More details of circuit analysis can be found elsewhere in [1], [9]. Measurement results of PseudoCMOS circuits based on n-type IGZO TFTs on both glass and polyimide plastic substrates will also be shown and analyzed. Section 5 concludes the paper with our future research.

Figure 3. 2V SAM OTFTs (a) device structure, and (b) device photo (W=500 m, L=50 m).

Figure 4. Drain-source current (IDS ) versus (a) the gate voltage (VGS ) and (b) the Drain-source voltage (VDS ) (W=500 m, L=50 m). acid) to provide a high gate capacitance while keeping a low gate leakage current. The semiconductor layer Pentacene is deposited using the thermal evaporation for higher carrier mobility ( 0.5cm2 V s). Thanks to the high gate capacitance of SAM-dielectric ( 600F cm2 ), the SAM OTFTs can be operated with a gate voltage (VGS ) at only 2V, which enables the use of the same supply voltage of CMOS LSIs for SAM OTFTs [10]. Figure 3(b) also shows the device layout with multiple source/drain (S/D) ngers that can increase the conduction current (IDS ) without a large area overhead. The IDS -VGS plot in the log scale is shown in Figure 4(a) and the IDS -VDS plot in the linear scale is shown in Figure 4(b), where the device width W is 500 m and the device length L is 50 m. From these plots we can obsereve that the threshold voltage (VT H ) for this state-of-art OTFT technology is around 0.5V and the on/off current ratio is around 105 .

2. Background TFT Technologies

2.2. Transparent IGZO TFTs 2.1. 2V SAM OTFTs
Figures 3(a) and (b) show the device structure and photo of a 2V SAM OTFT [10]. is shown in Figure 3(b). The gate dielectric is accomplished by rst exposing the gate terminal Al to O2 plasma ashing to grow AlOx ( 6-nm) and the entire sample is then treated with the SAM solution (n-octadecylphosphonic IGZO TFTs are emerging as a promising technology candidate for display and sensor appliations since 86% of visible lights can penetrate IGZO TFTs that makes the device transparent to human eyes. Figure 5(a) shows the device structure of a transparent IGZO TFT and Figure 5(b) shows a circuit sample on a plastic polyimide substrate that is attached to a 6-inch glass

Table 1. Comparison of inverter characteristics. Inverter Types VDD (V) SNM (V) Mobility (cm2 V s) AirStable? Tunable? Pseudo -D 2 0.91 0.5 (P) Y Y

Figure 5. (a) The sideview of an IGZO TFT, and (b) a circuit sample on a plastic polyimide substrate. (Glass wafer is used as the base for ease of circuit fabrications.)

[5] 3 0.53 0.6/0.02 (P/N) N N

[6] 20 0.67 0.03/0.05 (P/N) Y N

[1] 30 0.14 0.01 (P) Y N

Figure 6. IDS VGS relationship in the log scale for IGZO TFTs on (a) a glass substrate (VT H 25V), and (b) a polyimide plastic substrate (VT H 0.1V). wafer, which is used to ease circuit fabrication. Two different substrates (glass and polyimide plastics) are used to fabricate our test circuits for the validation purpose. Figure 6(a) shows the IDS VGS plot for IGZO TFTs on a glass substrate in which six different curves correspond to six different dies from the same sample. The results reveal the excellent device uniformity on a glass substrate. The threshold voltage VT H is around 25V and the on/off current ratio is around 104 for the glass sample. To further study the IGZO TFT characteristics on plastics, we have fabricated a circuit sample on a polyimide substrate and the IDS VGS plot is shown in Figure 6(b). Comparing this plot with Figure 6(a), we can see that the IGZO TFTs on a plastic substrates can still have a high carrier mobility ( 3cm2 V s) and a high conduction current (IDSAT 106 A), but the gate leakage current rises signicantly (from 1012 1010 A) and the threshold voltage VT H is reduced signicantly (from 25V 0.1V). The resultant circuit performance will be illustrated in Section 4.

Figure 7. Two versions of Pseudo-CMOS inverter designs. The differences between the Pseudo-E and Pseudo-D inverters are the gate connection 1 of M2 and the sizing ratio W . W2

3. Pseudo-CMOS in SAM-OTFTs
3.1. Pseudo-CMOS Inverters
To address the design challenges of using only mono-type TFTs, we proposed a novel design style

called Pseudo-CMOS. More details of circuit analysis and simulations can be found elsewhere in [1], [9]. Figure 7 shows the schematics of Pseudo-CMOS inverters. There are two versions of Pseudo-CMOS inverters: Pseudo-E and Pseudo-D inverters. The differences between the Pseudo-E and Pseudo-D inverters are the gate connection of M2 and the sizing ratio W1 . For the Pseudo-E inverter, M1 and MU P work W2 simultaneously to pull the output to high when the input is low. In the meantime, VIM is pulled to high so the MDP is switched off to prevent a direct current from VDD to Ground in the MU P and MDP pair. On the other hand, the Pseudo-D inverter works in the same manner as the Pseudo-E inverter while M2 (VGS =0V) in the Pseudo-D inverter provides a much RM 4 > 104 in Fig. 7 ) pull-down force weaker ( R M2 to discharge VIM to VSS when the input is high . This subtle difference will actually make a signicant difference on the circuit performance. Furthermore, by adjusting VSS voltages, VIM can also be adjusted to control the pull-down force with M2 , which can be useful to enhace the circuit yield and reliability. Key characteristics of these mono-type and other complementary-type inverters [5], [6] are summarized in Table 1. Note that the static noise margin (SNM)

Figure 8. The inverter VTCs of proposed PseudoE and Pseudo-D inverters. Different curves correspond to VTCs under different VSS. The maximal achievable inverter gain is tunable and can be >20 for Pseudo-D inverters.

Figure 10. Schematics of Pseudo-E and PseudoD NAND gates based on p-type TFTs

Figure 9. The inverter VTCs under different tuning voltages. (VSS = 0V and -2V)

Figure 11. The transfer function of a two-input Pseudo-D NAND gate with one input xed at VDD (a) When input B is xed at VDD, and (b) when input A is xed at VDD. The nearly identical curves reveal good input symmetry of the NAND gate.

shown here has been normalized to the same supply voltage (i.e. VDD =2V) for comparison purposes and the tuning voltage VSS for the proposed Pseudo-D inverter is set to -2V. Although complementary-type inverters can have less static power consumption [5], [6], their transfer characteristics are highly asymmetric due to the mobility mismatch between the n-type and ptype OTFTs. This inevitably degrades their SNMs. Furthermore, implementing complementary-type inverters requires using either unstable n-type devices [5] or a higher supply voltage to compensate for the low carrier mobility [6] ( VGS ), which makes the inverters less reliable and slower than mono-type solutions which uses only faster and air-stable materials (e.g. Pentacene). In addition, complex material treatments, process integration, as well as the manufacturing cost, also make complementary-type TFTs challenging for larger scale of digital designs [1]. Figure 8 shows the voltage transfer characteristics (VTC) of Pseudo-E and Pseudo-D inverters. Different curves reect different VTCs under different VSS voltages. When VSS is adjusted to -2V, Pseudo-D inverter can achieve a high small-signal gain (> 20) and SNM ( 0.91V) because of its symmetric VTC as shown in Figures 8 and 9, and Table 1. Adjusting VSS also

offers post-fabrication tunability that can compensate process variations or device degradation caused by bias-stress effects [11], [9], [12] to enhance the yield and the circuit reliability.

3.2. Pseudo-CMOS NAND Gates

To further study the potential of Pseudo-CMOS designs for larger scale integration, we designed and

Figure 12. The effects of VSS for a Pseudo-D NAND gate: (a) its transfer curves, and (b) the small-signal gain and its corresponding input voltage. (For the ideal case, the maximum-gain input voltage should be VDD/2.)

Figure 13. Schematics of Pseudo-E and Pseudofor D inverters based on n-type TFTs. ( 1 3 Pseudo-E and 4 for Pseudo-D inverters.)

fabricated 2-input NAND gates based on 2V SAM OTFTs, which is the most basic building block for digital design. The schematics of Pseudo-E and Pseudo-D NAND gates are shown in Figure 10. To evaluate the performance of a NAND gate, we x one input of the NAND gate to be VDD and vary the other input to obtain a tranfer curve similar to the inverter VTC. The resulting VTCs are shown in Figure 11. Figures 11(a) and (b) show the transfer curve of a PseudoD NAND gate when keeping input B and input A high, respectively. These two graphs indicate that this Pseudo-D NAND gate has a good input symmetry. The post-fabrication tunability of this NAND gate is illustrated in Figure 12 . By adjusting the tuning voltage VSS, the transfer curve, the small-signal gain, and the maximal-gain input voltage are tunable. This feature enables compensation for process variations and aging as well for enhancement of circuit performance. These results demonstrate that the PseudoCMOS NAND gates based on p-type TFTs, such as the SAM OTFTs, are sufciently robust as a fundamental building block for larger scale digital design.

Figure 14. Inverter VTCs of (a) Diode-load (sizing ratio = 1 ), (b) Phillips RFID [1] (sizing ratio 3 =4), (c) Pseudo-E (VSS =45V) and (d) PseudoD (VSS =45V). All inverters are based on n-type IGZO TFTs on the glass substrate. (VDD =40V)

extraordinary large sizing ratio ( > 5), the smallsignal inverter gain of the conventional Diode-Load and Phillips-RFID [1] designs is smaller than one, which fails to meet the minimum requirement of a workable inverter. On ther other hand, fabricated on the identical substrate with the same technology, both Pseudo-E ( Figure 14(c)) and Pseudo-D (Figure 14(d)) inverters achieve an inverter gain greater than 2, which make these inverters sufciently robust. It should be noted that an even greater performance can be achieved by tuning the VSS voltage.

4.2. Pseudo-CMOS inverter on Plastics

4. Pseudo-CMOS in IGZO TFTs

4.1. Pseudo-CMOS Inverters on Glass
To further verify the effectiveness of Pseudo-CMOS designs in n-type TFTs, we designed and fabricated digital cells based on IGZO TFTs on both glass and plastic substrates. Figure 13 shows the schematics of n-TFT-based Pseudo-E and Pseudo-D inverters. To compare different inverter designs, we designed, fabricated, and measured several inverters and the measurement results are shown in Figure 14. Based on Figures 14(a) and (b), it is clear that without using The Pseudo-E and Pseudo-D inverters are also fabricated on a polyimide plastic substrate with identical design parameters as those on the glass substrate. Figure 15 shows the inverter VTC of a Pseudo-E inverter on a plastic substrate. The small-signal inverter gain ( 6) of this inverter is even greater than that on a glass substrate ( 2.5) and is therefore also sufciently robust to be used as fundamental building blocks for larger scale of digital design based on IGZO TFTs.

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Figure 15. The inverter VTC of a Pseudo-E inverter on a polyimide plastic substrate. Smallsignal gain is around 6.

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5. Conclusion
In this paper, we compare TFT technologies and illustrate the design challenges of TFT circuits. We also designed, fabricated, and measured some standard logic cells in Pseudo-CMOS design style based on three different TFT technologies: 1) p-type SAM OTFTs on silicon, 2) n-type IGZO TFTs on glass, and 3) IGZO TFTs on polyimide plastics. The measurement results of logic cells based on 2V SAM OTFTs show that Pseudo-CMOS inverters and NAND gates can achieve performance comparable to their complementary-type counterparts, while with a lower manufacturing cost and greater reliability. In addition, the built-in post-fabrication tunability can compensate for the process variations and device degradation, as well as enhance the circuit performance. The measurement results of cells based on ntype IGZO TFTs also show the superiority of PseudoCMOS designs in comparison with prior art. To the best of our knowledge, this is the rst comprehensive design solution that can be used for larger scale of circuits in exible electronics. Our future works include the developement of an analog-to-digital converter (ADC) that is based on Pseudo-CMOS cells and the circuits applications will be in exible sensors and displays.

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