1

k v m phng b m BCD c chc nng la chn m tin hoc m li

v hin th kt qu m trn LED 7 thanh.
1 Thit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D1_C1 is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR (7 downto 0));
end D1_C1;
architecture D1_C1 of D1_C1 is
signal temp:STD_LOGIC_VECTOR (3 downto 0);
begin
process(clk,rst)
begin
if(rst='1') then
temp<="0000";
elsif(rising_edge(clk)) then
if(sel='1') then
if temp="1001" then
temp<="0000";
else temp<=temp+1;
end if;
else
if temp="0000" then
temp<="1001";
else temp<=temp-1;
end if;
end if;
end if;
end process;
process(clk,temp)
begin
case temp is
when "0000" => seg<= x"C0";
when "0001" => seg<= x"F9";
when "0010" => seg<= x"A4";
when "0011" => seg<= x"B0";
when "0100" => seg<= x"99";
when "0101" => seg<= x"92";
when "0110" => seg<= x"82";

when "0111" => seg<= x"F8";

when "1000" => seg<= x"80";
when "1001" => seg<= x"90";
when others =>NULL;
end case;
end process;
end D1_C1;
-- rst =100khz, sel=0.5Mhz, clk=20Mhz.
2 Vit chng trnh iu khin 2 led : LED0 v LED7 sng nhp nhy theo chu k

1s.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D1_C2 is
port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
q0 : out STD_LOGIC;
q1 : out STD_LOGIC
);
end D1_C2;
--}} End of automatically maintained section
architecture D1_C2 of D1_C2 is
signal j : integer:=1;
begin
process(clk,rst)
begin
if rst ='0' then j<=0;
else
if rising_edge(clk) then
if j=3 then j<=0;
else
j<=j+1;
end if;
end if;
end if;
end process;
process(rst,j)
begin
if rst ='0' then q0<='0';q1<='0';
else
if j=1 then q0<='1';q1<='1'; end if;
if j=3 then q0<='0';q1<='0'; end if ;

end if;
end process;
end led;
-- clk =2hz
3 Thit k v m phng b m BCD v hin th kt qu m trn LED 7 thanh theo phng
php my trng thi.
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D2_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR(7 downto 0)
);
end D2_C1;
architecture D2_C1 of D2_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 => s <=s1;
when s1 => s <=s2;
when s2 => s <=s3;
when s3 => s <=s4;
when s4 => s <=s5;
when s5 => s <=s6;
when s6 => s <=s7;
when s7 => s <=s8;
when s8 => s <=s9;
when s9 => s <=s0;
end case;
end if;
end if;
end process;
output_state:process(s)
begin

case s is
when s0=> Q<="00000000";
when s1=> Q<="00000001";
when s2=> Q<="00000010";
when s3=> Q<="00000011";
when s4=> Q<="00000100";
when s5=> Q<="00000101";
when s6=> Q<="00000110";
when s7=> Q<="00000111";
when s8=> Q<="00001001";
when s9=> Q<="00001010";
end case;
end process;
end D2_C1;
-- rst = 0.5Mhz, clk=10Mhz
4 Vit chng trnh m tin theo m nh phn K = 128, u ra hin th trn 8 LED n
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity D2_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D2_C2;
--}} End of automatically maintained section
architecture D2_C2 of D2_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 127;
begin
if (rst='1') then dem:=0;
else
if (rising_edge(clk)) then
if(dem=127) then dem:=0;
else dem:=dem+1;
end if;
end if;
end if;
seg<=conv_std_logic_vector(dem,8);

end process;
end D2_C2;
-- rst=0 or 78Khz; clk=25Mhz;
5 Thit k v m phng b m 9 c chc nng la chn m tin hoc m li v hin th kt
qu m trn LED 7 thanh.
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D3_C1 is
port(
rst : in STD_LOGIC;
sel : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D3_C1;
architecture D3_C1 of D3_C1 is
begin
process(rst,clk,sel)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (sel='1') then
if (dem=9) then dem:=0;
else dem:=dem+1;
end if;
elsif (sel='0') then
if(dem=0) then dem:=9;
else dem:=dem-1;
end if;
end if;
end if;
case dem is
when 0 => seg<= x"C0";
when 1 => seg<= x"F9";
when 2 => seg<= x"A4";
when 3 => seg<= x"B0";
when 4 => seg<= x"99";
when 5 => seg<= x"92";
when 6 => seg<= x"82";
when 7 => seg<= x"F8";

when 8 => seg<= x"80";

when others => seg<= x"90";
end case;
end process;
end D3_C1;
-- rst=500Khz; sel=1Mhz; clk=20Mhz;
6 Vit chng trnh iu khin 8 led n sng ln lt theo quy lut: LED0 sng LED1 sng
.- LED7 sng.
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D3_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D3_C2;
architecture D3_C2 of D3_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (dem=8) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="00000001";
when 2=> seg <="00000010";
when 3=> seg <="00000100";
when 4=> seg <="00001000";
when 5=> seg <="00010000";
when 6=> seg <="00100000";
when 7=> seg <="01000000";
when others=> seg <="10000000";
end case;
end process;
end D3_C2;
-- rst=500Khz; clk=10Mhz;

7 Thit k v m phng b m 9 v hin th kt qu m trn LED 7 thanh theo phng php

my trng thi.
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D4_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D4_C1;
architecture D4_C1 of D4_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 => s <=s1;
when s1 => s <=s2;
when s2 => s <=s3;
when s3 => s <=s4;
when s4 => s <=s5;
when s5 => s <=s6;
when s6 => s <=s7;
when s7 => s <=s8;
when s8 => s <=s9;
when s9 => s <=s0;
end case;
end if;
end if;
end process;
output_state:process(s)
begin
case s is
when s0 => seg<= x"C0";
when s1 => seg<= x"F9";
when s2 => seg<= x"A4";
when s3 => seg<= x"B0";

when s4 => seg<= x"99";

when s5 => seg<= x"92";
when s6 => seg<= x"82";
when s7 => seg<= x"F8";
when s8 => seg<= x"80";
when s9 => seg<= x"90";
end case;
end process;
end D4_C1;
-- rst=0.5Mhz; clk=20Mhz;
8 Vit chng trnh iu khin 8 led n sng lan theo quy lut LED0 sng, LED1 v LED0
sng, LED2, LED1 v LED0 sng,, 7 LED cng sng
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D4_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D4_C2;
architecture D4_C2 of D4_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 8;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (dem=8) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="00000001";
when 2=> seg <="00000011";
when 3=> seg <="00000111";
when 4=> seg <="00001111";
when 5=> seg <="00011111";
when 6=> seg <="00111111";
when 7=> seg <="01111111";
when others=> seg <="11111111";

end case;
end process;
end D4_C2;
--rst=0.5Mhz; clk=20Mhz;
9 Thit k v m phng thanh ghi dch vi s bit c th thay i c v c th la chn c
chc nng thc hin: vo ni tip ra ni tip hoc vo ni tip ra song song.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D5_C1 is
generic (n:integer:=8);
port(
clk : in STD_LOGIC;
sel : in STD_LOGIC;
SI : in bit;
Q : out bit_VECTOR(n-1 downto 0)
);
end D5_C1;
--}} End of automatically maintained section
architecture D5_C1 of D5_C1 is
signal temp:bit_vector(n-1 downto 0);
begin
process (clk,SI)
begin
if (clk'event and clk='1') then
temp <= temp(n-2 downto 0)& SI;
end if;
end process;
process(sel,clk)
begin
if (rising_edge(clk))then
if (sel='1') then Q(0)<=temp(n-1);
else
if (sel='0') then Q<=temp;
end if;
end if;
end if;
end process;
end D5_C1;

10

10 Vit chng trnh iu khin 8 led n trn Nanoboad sng theo quy lut: LED0,1,2,3 sng
mu xanh, LED 4,5,6,7 tt LED0,1,2,3 tt, LED 4,5,6,7 sng mu
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D5_C2 is
port(
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D5_C2;
architecture D5_C2 of D5_C2 is
begin
process(clk)
begin
if(clk='1') then seg<="00001111";
else seg<="11110000";
end if;
end process;
end D5_C2;
11 Thit k v m phng b m t 0 ti 99 c chc nng la chn m tin hoc m li v
hin th kt qu m trn LED 7 thanh.
----------------------------------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity D6_C1 is
port(
rst : in STD_LOGIC;
sel : in STD_LOGIC;
clk : in STD_LOGIC;
seg1 : out STD_LOGIC_VECTOR(7 downto 0);--hang don vi
seg2 : out STD_LOGIC_VECTOR(7 downto 0)--hang chuc
);
end D6_C1;
architecture D6_C1 of D6_C1 is
begin
process(rst,clk,sel)
variable temp1:integer range 0 to 10;
variable temp2:integer range 0 to 10;

11

begin
if (rst='1') then
temp1:=0;
temp2:=0;
elsif (rising_edge(clk)) then
if (sel='1') then
if (temp1=10) then
temp1:=0;
temp2:=temp2+1;
if (temp2=10) then temp2:=0;
end if;
else temp1:=temp1+1;
end if;
elsif (sel='0') then
if(temp1=0) then
temp1:=9;
temp2:=temp2-1;
if (temp2=0) then temp2:=9;
end if;
else temp1:=temp1-1;
end if;
end if;
end if;
case temp1 is
when 0 => seg1<= x"C0";
when 1 => seg1<= x"F9";
when 2 => seg1<= x"A4";
when 3 => seg1<= x"B0";
when 4 => seg1<= x"99";
when 5 => seg1<= x"92";
when 6 => seg1<= x"82";
when 7 => seg1<= x"F8";
when 8 => seg1<= x"80";
when 9 => seg1<= x"90";
when others =>NULL;
end case;
case temp2 is
when 0 => seg2<= x"C0";
when 1 => seg2<= x"F9";
when 2 => seg2<= x"A4";
when 3 => seg2<= x"B0";
when 4 => seg2<= x"99";
when 5 => seg2<= x"92";
when 6 => seg2<= x"82";
when 7 => seg2<= x"F8";

12

when 8 => seg2<= x"80";

when 9 => seg2<= x"90";
when others =>NULL;
end case;
end process;
end D6_C1;
-- rst= 10kHz; sel=50Khz; clk=20Mhz;
12 Vit chng trnh s dng 4 button lm u vo, u ra l LED0, LED1, LED2, LED3 sng
tng ng khi bm button 0,1,2,3
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D6_C2 is
port(
nut : in STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(3 downto 0)
);
end D6_C2;
architecture D6_C2 of D6_C2 is
begin
process(nut)
begin
case nut is
when "0000" =>seg<="0000";
when "0001" =>seg<="0001";
when "0010" =>seg<="0010";
when "0100" =>seg<="0100";
when "1000" =>seg<="1000";
when others =>null;
end case;
end process;
end D6_C2;
-- nut = random 0000=>11111 uniform 100ns; chi dung khi mo phong
13 Thit k b m tin t 0 n, sau t m li t n 0 v hin th trn LED 7 thanh.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D7_C1 is
generic (n:integer :=9);
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg1 : out STD_LOGIC_VECTOR(7 downto 0)

13

);
end D7_C1;
architecture D7_C1 of D7_C1 is
begin
process(rst,clk)
variable temp:integer range 0 to 9;
variable num:integer range 0 to 1:=0;
begin
if (rst='1') then
temp:=0;
elsif (rising_edge(clk)) then
if (num = 0) then
if (temp=n) then
num:=1;
else temp:=temp+1;
end if;
end if;
if (num = 1) then
if (temp=0) then
num:=0;
else temp:=temp-1;
end if;
end if;
end if;
case temp is
when 0 => seg1<= x"C0";
when 1 => seg1<= x"F9";
when 2 => seg1<= x"A4";
when 3 => seg1<= x"B0";
when 4 => seg1<= x"99";
when 5 => seg1<= x"92";
when 6 => seg1<= x"82";
when 7 => seg1<= x"F8";
when 8 => seg1<= x"80";
when 9 => seg1<= x"90";
when others =>NULL;
end case;
end process;
end D7_C1;
--rst=500Khz; clk=20Mhz;

14

14 Vit chng trnh m t mch DEMUX 1-8 s dng sw0 sw2 lm u vo iu khin, Led0
Led7 l 8 u ra.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D7_C2 is
port(
SI : in bit;
sel : in bit_VECTOR(2 downto 0);
SO : out bit_vector (7 downto 0)
);
end D7_C2;
architecture D7_C2 of D7_C2 is
begin
SO <= (SI & "0000000") when (sel="000") else
('0' & SI & "000000") when (sel="001") else
("00" & SI & "00000") when (sel="010") else
("000" & SI & "0000") when (sel="011") else
("0000" & SI & "000") when (sel="100") else
("00000" & SI & "00") when (sel="101") else
("000000" & SI & '0') when (sel="110") else
("0000000" & SI) ;
end D7_C2;
-- SI=random 1 ns; sel=random 3 ns;
15 Thit k b m 10 thi gian thc s dng b to dao ng tn s 10 MHz v hin th kt qu
m trn LED 7 thanh.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D8_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D8_C1;
architecture D8_C1 of D8_C1 is
begin
process(rst,clk)
variable dem:integer range 0 to 9;
begin

15

if (rst='1') then dem:=0;

elsif (rising_edge(clk)) then
if (dem=9) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0 => seg<= x"C0";
when 1 => seg<= x"F9";
when 2 => seg<= x"A4";
when 3 => seg<= x"B0";
when 4 => seg<= x"99";
when 5 => seg<= x"92";
when 6 => seg<= x"82";
when 7 => seg<= x"F8";
when 8 => seg<= x"80";
when 9 => seg<= x"90";
when others =>NULL;
end case;
end process;
end D8_C1;
-- rst= 100Khz; clk=10Mhz;
16 Vit chng trnh m li theo m nh phn K = 128, u ra hin th trn 8 LED n.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
entity D8_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D8_C2;
architecture D8_C2 of D8_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 127;
begin
if (rst='1') then dem:=0;
else
if (rising_edge(clk)) then
if(dem=0) then dem:=127;
else dem:=dem-1;

16

end if;
end if;
end if;
seg<=conv_std_logic_vector(dem,8);
end process;
end D8_C2;
-- rst=0 or 78Khz; clk=25Mhz;

17 Thit k b ALU 8 bit 4 bit chn php tnh.

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use IEEE.numeric_std.all;
entity D9_C1 is
port(
rst : in STD_LOGIC;
cin : in STD_LOGIC;
a : in STD_LOGIC_VECTOR(7 downto 0);
b : in STD_LOGIC_VECTOR(7 downto 0);
sel : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(7 downto 0)
);
end D9_C1;
architecture D9_C1 of D9_C1 is
begin
process(sel)
variable temp:std_logic_vector (7 downto 0);
begin
case sel is
when "0000" => temp:=a;
when "0001" => temp:=a+1;
when "0010" => temp:=a-1;
when "0011" => temp:=b;
when "0100" => temp:=b+1;
when "0101" => temp:=b-1;
when "0110" => temp:=a+b;
when "0111" => temp:=a + b + cin;
when "1000" => temp:=NOT a;
when "1001" => temp:=NOT b;
when "1010" => temp:=a AND b;

17

when "1011"
when "1100"
when "1101"
when "1110"
when others

=> temp:=a OR b;
=> temp:=a NAND b;
=> temp:=a NOR b;
=> temp:=a XOR b;
=> temp:=a XNOR b ;

end case;
y <=temp;
end process;
end D9_C1;
-- rst=10khz; cin=5Mhz; a,b= counter 0=>1111111 50ns; sel= random 100ns;
18 Vit chng trnh m thp phn v hin th kt qu trn LED n.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D9_C2 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(9 downto 0)
);
end D9_C2;
architecture D9_C2 of D9_C2 is
begin
process(rst,clk)
variable dem:integer range 0 to 9;
begin
if (rst='1') then dem:=0;
elsif (rising_edge(clk)) then
if (dem=8) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0 => seg<= "0000000001";
when 1 => seg<= "0000000010";
when 2 => seg<= "0000000100";
when 3 => seg<= "0000001000";
when 4 => seg<= "0000010000";
when 5 => seg<= "0000100000";
when 6 => seg<= "0001000000";
when 7 => seg<= "0010000000";
when 8 => seg<= "0100000000";
when 9 => seg<= "1000000000";
when others =>NULL;

18

end case;
end process;
end D9_C2;
-- rst= 100Khz; clk=10Mhz;
19 Thit k mch pht hin chui nh sau: u vo ca mch l mt lung bit ni tip, u ra ca
n l 1 khi xut hin chui bit 111 v u ra l 0 trong cc trng hp cn li.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D10_C1 is
port(
rst : in STD_LOGIC;
d : in BIT;
clk : in STD_LOGIC;
y : out STD_LOGIC
);
end D10_C1;
architecture D10_C1 of D10_C1 is
type state is (s0,s1,s2,s3);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 =>
if d='0' then s <=s0; else s<=s1;
end if;
when s1 =>
if d='0' then s <=s2; else s<=s3;
end if;
when s2 =>
if d='0' then s <=s0; else s<=s1;
end if;
when s3 =>
if d='0' then s <=s2; else s<=s3;
end if;
end case;
end if;
end if;
end process;

19

output:process(s,clk)
begin
if (rising_edge(clk)) then
if ((s=s3) and (d='1')) then
y<='1';
else y<='0';
end if;
end if;
end process;
end D10_C1;
--rst=500khz; d= random 100ns; clk=

5Mhz;

20 Vit chng trnh iu khin LED0 sng nhp nhy theo chu k 1s.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D10_C2 is
port(
clk : in STD_LOGIC;
y : out STD_LOGIC
);
end D10_C2;
architecture D10_C2 of D10_C2 is
begin
process(clk)
begin
if(clk='1') then y<='1';
else y<='0';
end if;
end process;
end D10_C2;
--clk=0.5hz
21 Thit k mch pht hin chui nh sau: u vo ca mch l mt lung bit ni tip, u ra ca
n l 1 khi xut hin chui bit 000 v u ra l 0 trong cc trng hp cn li
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D11_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
y : out STD_LOGIC;
d : in BIT

20

);
end D11_C1;
architecture D11_C1 of D11_C1 is
type state is (s0,s1,s2,s3);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 =>
if d='0' then s <=s1; else s<=s0;
end if;
when s1 =>
if d='0' then s <=s3; else s<=s2;
end if;
when s2 =>
if d='0' then s <=s1; else s<=s0;
end if;
when s3 =>
if d='0' then s <=s3; else s<=s2;
end if;
end case;
end if;
end if;
end process;
output:process(s,clk)
begin
if (rising_edge(clk)) then
if ((s=s3) and (d='0')) then
y<='1';
else y<='0';
end if;
end if;
end process;
end D11_C1;
--rst=100khz; d= random 100ns; clk=5Mhz;
22 Vit chng trnh iu khin LED0 v LED1 cng sng nhp nhy theo chu k 1s.
library IEEE;
use IEEE.STD_LOGIC_1164.all;

21

entity D11_C2 is
port(
clk:in std_logic;
s0,s1 : out STD_LOGIC
);
end D11_C2;
architecture D11_C2 of D11_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s1<='1';
else s0<='0';s1<='0';
end if;
end process;
end D11_C2;
-- clk=0.5hz
23 Thit k b chuyn i song song thnh ni tip.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D12_C1 is
port(
load : in STD_LOGIC;
clk : in STD_LOGIC;
d : in STD_LOGIC_VECTOR(7 downto 0);
dout : out STD_LOGIC
);
end D12_C1;
architecture D12_C1 of D12_C1 is
signal t:std_logic;
signal temp:std_logic_vector(7 downto 0);
begin
process(clk,load,d)
begin
if (load ='1') then temp<=d;
elsif (rising_edge(clk)) then
t<=temp(7);
temp(7 downto 1)<= temp(6 downto 0);
temp(0)<='0';
end if;
end process;

22

dout<=t;
end D12_C1;
--load 500khz;clk=20Mhz;

d counter 0-11111111 binary 125 ns;

24 Vit chng trnh iu khin 2 led : LED0 v LED7 sng nhp nhy theo chu k 1s.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D12_C2 is
port(
clk:in std_logic;
s0,s7 : out STD_LOGIC
);
end D12_C2;
--}} End of automatically maintained section
architecture D12_C2 of D12_C2 is
begin
process(clk)
begin
if(clk='1') then s0<='1';s7<='1';
else s0<='0';s7<='0';
end if;
end process;
end D12_C2;
-- clk=0.5hz
25 Thit k v m phng b m Gray 4 bit v hin th kt qu di dng thp phn trn LED 7
thanh.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY D13_C1 IS
PORT (
rst:in std_logic;
clk:IN STD_logic;
seg:out STD_Logic_vector(7 downto 0));
END D13_C1;
ARCHITECTURE D13_C1 of D13_C1 IS

23

signal temp: std_logic_vector(3 downto 0);

signal gray: std_logic_vector(3 downto 0);
begin
process (clk,rst)
begin
if(rst='1') then
temp<="0000";
gray<="0000";
elsif (rising_edge(clk)) then
if(temp="1001") then temp<="0000";
else temp <= temp+1;
end if;
gray(3)<=temp(3);
for i in 2 downto 0 loop
gray(i)<= temp(i+1) xor temp(i);
end loop;
end if;
end process;
process(gray)
begin
case gray is
when "0000" => seg<= x"C0";
when "0001" => seg<= x"F9";
when "0011" => seg<= x"A4";
when "0010" => seg<= x"B0";
when "0110" => seg<= x"99";
when "0111" => seg<= x"92";
when "0101" => seg<= x"82";
when "0100" => seg<= x"F8";
when "1100" => seg<= x"80";
when "1101" => seg<= x"90";
when others =>NULL;
end case;
end process;
end D13_C1;
--d= counter 100 ns;
26 Vit chng trnh iu khin 8 led sng lan t gia sang hai bn.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D13_C2 is
port(
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)

24

);
end D13_C2;
architecture D13_C2 of D13_C2 is
begin
process(clk)
variable dem:integer range 0 to 4;
begin
if (rising_edge(clk)) then
if (dem=4) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="00011000";
when 2=> seg <="00111100";
when 3=> seg <="01111110";
when 4=> seg <="11111111";
when others=> seg <="XXXXXXXX";
end case;
end process;
end D13_C2;
-- clk=5Mhz;
27 Thit k v m phng b m nh phn 4 bit v hin th kt qu di dng HEX trn LED 7
thanh theo phng php my trng thi.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity D14_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(6 downto 0)
);
end D14_C1;
architecture D14_C1 of D14_C1 is
signal temp:STD_Logic_vector (3 downto 0);
begin
process (clk,rst)
begin
if(rst='1') then
temp<="0000";

25

elsif (rising_edge(clk)) then

if(temp="1111") then temp<="0000";
else temp <= temp+1;
end if;
end if;
end process;
process(temp)
begin
case temp is
WHEN "0000"=>seg<="1111110";
WHEN "0001"=>seg<="0110000";
WHEN "0010"=>seg<="1101101";
WHEN "0011"=>seg<="1111001";
WHEN "0100"=>seg<="0110011";
WHEN "0101"=>seg<="1011011";
WHEN "0110"=>seg<="1011111";
WHEN "0111"=>seg<="1110000";
WHEN "1000"=>seg<="1111111";
WHEN "1001"=>seg<="1111011";
WHEN "1010"=>seg<="1110111";
WHEN "1011"=>seg<="0011111";
WHEN "1100"=>seg<="1001110";
WHEN "1101"=>seg<="0111101";
WHEN "1110"=>seg<="1001111";
WHEN "1111"=>seg<="1000111";
WHEN OTHERS=>seg<="XXXXXXX";
end case;
end process;
end D14_C1;
-- rst=500khz; clk=20Mhz;
28 Vit chng trnh iu khin 8 led sng lan t hai bn vo vo gia.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D14_C2 is
port(
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D14_C2;
architecture D14_C2 of D14_C2 is
begin
process(clk)

26

variable dem:integer range 0 to 4;

begin
if (rising_edge(clk)) then
if (dem=4) then dem:=0;
else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="10000001";
when 2=> seg <="11000011";
when 3=> seg <="11100111";
when 4=> seg <="11111111";
when others=> seg <="XXXXXXXX";
end case;
end process;
end D14_C2;
-- clk=5Mhz;
29 Thit k v m phng b m Gray 4 bit v hin th kt qu di dng thp phn trn LED 7
thanh bng phng php my trng thi.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D15_C1 is
port(
rst : in STD_LOGIC;
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D15_C1;
architecture D15_C1 of D15_C1 is
type state is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal s:state;
begin
next_state:process(rst,clk)
begin
if (rst='1') then s<=s0;
else
if (rising_edge(clk)) then
case s is
when s0 => s <=s1;
when s1 => s <=s2;
when s2 => s <=s3;

27

when s3 => s <=s4;

when s4 => s <=s5;
when s5 => s <=s6;
when s6 => s <=s7;
when s7 => s <=s8;
when s8 => s <=s9;
when s9 => s <=s0;
end case;
end if;
end if;
end process;
output_state:process(s)
begin
case s is
when s0 => seg<= x"C0";
when s1 => seg<= x"F9";
when s2 => seg<= x"A4";
when s3 => seg<= x"B0";
when s4 => seg<= x"99";
when s5 => seg<= x"92";
when s6 => seg<= x"82";
when s7 => seg<= x"F8";
when s8 => seg<= x"80";
when s9 => seg<= x"90";
end case;
end process;
end D15_C1;
-- rst=0.5Mhz; clk=20Mhz;
30 Vit chng trnh iu khin 8 led sng lan t gia sang hai bn.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity D15_C2 is
port(
clk : in STD_LOGIC;
seg : out STD_LOGIC_VECTOR(7 downto 0)
);
end D15_C2;
architecture D15_C2 of D15_C2 is
begin
process(clk)
variable dem:integer range 0 to 4;
begin
if (rising_edge(clk)) then

28

if (dem=4) then dem:=0;

else dem:=dem+1;
end if;
end if;
case dem is
when 0=> seg <="00000000";
when 1=> seg <="00011000";
when 2=> seg <="00111100";
when 3=> seg <="01111110";
when 4=> seg <="11111111";
when others=> seg <="XXXXXXXX";
end case;
end process;
end D15_C2;
-- clk=5Mhz;