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Digital Echo/Surround Processor IC

PT2396

DESCRIPTION
PT2396 is a digital echo/surround processor IC utilizing CMOS Technology. Analog Signal inputted to PT2396 is converted to digital signal by A-D converter and then stored into the internal memory. After a certain delay time, this memory-stored digital signal is converted back into analog signal via the D-A converter. A low cost echo system may be achieved with the PT2396's A-D converter, D-A converter, incorporating ADM (Adaptive Delta Modulation) Algorithm while maintaining lower noise, lower distortion, and higher S/N ratio. PT2396 is functionally compatible with M65831P. If you are replacing M65831P with our PT2396, you must take note that PT2396 does not need to connect an external resistor (30 Ohms) to Pin 15 and Pin 21.

FEATURES
• • • • • • • • • CMOS Technology Low Power Consumption Low Noise (-92 dBV typical) Low Distortion (0.5% typical) Built-in 48 K Memory Automatic Reset Circuit Included A-D, D-A Converters (Adaptive Delta Modulation), 2 LPFs and 48 K-bit Memory Sleep Mode Function Parallel or Serial Data controlled from Micro Controller

APPLICATIONS
• • • • KARAOKE Electronic Musical Instruments VCD, DVD Radio Set

PT2396 V1.3

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September, 2004

3 -2- EA S Y/(/ MC U) DL 2 /C L K 21 OP1OUT 19 18 17 16 15 14 13 SL E EP OS CO TES T L P F2 IN O P1 IN O P2 IN CC 1 CC 2 September.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. 2004 .tw Digital Echo/Surround Processor IC PT2396 BLOCK DIAGRAM L P F1 O UT L P F2 O UT + OP2 L P F2 O P1 OUT O P2 OUT L P F1 IN V CC + L P F1 + CO M P + OP1 MO D DE M + RE F 1 /2 V CC D1 RE S E T CL O C K DE L C DG N D DO 0 DO 1 MO MI 4 8K B IT M E MO RY A G ND A UT O RE S E T V DD O S CI O S CIL L AT OR DE L AY TI ME C ON TR O L DL 1 /R EQ DL 3 /D IN DL 4 /ID S PIN CONFIGURATION VD D OSCI OSCO DL1/R EQ DL2/C LK DL3/D IN DL4/IDS T EST EA SY/(/MCU ) 1 2 3 4 5 6 7 8 9 24 23 22 20 VC C LPF 1IN LPF 1OU T OP1IN RE F CC1 CC2 OP2IN OP2OUT LPF 2IN LPF 2OU T PT23 96 SLEE P 10 DGND 11 AGND 12 PT2396 V1.com.princeton.

This pin connected to the Analog GND. R. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 PT2396 V1. Normal Mode = Low EASY/(/MCU) Pin. This pin connects to 2MHz ceramic resonator. EASY Mode = High MCU Mode = Low Sleep Pin. MCU Mode: This pin inputs request data. Test Pin. Oscillator Output Pin. This pin connects to the Analog GND at one external point. Oscillator Input Pin. C. 2004 . MCU Mode: This pin inputs serial data. Easy Mode: This pin inputs DL2 data. These pins form the OP-AMP2 Output Pin integrator with external OP-AMP2 Input Pin C. Current Control 2 Pin Pin No. This pin connects to 2MHz ceramic resonator or inputs an external clock. R.princeton. Easy Mode: This pin inputs DL3 data.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.com. Easy Mode: This pin inputs DL1 data. Delay1/Request Pin. Low Pass Filter 2 Output Pin. MCU Mode: This pin inputs shift clock.3 -3- September. Sleep Mode = High Normal Mode = Low Digital GND Pin. Easy Mode: This pin inputs DL4 data. Delay 3/Serial Data Pin. Delay2/Shift Clock Pin. These pins form the low pass filter with external Low Pass Filter 2 Input Pin.tw Digital Echo/Surround Processor IC PT2396 PIN DESCRIPTION Pin Name VDD OSCI OSCO DL1/REQ DL2/CLK DL3/DIN DL4/IDS TEST EASY/(/MCU) SLEEP DGND AGND LPF2OUT LPF2IN OP2OUT OP2IN CC2 I/O I O I I I I I I I O I O I Description Digital Supply Voltage. MCU Mode: This pin controls ID Code. Delay 4/ID Switch Pin. Analog GND Pin.

PT2396 Pin No. 18 19 These pins form the integrator with external C. R.com.tw Digital Echo/Surround Processor IC Pin Name CC1 REF OP1IN OP1OUT LPF1OUT LPF1IN VCC I/O I O O I Description Current Control 1 Pin. 2004 . R.princeton.3 -4- September. Low Pass Filter 1 Output Pin Low Pass Filter 1 Input Pin Analog Supply Voltage Pin. Reference Pin.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. OP-AMP 1 Output Pin. 20 21 22 23 24 PT2396 V1. Reference Voltage = 1/2 VCC OP-AMP 1 Input Pin. These pins form the low pass filter with external C.

namely – DL1/REQ.4 73.7 172.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. The following table gives the various Delay Time with reference to the Pins DL1 ~ DL4.3 196.6 36.9 135. DL2/CLK. and DL4/IDS are all used as inputs for Delay Time Data (DL1 ~ DL4).5 159.2 61.0 98.sampling frequency (KHz) Td = Delay Time (msec) DL2 L DL1 L H L H L H L H L H L H L H L H Td (ms) 12. fs DL4 DL3 L H 500 L L H H L L H 250 H L H H Note: fs . 2004 .3 24.2 147.0 184.3 -5- September.tw Digital Echo/Surround Processor IC PT2396 FUNCTIONAL DESCRIPTION DELAY TIME EASY MODE The Easy Mode is activated when the EASY/(/MCU) Pin is in HIGH State.7 86. DL3/DIN.6 PT2396 V1.princeton. The Delay Pins: namely -.6 122. Under the Easy Mode.com.3 110.9 49.DL1~DL4 determine the amount of time the memory-stored signal would be stored in the 48 K-bit memory (delay time).

tw Digital Echo/Surround Processor IC MCU MODE PT2396 The MCU Mode is activated when the EASY/(/MCU) Pin is in Low State.3 -6- September. The delay time is set by the serial data from the MCU. 2004 .princeton. Please refer to below: IDS Pin 0 1 ID1 0 0 ID2 1 1 ID3 0 0 ID4 0 1 PT2396 V1. Pin 7 may be pulled High or Low. When 2 pieces of PT2396 are used. Please refer to the timing diagram below: Pin 4 RE Q Pin 5 CLK Pin 6 DIN S lee p DL 1 DL 2 DL 3 DL 4 M ute ID1 ID2 ID3 ID4 wh er e: D ela y Ti me = D L1 ~ DL 4 ID Cod es = ID1 ~ ID4 The DIN Signal is shifted in the falling edge of the CLK Signal when the ID Code Bits values are verified as follows: ID1 and ID3 = Low ID2 = High ID4 = IDS Pin then.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. Pin 7 determines which PT2396 is in control. the last ten data bits are latched at the rising edge of the REQ Signal.com.

tw Digital Echo/Surround Processor IC SLEEP MODE FUNCTION EASY MODE PT2396 Also under this mode. SYSTEM RESET PT2396 features an auto-rest function. the clock and the RAM stops in order to reduce the circuit current.5 msec if MCU Mode is enabled. 2004 .3 -7- September. At this point. The reset time is approximately 120 msec and the delay time is set at 147.com. the SLEEP Mode may be activated when the SLEEP Pin is in High State. otherwise. When the SLEEP Pin is set to LOW.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. MCU MODE The Sleep Mode is activated when the SLEEP Pin is set to HIGH. PT2396 V1. there is normal operation.princeton. the Normal Mode applies.

Delay Signal Mute Time 525ms Condition 3: Automatic Mute Function Diagram 3 -.3 -8- September.SLEEP Mode is canceled. 2.tw Digital Echo/Surround Processor IC MUTE FUNCTION EASY MODE PT2396 Under the EASY Mode. Condition 1: Automatic Mute Function Diagram 1 -. 2004 .Delay Time Change D e la y S ig n al 1 D e la y S ig n al 2 5 25 m s M u te Tim e Condition 2: Automatic Mute Function Diagram 2 -. the mute function is automatically activated under the following conditions: 1.During Power ON Delay Signal 120msec Mute Time 525ms PT2396 V1.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. 3.princeton.com. Power is turned ON. SLEEP Mode is canceled. Delay Time is changed.

Please refer to the diagrams below.princeton. then an automatic muting function can be used (also see EASY Mode Section). Signal Mute When Bit 6 = "1" PT2396 V1.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. However.tw Digital Echo/Surround Processor IC MCU MODE PT2396 From the DIN signal (DL3 Pin). if this Mute bit (from the DIN Pin) is read High. 2004 . if the Mute bit is read as Low.3 -9- September. then normal muting function can be performed (see figure below).com.

5 -92 -40 525 525 12. Vcc=5V. f=1KHz.2 VDD 0. 16.tw Digital Echo/Surround Processor IC PT2396 ABSOLUTE MAXIMUM RATING (Unless otherwise specified.5 0.7VDD 0 Typ.5 0.3 0. 40.princeton. Operating Current Icc RL=47KΩ Voltage Gain Gv THD=10% 30KHz LPF fs=500 KHz Output Distortion THD Vi=1Vrms fs=250 KHz Output Noise Voltage Supply Voltage Rejection Ratio Mute Time Operating Current (Sleep Mode) VNo SVRR TMUTE Iccs DIN=0V Vcc=5V.0 -0.5 100 1 -40 ~ +85 -65 ~ +150 Unit V mA W ℃ ℃ RECOMMENDED OPERATING CONDITIONS Parameter Supply Voltage Clock Frequency High Input Voltage Low Input Voltage Symbol Vcc Fck VIH VIL Min. 4.0 Unit mA dB % dBV dB ms mA PT2396 V1.2 1. f=100Hz Upon Changing Delay Time Upon canceling Sleep Mode Sleep Mode Typ. Ta=25℃) Parameter Symbol Test Conditions Min.5 -75 -25 30. 5. Ta=25℃) Parameter Supply Voltage Operating Current Power Dissipation Operating Temperature Storage Temperature Symbol Vcc Icc Pd Topr Tstg Ratings 5.com.3 .Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. Vp-p=100mV. 5 2 Max.0 Max.10 - September.3VDD Unit V MHz V V ELECTRICAL CHARACTERISTICS (Unless otherwise specified.0 1. 2004 . Vi=100mVrms.

com. Every Digital GND must be connected to the Analog GND at one Point 2.1u Note: 1. PT2396 V1. please take note that PT2396 does not need to connect an external resistor (30 Ohms) to Pin 15 and Pin 21.tw Digital Echo/Surround Processor IC PT2396 APPLICATION CIRCUITS EASY MODE IN + + OUT + 14 CC1 LPF1IN OP1IN OP2IN LPF1OUT OP1OUT LPF2IN DGND VCC REF CC2 OP2OUT 13 LPF2OUT AGND 1 100u 2 1M 2MHz 100P 100P SETTING DELAY TIME SLEEP SW SLEEP OSCO TEST OSCI VDD Dl2 Dl4 Dl3 Dl1 +5V DGND AGND + 0.3 . 2004 .princeton.11 - September.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. When replacing M65831 with PT2396.

com. please refer below: IDS Pin 0 1 ID1 0 0 ID2 1 1 ID3 0 0 ID4 0 1 PT2396 V1.3 .princeton.12 - September.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. Every Digital GND must be connected to the Analog GND at one Point 2. 7).1u Note: 1.tw Digital Echo/Surround Processor IC MCU MODE PT2396 IN + + OUT + 14 LPF1 OUT OP1 OUT OP2 OUT CC1 LPF1 IN OP1 IN OP2 IN LPF2 IN DGND REF CC2 V CC 13 LPF2 OUT AGND OSCO SLEEP TEST DATA OSCI REQ SCK V DD IDS 1 100u 2 1M 2MHz 100P 100P MICROCOMPUTER 5V SLEEP SW +5V DGND AGND + 0. For the DL4/IDs Pin (Pin No. 2004 .

tw Digital Echo/Surround Processor IC SURROUND APPLICATION CIRCUIT PT2396 IN + + OUT + 14 CC1 OP2 IN LPF1 IN LPF1 OUT LPF2 IN DGND OP1 IN VCC REF CC2 OP1 OUT OP2 OUT 13 LPF2 OUT AGND 1 100u 2 1M 2MHz 100P 100P 5V SLEEP SW +5V DGND AGND + 0. 7).com.1u MICROCOMPUTER Note: 1.13 - SLEEP OSCO TEST DATA OSCI REQ VDD SCK IDS September. 2004 .3 . Every Digital GND must be connected to the Analog GND at one Point For the DL4/IDs Pin (Pin No.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. please refer below: IDS Pin 0 1 ID1 0 0 ID2 1 1 ID3 0 0 ID4 0 1 PT2396 V1.princeton.

Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. DIP. PT2396 V1. 300mil 24 pins. (L) = Lead Free 2. 300mil Top Code PT2396 PT2396-S PT2396 PT2396-S Notes: 1. SOP. The Lead Free mark is put in front of the date code. 2004 .tw Digital Echo/Surround Processor IC PT2396 ORDER INFORMATION Valid Part Number PT2396 PT2396-S PT2396 (L) PT2396-S (L) Package Type 24 pins. SOP.princeton. DIP. 600mil 24 pins.14 - September.3 .com. 600mil 24 pins.

15 - September.3 . DIP.com.princeton. 2004 . 600 MIL PT2396 V1.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.tw Digital Echo/Surround Processor IC PT2396 PACKAGE INFORMATION 24 PINS.

08 PT2396 Notes: 1. 6.93 Nom.) shall b symmetrical about the lateral and longitudinal package centerlines.com. Dimensions A. mess.32 2. 2004 . “D” & “E1” dimensions.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www. 7. (0. Dimensioning and tolerancing per ANSI Y14. Pointed our rounded leads tips are preferred to ease insertion. 8. 4. 3. A1 and L are measured with the package seated in JEDEC Seating Plane Gauge GS-3. PT2396 V1.24 BASIC Max.24 12.18 0. 12. For automatic insertion.13 15. JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.54 BASIC 15.77 0. N. “D” & “E1” dimensions for plastic package.95 0.39 3.3 0.356 0.381 32. Controlling dimension: MILLIMETER 2. N/2.35 4.78 5. any rained irregularity on the top surface (step. “eC” must be zero or greater. 0. and N/2+1) may be configured as shown in Figure 2. 11.558 1.7 15. (N=24) 9. Refer JEDEC MS-011 Variation AA. 10. for ceramic packages.5M-1982. “eB” and “eC” are measured at the lead tips with the loads un-constrained. Corner leads (1. do not includes mold flash or protrusion. include allowance for glass overrun and meniscus and lid to base mismatch.16 - September.01 inch.77 0. etc. 2. 6.73 17. 5.204 29. Mold flash or protrusions shall not exceed 0. “E” and “eA” measured with the leads constrained to be perpendicular to plane T.25mm).87 14. “N” is the maximum quantity of lead positions.tw Digital Echo/Surround Processor IC Symbol A A1 A2 B B1 C D D1 E E1 e eA eB L Min.3 .princeton.

com.35 0.32 15.40 0° .20 7.27 bsc.30 0. Max.23 15.3 Min.60 10. . 2004 1.33 0.27 8° September.40 10.51 0.65 0. SOP.princeton.tw Digital Echo/Surround Processor IC 24 PINS.25 0.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.60 7. 2.00 0.65 0.10 0. 2. 300 MIL PT2396 Symbols A A1 B C D E e H h L α PT2396 V1.17 - Nom.75 1.

protrusions or gate burrs. It is not present. Controlling dimension: MILLIMETER. “L” is the length of the terminal for soldering to a substrate. The lead width “B” as measured 0.61mm (0. (N=24) 7. Refer to JEDEC MS-013. Dimension “E” does not include interlead flash protrusions.18 - September.36 mm (0.24 in). 8.3 . 5.25 mm (0. 6. 9. 4. 2004 . Dimensioning and tolerancing per ANSI Y 14. “N” is the number of terminal position. Interlead flash or protrusions shall not exceed 0. Dimension “D” does not include mold flash.princeton. JEDEC is the trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION.014 in) or greater above the seating plane.010 in) per side. Variation AD. shall not exceed a maximum value of 0.com.tw Digital Echo/Surround Processor IC PT2396 Notes: 1. a visual index feature must be located within the crosshatched area. Mold Flash. protrusion or gate burrs shall not exceed 0.006 in)per side. PT2396 V1.15mm (0. 2.5-1982. 3. The chamfer on the body is optional.Tel: 886-2-66296288 Fax: 886-2-29174598 URL: http://www.