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Specification of the Bluetooth System Part B : 6,7,8,9,11

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Contents
Part B : BASEBAND SPECIFICATION
6. Logical Channels 7. Data Whitening 8. Transmit/Receive Routines 9. Transmit/Receive Timing 11. Hop Selection

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Logical Channels
LC control channel
low level link control information ARQ, flow control, payload characterization packet header

LM control channel
control information using DM packets SCO/ACL link L_CH : 11

US user channel
synchronous user data SCO link

UA user channel
L2CAP asynchronous user data ACL link / SCO DV packet L_CH no fragmentation : 10 fragmentation : 10/01
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UI user channel
supported by timing start packet (at higher level) ACL link / SCO DV packet L_CH(at baseband) same as UA
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Data Whitening(1)
Payload Scrambling (Tx)
header / payload randomizing the data minimizing DC bias scrambling

Payload Descrambling (Rx)

using the same scrambling word

Whitening word generator

g(D)=D7+D4+1

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Data Whitening(2)
LFSR initialization : general form
master clock CLK6-1 / 1
LSB CLK6-1 MSB 1

LFSR initialization exception form: FHS

using X 79-hop system
LSB X4-0 1 MSB 1

23-hop syatem
LSB X3-0 1 1 MSB 0

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Transmit/Receive Routines : Tx Routine

Functional diagram of Tx buffering

ACL/SCO separation Buffer number (Master) ACL : one buffer for each slave SCO : one or more buffers for each slave Buffer composition current register : link controller access next register : link manager access Switch S1,S2 control : link controller ACL buffer * (DV) DM/DH packets, DM1, SCO buffer HV packets, (DV)
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Transmit/Receive Routines : ACL traffic(1)

Packet Types DM : poor link quality DH : good link quality Default pack type NULL Tx routine

NAK : keep switch ACK : change switch S1 3. Check ARQN(response)

LC

3. Transmit packet

LM
2. Build packet

Packet composer

1. Read current register

1. Load new data 2. flush command

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2. Send the payload ? 1. Switch change(S1a S1b)

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Transmit/Receive Routines : ACL traffic(2)

flush command switch the S1 switch to the proper register continue the flow in the Link Controller after default packet or interrupt time-bounded(isochronous) data re-transmitting control

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Transmit/Receive Routines : SCO traffic

Packet Types HV S2 switch changing interval Tsco Tx routine(SCO slot) S2 switching read the current register(packet composer) Data/link control information using DM1, DV packet high priority control information can interrupt current SCO information

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Transmit/Receive Routines : Mixed data/voice traffic

DV packet SCO link support data/voice

Switch changing S1 : depending ARQN S2 : automatically changing Packet type changing : DV to HV no data flush command new data after data interrupt

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Transmit/Receive Routines : Default packet types

ACL link default packet NULL packet NULL packet no user information
NULL packet : ARQN, flow control no packet sending

allocate the next slave-to-master slot POLL packet require a response SCO link default packet SCO packet type negotiated at the LM when SCO link establishment

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Transmit/Receive Routines : Rx Routine

Functional diagram of Rx buffering ACL/SCO separation Buffer number (Master) ACL : single Rx buffer SCO : depending on SCO links Buffer composition current register : link manager access next register : link controller access Switch switching S1 change : link manager has read the old register S2 change : Tsco interval STOP indication(response) Rx register is not empty SEQN field ACL register load indication
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Transmit/Receive Routines : Flow Control

Flow control header field in the return Tx packet STOP/GO Destination control STOP indication Rx ACL buffer is not emptied GO indication default value can receive packets not including data flow control separation for Tx/Rx Source control STOP

1. Switch to the default packet 2. Freeze the Tx ACL buffer 3. Send default packet while STOP

Multi-slave configuration FLOW control affects only to the master-to-STOP issued slave
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Transmit/Receive Routines : Bitstream Process

Packet header bit process

Payload bit process

mandatory process
whitening/de-whitening
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Transmit/Receive Timing
TDD(time-division duplex) Transmission start(normal connection mode) master : CLK1=0 slave : CLK1=1 Timing diagram signals at the antenna

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Transmit/Receive Timing : Master/Slave Timing Synchronization

Piconet synchronization : master clock CLK

Tx
Based on master clock Interval : M1250s (M is a positive integer)

Tx
Based on most recent slave Rx timing Adjust offset time

not adjust Rx/Tx timing Master

Slave

adjust offset by received packet

Rx
Shift from Tx : N625s (N is an odd, positive integer) Using 10s uncertainty window

Rx
Based on latest successful trigger Trigger occurrence : ACL/SCO links Uncertainty window : 10s
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Transmit/Receive Timing : Connection State

Rx/Tx cycle of Bluetooth master(single slot mode)

g(m) : channel hopping frequency Rx timing : using 10s uncertainty window, N625s shift from Tx(N:positive, odd
integer) Tx timing : M1250s shift from Tx(M:positive integer)

Rx/Tx cycle of Bluetooth slave(single slot mode)

Tx timing : N625s shift from Rx(N:positive, odd integer)

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Transmit/Receive Timing : Return From HOLD Mode / Park Mode Wake-Up

Return from HOLD mode listen for the master increase search window : 10s to large Xs

Search window center hops X < 625 : g(2m), g(2m+2), , g(2m+2i) , i is a integer X > 625 : g(2m), g(2m+4), , g(2m+4i), or g(2m), g(2m+6), , g(2m+6i) Park Mode Wake-Up similar HOLD mode
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Transmit/Receive Timing : Page State

Master transmits the paged units DAC(ID) Hop rate increase hopping rate : 3200 hops/s in a single Tx/Rx slot, two different hop frequencies

Listening period : 625 s Uncertainty window 10s

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Transmit/Receive Timing : FHS Packet(1)

FHS packet at connection setup/master-slave switch timing/frequency synchronization Timing of FHS packet on successful page in first half slot

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Transmit/Receive Timing : FHS Packet(2)

Timing of FHS packet on successful page in second half slot

Slave Rx/Tx timing adjust reception of the FHS

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Transmit/Receive Timing : Multi-slave operation

Tx start slot number Master : even numbered slot Slave : odd numbered slot Slave response AM_ADDR addressed slave reserved SCO slave-to-master slot access requests in the park mode

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HOP SELECTION
Page hopping sequence
32(16) unique wake-up frequencies distributed equally over 79(23)MHz period length of 32(16) shifting phase mapping from a counter to Page the hop frequencies

Inquiry sequence
32(16) unique wake-up frequencies distributed equally over 79(23)MHz period length of 32(16) deriving hop sequence LAP : GIAC LAP UAP : DCI

response sequence

Inquiry response sequence

one-to-one correspondence to the current inquiry hopping sequence deriving hop sequence LAP : GIAC LAP UAP : DCI
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one-to-one correspondence to the current paging hopping sequence master/slave using different rules

Channel hopping sequence

long period distributed equally over 79(23)MHz
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HOP SELECTION : General Selection Scheme(1)

Selection scheme selecting a sequence mapping sequence on the hop frequencies Input native clock address

inquiry
CLKN 28 bits

clock
page
masters estimate of the paged unit 28 bits

address inquiry

28 bits LAP/UAP(4 LSBs)

GIAC address

connection
master address

connection

master clock CLK CLKN is modified by an offset 27 MSBs

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page

paged unit address

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HOP SELECTION : General Selection Scheme(2)

Selection scheme selecting a segment of 32(16) hop frequencies choosing randomly the hops Page, page scan, page response using the same 32-hop segment all the time using the address Connection state sliding through 79(23) hops

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HOP SELECTION : Selection Kernel(1)

Kernel input X : phase in the 32(16)-hop segment Y1, Y2 : transmission direction A~D : hops ordering in the segment E, F : mapping on to the hop frequencies Kernel output address of the register Selection Procedure first addition XOR permutation second addition register selection

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HOP SELECTION : Selection Kernel(2)

First addition add a constant to the phase modulo 32(16) page hopping sequence : redundant

XOR operation (output first addition : 4 LSBs) XOR ( A22-19 )

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HOP SELECTION : Selection Kernel(3)

Permutation operation 7 stages of butterfly operation Control signal P
0 8 9 13

D0-8

C i Y1
i = 0, , 4

operation

butterfly implementation

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HOP SELECTION : Selection Kernel(4)

Second addition operation add a constant to the output of permutation modulo 79(23) mapping the 32(16)-hop segment on the hop frequencies

Register bank loaded with the synthesizer code words configuration

upper half : even hop frequencies lower half : odd hop frequencies

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HOP SELECTION : CONTROL WORD(1)

Control Word

Clock types
CLK 27-0 : master clock of the current piconet. CLKN 27-0 : native clock of the unit. CLKE 27-0 : paging units estimate of the paged units native

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HOP SELECTION : CONTROL WORD(2)

Page scan substates
Address : Bluetooth device address of the scanning unit X : CLKN

Inquiry scan substates

Address
0 GIAC LAP 27 23 24 4 LSBs of DCI

X : CLKN

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HOP SELECTION : CONTROL WORD(3)

Page substate
Paging frequencies : 32 paging frequencies, 1.28s interval Paging sequence
A-train : {f ( k 8), B-train : {f ( k + 8),
, f ( k ), , f ( k + 7)} , f (k + 15), f (k 16), , f (k 9)}

X input
( 79 ) 79-hop system : X p = [CLKE1612 + koffset + (CLKE 4 2, 0 CLKE1612 ) mod 16] mod 32

( 23) 23-hop system : X p = [CLKE1512 + 8 + CLKE 4 2, 0 ] mod 16

offset
24 koffset = 8 A train B train

79-hop system : A-train, initialized with 24 23-hop system : A-train, initialized with 8

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HOP SELECTION : CONTROL WORD(4)

Page response : Slave response
Receiving access code Page scan

Slave response

1. Freeze the current CLKN16-12,

* CLKN 16 12

2. Response slot, (N+1)-th

( 23) X prs

( 79 ) * X prs = CLKN 16 12 + N mod 32

* 15 12

[ = [CLKN

] + N ] mod 16

Receiving FHS Send response packet

N : counter Set to zero : receiving the access code N = N + 1, when CLK 1 = 0

Connection state

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HOP SELECTION : CONTROL WORD(5)

Page response : Master response Master response 1. Freeze the current CLKE16-12,
* CLKE16 12

Receiving slave response

2. Freeze the current koffset

* k offset

3. Response slot, (N+1)-th

( 79 ) * * X prm = [CLKE16 12 + k offset + * * (CLKE 4 2 , 0 CLKE16 12 ) mod 16 + N ] mod 32 ( 23 ) * * X prm = CLKE15 12 + 8 + CLKE 4 2 , 0 + N mod 16

N : counter Starting at one : receiving the access code N = N + 1, when CLK 1 = 0

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HOP SELECTION : CONTROL WORD(6)

Inquiry substate
Similar to page substate Clock : inquirer native clock CLKN X input
79-hop system : X i( 79 ) = [CLKN 1612 + koffset + (CLKN 4 2 ,0 CLKN1612 ) mod 16] mod 32 23-hop system : X i( 23) = [CLKN 1512 + 8 + CLKN 4 2, 0 ] mod 16

Address
0 GIAC LAP 27 23 24 4 LSBs of DCI

Offset koffset
79-hop system : arbitary 23-hop system : 8

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HOP SELECTION : CONTROL WORD(7)

Inquiry response
Similar to slave response X input ( 79 ) * 79-hop system : X ir = CLKN 16 12 + N mod 32
( 23) 23-hop system : X ir

[ = [CLKN

* 15 12

] + N ] mod 16

Counter N
FHS packet transmitting in response to the inquiry

Address
0 GIAC LAP 27 23 24 4 LSBs of DCI

Connection state
Clock : Mater clock CLK Address : Master Bluetooth device address

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