1736 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO.

8, AUGUST 2005

A Low-Power CAM Using Pulsed NAND–NOR

Match-Line and Charge-Recycling
Search-Line Driver
Byung-Do Yang and Lee-Sup Kim

Abstract—This paper proposes a low-power CAM using pulsed

NAND-NOR match-line and charge-recycling search-line. The pulsed
NAND–NOR match-line not only significantly reduces the match-line
power by activating only a few match-lines by using NAND cells
for several bits but also achieves high speed by using NOR cells
for most bits. The charge-recycling search-line driver reduces the
search-line power by recycling the charge of search-lines without
precharging. The CAM chip with 128 32 bit is fabricated in a
0.25- m CMOS process with 2.5 V. It dissipates 17.2 fJ/bit/search.
It consumes 31% power of the dynamic NOR-type CAM.
Index Terms—CAM, charge recycling, low power, match-line
(ML), search-line (SL).

I. INTRODUCTION

C ONTENT-ADDRESSABLE memory (CAM) provides a

fast data search function. It compares a search data with all
stored data in parallel and then returns the address at which the
matching data is found. CAM is used in a wide range of appli-
cations such as lookup tables, databases, associative computing,
and data compression. However, it consumes considerably large
power due to its fully parallel comparison. In the search opera-
tion, a large amount of circuitry is active and consumes power.
Moreover, CAM consumes more power as its size increases be-
cause its power consumption is proportional to its memory size.
Fig. 1 shows the simplified CAM architecture consisting of
an array of memory cells, a search word register, a word match
circuit, and an address encoder. Each row of the array stores
a word and a match-line (ML). A search word is supplied on
search-lines (SLs). The CAM compares the search data with
all memory cells and identifies a matching word. As a result
of this parallel comparison, the voltages of MLs are changed.
The major portion of CAM power is consumed in the highly
capacitive MLs and SLs which are charged and discharged in
every cycle [1]–[4].
To reduce the power consumption of CAMs, several tech-
niques were proposed. The NAND-type CAM consumes the least
power but it is the slowest because only a high-precharged ML
is discharged through many transistors in series [1], [3]. In con-
trast, the NOR-type CAM is the fastest but it dissipates the largest
Manuscript received December 12, 2004; revised March 25, 2005. This work
was supported by KOSEF through the MICROS at KAIST, Republic of Korea.
The authors are with the Department of Electrical Engineering and Computer
Science, Korea Advanced Institute of Science and Technology (KAIST), Dae-
jeon 305-701, Korea (e-mail: bdyang@mvlsi.kaist.ac.kr; lskim@ee.kaist.ac.kr).
Digital Object Identifier 10.1109/JSSC.2005.852028
0018-9200/$20.00 © 2005 IEEE
Fig. 1. Simplified CAM architecture.
power because all high-precharged MLs except one are dis-
charged through many transistors in parallel [2], [3]. To achieve
both low power and high speed, several techniques have been
developed based on the NOR-type CAM. Miyatake’s technique
limits the swing voltage of MLs to reduce the power consump-
tion of MLs [4]. Lin’s technique reduces the number of the
activated MLs by using the precomputation-based CAM [5].
Arsovski’s technique reduces the static power consumption of
MLs by allocating less power to the mismatched MLs [6]. It
also reduces the SL power by minimizing the switching activity
of SLs. Choi’s technique significantly saves the ML power by
using the hierarchical search composed of a small NOR-type
main-bank for coarse search and several large NAND-type sub-
banks for fine search [7]. However, this cannot use fully the
memory cells because the data stored in the same sub-bank must
have the same bits in the main-bank.
Without the loss of the memory utilization, the proposed
pulsed NAND–NOR CAM (PNN-CAM) reduces power con-
sumed in both MLs and SLs by using pulsed NAND–NOR
match-line (PNN-ML) and charge-recycling search-line driver
(CRSLD), respectively. The PNN-ML not only significantly
reduces the ML power by activating only a few MLs by using
YANG AND KIM: LOW-POWER CAM USING PULSED NAND–NOR MATCH-LINE AND CHARGE-RECYCLING SEARCH-LINE DRIVER 1737

Fig. 2. Pulsed NAND–NOR ML architecture.

Fig. 3. (a) NAND-ML. (b) NOR-ML.

the NAND cells for several bits but also achieves high speed by
using the NOR cells for most bits. The CRSLD reduces the SL
power by recycling the charge of SLs without the SL precharge.
Fig. 4. Activations in NAND-MLs and NOR-MLs.
The organization of this paper is as follows. In Section II, we
propose the PNN-CAM using the PNN-ML and the CRSLD. In
Section III, we present performance comparisons and show test CAMs. The NAND-ML in the NAND type CAM consumes the
results of the fabricated chip. This paper ends with the conclu- least power but it is the slowest. The NOR-ML in the NOR type
sion in Section IV. CAM is the fastest but it dissipates the largest power.
Fig. 3(a) shows the NAND-ML with NAND cells. The av-
II. ARCHITECTURE erage capacitance of the NAND-ML is
where the
A. Pulsed NAND-NOR Match-Line Scheme matching probability of each bit is and is drain capac-
Fig. 2 shows the pulsed NAND–NOR match-line (PNN-ML) itance of transistors [3]. Its swing voltage is
architecture. The CAM has PNN-MLs and a replica PNN-ML. due to the voltage drop of series NMOS transistors whose gate
Each PNN-ML consists of NAND cells and - NOR cells. The voltage is . The effective capacitance of NAND-ML is
PNN-ML utilizes the advantages of both NAND- and NOR-type where the degradation ratio is .
1738 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005

Fig. 5. Power consumption in mismatched MLs (a) without the replica PNN-ML and (b) with the replica PNN-ML.

The capacitance of ML-precharge transistors is where

is gate capacitance of transistors. Therefore, the NAND-ML
consumes power
. Although the NAND-ML consumes the least power, it is
slow because the high-precharged ML is discharged through
transistors in series.
Fig. 3(b) shows the NOR-ML with NOR cells [2]. During
the precharge time, all SLs are discharged to ground. Each cell
turns on an NMOS transistor connected to the ML. Four drain
capacitances of transistors per bit are connected to the ML. The
capacitance of the NOR-ML is . The capacitance of
ML-precharge transistors is . Therefore, the NOR-ML con-
sumes power .
Although the NOR-ML is the fastest, it consumes a large amount
of power because all high-precharged MLs except one are dis-
charged through some of transistors in parallel.
The PNN-ML utilizes the advantages of both NAND-MLs
and NOR-MLs. In the PNN-ML, only several bits are used
for NAND cells and most bits are used for NOR cells.
Fig. 4 shows the activations in NAND-MLs and NOR-MLs. All Fig. 6. Simulated waveforms of the PNN-ML.
NAND-MLs are activated but they consume a very small amount
of power. The NAND cells reduce the number of activated verter, and the SL charge-recycling (SLCR) signal. When the
MLs. When all NAND cells are matched, the NAND-ML activates NOR cell is matched, it disconnects the ML from ground. Both
its ML of NOR cells. If the matching probability of each bit is and ground are supplied to the gates of NMOS transistors
, the matching probability of NAND cells is . The in the replica NOR cells to disconnect the replica ML (RML)
number of activated MLs is reduced from to where from ground, as shown in Fig. 2.
is the number of MLs in the CAM. When and , Fig. 6 shows the simulated waveforms of the PNN-ML. At
only two MLs are activated on the average. The PNN-ML saves first, the SLs are driven to or ground. The match-line
the power by reducing the number of activated MLs with NOR precharge (MLPC) signal is “1” and the MLE is “0.” All MLs
cells. are discharged to ground by the MLPC. All NAND-MLs are
At most, one of the activated MLs is matched. The matched precharged to by the MLE. Then, the MLPC becomes
ML consumes the dynamic power to charge the ML to . “0” and the MLE becomes “1.” The replica NAND-ML is
Most activated MLs are not matched. The mismatched MLs con- discharged to ground and it supplies current to the RML with
sume the static power during the time when their NAND cells are a ML-charging PMOS transistor. At the same time, a few
matched, as shown in Fig. 5(a). To minimize the static power, matched NAND-MLs are discharged and they supply currents
the PNN-ML uses the pulsed match-line enable (MLE) signal to their MLs. When the RML is higher than , the MLE
generated by a replica PNN-ML, as shown in Fig. 5(b) [8]. The returns to “0.” In practice, the RML rises to by
replica PNN-ML consists of series NMOS transistors in the adding the delay element for the reliable operation in MLs.
replica NAND cells and parallel NMOS transistors All NAND-MLs are precharged and all ML-charging PMOS
in the replica NOR cells, as shown in Fig. 2. When the NAND transistors are turned off. After that, the RML and matched ML
cell is matched, the gate voltage of series NMOS transistors is are charged from to by the PMOS transistor
. To make the same delay as the ML, is keepers in the output drivers. The RML and matched ML con-
supplied to the gates of NMOS transistors in the replica NAND sume the dynamic power. All mismatched MLs consume the
cells. This voltage is generated by an NMOS transistor, an in- static power only during the short pulse when the MLE is “1.”
YANG AND KIM: LOW-POWER CAM USING PULSED NAND–NOR MATCH-LINE AND CHARGE-RECYCLING SEARCH-LINE DRIVER 1739

TABLE I
EFFECTIVE CAPACITANCE COMPARISONS OF MLs

Fig. 7. Architectures of the PNN-ML when (a) m = 32 and (b) m = 144.

The PNN-ML significantly saves the ML power by activating a fective capacitance per ML is .
few MLs and by reducing the static power in the mismatched When , and , it is only . As a
MLs with the pulse operation. result, the PNN-ML consumes power
Each PNN-ML consumes power in -bit NAND-ML, .
-bit ML, and three ML-precharge transistors. The capacitances Table I tabulates the effective capacitances of MLs.
of NAND-ML and ML-precharge transistors are In summary, the PNN-ML reduces the number of activated
and , respectively. The capacitances of both RML and MLs from to by using NAND cells, and then it saves the
matched ML are . The power consumption static power consumed in the activated MLs by using the pulse
of the mismatched ML is smaller than that of the RML because operation of the replica PNN-ML. The PNN-ML consumes
the mismatched ML consumes the static power during the time power in all NAND-MLs, a few MLs, and three ML-precharge
when the RML is charged to instead of . To transistors per ML. The power of PNN-ML is a little larger than
simplify the power consumption of the mismatched MLs, we that of the NAND-ML. The delay of PNN-ML is the summation
approximate the effective capacitance of the mismatched ML of delays of -bit NAND-ML and -bit NOR-ML. The
as that of the RML. The total number of the RML and all ac- PNN-ML is a little slower than the NOR-ML due to the delay of
tivated MLs is and the capacitance of the MLs is the small -bit NAND-ML.
. Therefore, the total capacitance of the RML Although the NOR-ML is much faster than the NAND-ML, its
and all activated MLs are . The ef- delay increases proportional to . Therefore, as increases,
1740
Fig. 8. Power and delay comparisons of MLs when (a) n = 128 and m = 32 and (b) n = 512 and m = 144.
Fig. 9. CAM architecture.
the PNN-ML becomes slow. To improve the speed, it utilizes
the hierarchical ML in [7]. Fig. 7 shows the architectures of the
PNN-ML. When , the PNN-ML is relatively fast. How-
ever, when , it becomes slow. To improve the speed,
the PNN-ML is hierarchically divided into four sub-PNN-MLs
with bits. The sub-PNN-ML consists of NAND cells and
NOR cells. The search result is hierarchically gener-
ated by four sub-PNN-MLs with three AND gates. Its delay is
equal to the summation of delays of -bit sub-PNN-ML, two
AND gates, and the hierarchical ML wires. Although the hierar-
chical PNN-ML consumes more power due to four NAND-MLs,
12 ML-precharge transistors, three AND gates, and the hierar-
chical ML wires, it is much faster.
Fig. 8 shows the power and delay comparisons of MLs. All
simulations in this paper are performed in a 0.25- m CMOS
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005
process with V. When and ,
it consumes 20% more power but it is three times faster than
the NAND-ML. Also, it is 19% slower but it consumes 89% less
power than the NOR-ML. When and , it
consumes 76% more power but it is 23 times faster than the
NAND-ML. Also, it is 28% faster and it consumes 90% less
power than the NOR-ML. This saves the power of MLs by re-
ducing the number of activated MLs and by using the pulse op-
eration. When , the PNN-ML with the hierarchical ML
is faster than the NOR-ML.
Fig. 9 shows the CAM architecture. During search opera-
tion, the I/O circuits catch and send the search data to SLs. The
SLs are connected to all memory cells. The CAM compares the
search data in SLs to the stored data. 128 32 bit memory is
divided into four sub-blocks with 32 32-bit memory in order
YANG AND KIM: LOW-POWER CAM USING PULSED NAND–NOR MATCH-LINE AND CHARGE-RECYCLING SEARCH-LINE DRIVER
Fig. 10. CRSLD.
to reduce the delay of the SL. When a ML is matched, the ad-
dress of the matched ML is encoded in the ROM encoder. The
encoded search address is send to the output pad of the chip by
the I/O circuits.
B. Charge-Recycling Search-Line Driver
In the PNN-ML, the SLs are not precharged because search
data change while all MLs are discharged to ground. The SLs
consume power only when the search data change. In general,
the transition probability of SL is smaller than one half. The
nonprecharged SLs consume less power than half of that of the
precharged SLs [6]. The CRSLD further saves the SL power by
recycling the charge of SLs.
Fig. 10 shows the CRSLD. Initially, the SLCR is “0.” The
transistor P1 turns on. The CR is “0.” The transmission gates
T1 and T2 turn off. Two tri-state drivers D1 and D2 drive the
SL pairs. The latch holds the data of SLs. The SLCR becomes
“1.” The transistor N1 turns on. When the search data change
from “0” to “1,” the transistors N2 and N3 turn on. When the
search data change from “1” to “0,” the transistors N4 and N5
turn on. Therefore, the CR becomes “1.” T1 turns on and two
SLs share their charges. The SLs become . T2 turns on
and the latch updates its data. If the search data do not change,
the CR remains at “0.” The SLCR returns to “0” and the CR
becomes “0.” T1 and T2 turn off. D1 and D2 drive the SL pairs
from to or ground.
Table II shows the power comparison of SLs. The precharged
SL driver consumes power where is the
capacitance of SL, because the SLs are precharged in every
clock cycles. The nonprecharged SL driver consumes power
where is the transition probability
of SL, because it drives the SLs only when search data changes
[6]. The nonprecharged SL driver consumes less power than a
half of power of the precharged SL driver.
Fig. 11 shows waveforms of the CRSLD. When search data
change, the CRSLD recycles the charge in SLs and then drives
1741
TABLE II
POWER COMPARISONS OF SLs
the SLs by the SLCR signal during search cycles. Therefore, the
CRSLD theoretically consumes power
which is half of power of the nonprecharged SLs. The CRSLD
theoretically consumes only one-fourth and one-half power of
the precharged SLs and the nonprecharged SLs when ,
respectively.
Fig. 12 shows the power comparisons of SLs. A single SL
is attached to cells where is the number of MLs. When
and , the CRSLD saves 60% and 21% power
compared to the precharged SL (PC-SL) and the nonprecharged
SL (NPC-SL), respectively. Although the SLs of the CRSLD
consume only one-half and one-fourth power of the precharged
SL and the nonprecharged SL, the power savings of the CRSLD
are reduced due to the control overhead. When and
, the CRSLD saves 84% and 21% power compared to
the precharged SL and the nonprecharged SL. As decreases,
the CRSLD saves more power.
Fig. 13 shows the power comparisons of SLs. When
and , the CRSLD consumes less power than the
nonprecharged SL. As increases, the power of the CRSLD
is close to one-fourth and one-half of the precharged SL and the
nonprecharged SL, because the power of SLs is proportional to
but the power of drivers is independent of . When ,
the power of the CRSLD becomes much smaller. When
, the CRSLD consumes less power than the nonprecharged
SL. As increases, the power of the CRSLD is close to one-
tenth and one-half of the precharged SL and the nonprecharged
1742 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 8, AUGUST 2005

Fig. 11. Waveforms of the CRSLD.

Fig. 12. Power comparisons of SLs when n = 128 and (a)  = 0:5 and (b)  = 0:2.

Fig. 13. Power comparisons of SLs according to n when (a)  = 0:5 and (b)  = 0:2.

SL. As increases and decreases, the CRSLD saves more
power.
III. PERFORMANCE COMPARISON AND TEST RESULTS
A. Performance Comparisons
Fig. 14 shows the energy and delay comparisons of various
CAMs. For a fair comparison, the proposed PNN-CAM, the dy-
namic NAND-type CAM using the NAND-MLs (NAND-CAM) [3],
the dynamic NOR-type CAM using the NOR-MLs (NOR-CAM)
[2], the current saving CAM (CS-CAM) [6], and the Hy-
brid-type CAM (Hybrid-CAM) [7] are simulated in a 0.25- m
CMOS process with V.
The NAND-CAM consumes the least ML power but it is
the slowest. The NOR-CAM is the fastest but it consumes the
largest ML power because all MLs precharged to and
then discharged to ground. With the speed of the NOR-CAM,
the CS-CAM reduces the ML power by supplying large cur-
rent to the matched ML and small current to the mismatched
MLs. Also, the SLs are not precharged. The Hybrid-CAM
further reduces the ML and SL power by using the hierarchical
search composed of a small NOR-type main-bank and several
large NAND-type sub-banks. The result of the main-bank ac-
tivates only a sub-bank. The main-bank is fast and consumes
a little power because it is a small NOR-CAM. The selected
sub-bank consumes a small amount of power because it uses the
NAND-MLs. To improve the speed of the NAND-MLs, we apply
the hierarchical ML structures and it inserts many of the ML-re-
peaters into the NAND-MLs. The Hybrid-CAM consumes the
least power in both MLs and SLs among the previous CAMs.
YANG AND KIM: LOW-POWER CAM USING PULSED NAND–NOR MATCH-LINE AND CHARGE-RECYCLING SEARCH-LINE DRIVER 1743

Fig. 15. Chip microphotograph of the PNN-CAM.

Fig. 14. Energy/bit/search and delay comparisons when CAM sizes are
2 2
(a) 128 32 bit and (b) 512 144 bit.

Also, it achieves high speed. However, this has a drawback. It

cannot use fully the memory cells because the data stored in
the same sub-bank must have the same bits in the main-bank.
Fig. 14(a) shows the energy and delay comparisons of CAMs
with 128 32 bit. The PNN-CAM with 128 32 bits consumes
17.2-fJ/bit/search with 3.8-ns search time. It consumes the
least power. Without the loss of the memory utilization, the
PNN-CAM reduces the power consumed in both MLs and Fig. 16. Measured waveforms of the PNN-CAM at 200 MHz.
SLs by using the PNN-ML and CRSLD, respectively. The
power saving of the PNN-CAM is only 4% compared to the
Therefore, the PNN-CAM is not only the fastest but also it con-
Hybrid-CAM. However, the PNN-CAM is faster than the Hy-
sumes the least power.
brid-CAM, because the PNN-CAM is based on the NOR-ML but
the Hybrid-CAM is based on the NAND-ML. The PNN-CAM
saves 69% and 50% power of the NOR-CAM and CS-CAM. B. Test Results
It is the fastest CAM except the NOR-CAM. It is 5% and 21% The test chip is fabricated in a 0.25- m CMOS process.
faster than the CS-CAM and the Hybrid-CAM, respectively. Fig. 15 shows the chip microphotograph. The features of
Fig. 14(b) shows the energy and delay comparisons of CAMs the chip are tabulated in Table III. The power is measured
512 144 bit. The PNN-CAM with 512 144 bit consumes 9.0 at 200 MHz with V. The chip core dissipates
fJ/bit/search with 6.1 ns search time. It consumes the least power 17.2-fJ/bit/search. The chip core area is 0.32 mm . Fig. 16
and it is the fastest. In the large CAM, the energy of the control shows the measured waveforms at 200 MHz. During search
unit and encoder is negligible compared to that of MLs and SLs. cycles, if input data is matched, the corresponding address is
The Hybrid-CAM is faster than the NOR-CAM and CS-CAM be- generated. In the measured waveforms, then input data is “1,”
cause it achieves high speed in a long ML with the hierarchical the data is matched and the precharged address is discharge
ML structure. The PNN-CAM further reduces the delay of ML to ground during a half clock cycles. Its maximum operating
by using both the NOR-ML and the hierarchical ML structure. frequency is 260 MHz at V.
1744
TABLE III
FEATURES OF THE PNN-CAM CHIP
IV. CONCLUSION
The PNN-CAM is proposed to achieve low power and high
speed. The PNN-CAM reduces the ML power by using the
PNN-ML. The PNN-ML not only significantly reduces the
ML power by activating only a few MLs by using the NAND
cells for several bits but also achieves high speed by using
the NOR cells for most bits. To reduce the delay of long MLs,
the hierarchical ML is utilized. The PNN-CAM reduces the
SL power by using the CRSLD. The CRSLD reduces the SL
power by recycling the charge of SLs without the SL precharge.
The small PNN-CAM with 128 32 bit consumes only 31%
power with 19% speed degradation compared to the dynamic
NOR-type CAM. The large PNN-CAM with 512 144 bit
consumes only 21% power with 39% speed improvement. The
PNN-CAM chip with 128 32 bit is fabricated in a 0.25- m
CMOS process with V. The chip core dissipates
17.2-fJ/bit/search. Its area is 0.32 mm . Its maximum operating
frequency is 260 MHz.
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Byung-Do Yang received the B.S., M.S., and Ph.D.
degrees in electrical engineering and computer sci-
ence from the Korea Advanced Institute of Science
and Technology (KAIST), Daejeon, Korea, in 1999,
2001, and 2005, respectively.
He joined the Memory Division, Samsung Elec-
tronics, Kyungki-Do, Korea, in 2005, where he has
been engaged in the design of DRAM. His research
interests include low-power DRAM circuits.
Lee-Sup Kim received the B.S. degree in electronics
engineering from Seoul National University, Seoul,
Korea, in 1982 and the M.S. and Ph.D. degrees in
electrical engineering from Stanford University,
Stanford, CA, in 1986 and 1990, respectively.
He was a Postdoctoral Fellow with the Toshiba
Corporation, Kawasaki, Japan, during 1990–1993,
where he was involved in the design of the high-per-
formance DSP and single-chip MPEG2 decoder.
Since March 1993, he has been with the Korea
Advanced Institute of Science and Technology,
Daejeon, Korea. In November 2002, he became a full Professor. His research
interests are multimedia VLSI design, hardware implementation of signal
processing algorithms, and low-power IC design.