ADC Subsystem Final Report

Prepared By: Team #Hashtag Timothy Hackett Kyle Emerson 30 April 2014

Table of Contents
List of Figures ........................................................................................................................................... 3 List of Tables ............................................................................................................................................. 4 Introduction ............................................................................................................................................... 5 Rationale ................................................................................................................................................... 5 Theory of Operation .............................................................................................................................. 5 Theory of Interfaces .............................................................................................................................. 6 Implementation ......................................................................................................................................... 6 Code and Circuitry ................................................................................................................................ 6 Verification Testing ............................................................................................................................... 9 Description of Sensor and Relation to Overall System..................................................................... 9 Module and Interface Schematics ................................................................................................... 10 Method of Testing ............................................................................................................................11 Testing Results ................................................................................................................................ 12 Requirements Verification............................................................................................................... 16 Validation Testing................................................................................................................................ 16 Results from Integrated System .......................................................................................................... 16 Discussion ............................................................................................................................................... 23 Value Statement....................................................................................................................................... 24 Conclusion .............................................................................................................................................. 24 Appendix ................................................................................................................................................. 25

List of Figures
Figure 1: Subsystem Block Diagram ........................................................................................................ 5 Figure 2: Initialization Code ..................................................................................................................... 6 Figure 3: CAN Messaging Code ............................................................................................................... 7 Figure 4: First Portion of Main Function .................................................................................................. 7 Figure 5: Second Portion of Main Function.............................................................................................. 8 Figure 6: Code Flow Block Diagram ........................................................................................................ 9 Figure 7: System Diagram ...................................................................................................................... 10 Figure 8: Subsystem Schematic .............................................................................................................. 10 Figure 9: Interface Diagram .....................................................................................................................11 Figure 10: Test A.1 .................................................................................................................................. 12 Figure 11: Test A.2 .................................................................................................................................. 13 Figure 12: Test A.2 .................................................................................................................................. 13 Figure 13: Test A.3 .................................................................................................................................. 13 Figure 14: Test A.3 .................................................................................................................................. 13 Figure 15: Test B.1 .................................................................................................................................. 14 Figure 16: Test B.2 .................................................................................................................................. 14 Figure 17: Test B.3 .................................................................................................................................. 14 Figure 18: Test AB.1 ............................................................................................................................... 15 Figure 19: Test ABC.1............................................................................................................................. 16 Figure 20: Test ABC.1............................................................................................................................. 16 Figure 21: Output of 1Vpp, 1 Hz Sine Waveform Input ......................................................................... 17 Figure 22: Output of 2Vpp, 1 Hz Sine Waveform Input ......................................................................... 17 Figure 23: Output of 3Vpp, 1 Hz Sine Waveform Input ......................................................................... 17 Figure 24: Output of 4Vpp, 1 Hz Sine Waveform Input ......................................................................... 17 Figure 25: Output of 5Vpp, 1 Hz Sine Waveform Input ......................................................................... 17 Figure 26: Output of 1Vpp, 10 Hz Sine Waveform Input ....................................................................... 18 Figure 27: Output of 2Vpp, 10 Hz Sine Waveform Input ....................................................................... 18 Figure 28: Output of 3Vpp, 10 Hz Sine Waveform Input ....................................................................... 18 Figure 29: Output of 4Vpp, 10 Hz Sine Waveform Input ....................................................................... 18 Figure 30: Output of 5Vpp, 10 Hz Sine Waveform Input ....................................................................... 18 Figure 31: Oscilloscope Capture of Input/Output Waveform ................................................................. 19 Figure 32: Black Box Op-Amp Schematic ............................................................................................. 19 Figure 33: Output of 1Vpp, 1 Hz Square Waveform Input ..................................................................... 20 Figure 34: Output of 2Vpp, 1 Hz Square Waveform Input ..................................................................... 20 Figure 35: Output of 3Vpp, 1 Hz Square Waveform Input ..................................................................... 21 Figure 36: Output of 4Vpp, 1 Hz Square Waveform Input ..................................................................... 21 Figure 37: Output of 5Vpp, 1 Hz Square Waveform Input ..................................................................... 21 Figure 38: Output of 1Vpp, 10 Hz Square Waveform Input ................................................................... 22 Figure 39: Output of 2Vpp, 10 Hz Square Waveform Input ................................................................... 22 Figure 40: Output of 3Vpp, 10 Hz Square Waveform Input ................................................................... 22 Figure 41: Output of 4Vpp, 10 Hz Square Waveform Input ................................................................... 22 Figure 42: Output of 5Vpp, 10 Hz Square Waveform Input ................................................................... 22 Figure 43: Black Box Schematic ............................................................................................................ 23

List of Tables
Table 1: Test Plan .................................................................................................................................... 12 Table 2: Bill of Materials ........................................................................................................................ 25

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Introduction
In any engineering environment, complex problems are taken apart and simplified into smaller, more specific tasks that are integrated and validated to achieve a viable solution. Within systems engineering, a complex system is broken down into several subsystems that communicate to one another to verify and validate another system. In Lab 3, subsystems are integrated together to analyze and characterize the hidden circuitry within a black box. The system consists of 4 main subsystems: a waveform generator, a gain amplifier, an ADC, and a keypad that controls the entire system. With proper communication and implementation, this system will effectively describe the response to an input signal. The purpose of our subsystem, the ADC, is to sample the output of the black box. This converter collects data from the output waveform and then exports the sample data to a CSV file where it is analyzed later. The ADC subsystem provides the final step in this diagnostics system and is essential for the completion of the embedded system. With the data provided by this subsystem, an analysis can be conducted to characterize the black box, which solves the problem presented in this lab.

Rationale
Theory of Operation
The ADC subsystem is made up of three main components: the sampling unit, file writer unit, and the CAN bus unit. The subsystem functional block diagram (Figure 1) shows the relationships between these three units:

Figure 1: Subsystem Block Diagram The sampling unit first samples the output of the black box and then quantizes this value to a finite resolution. The sampling unit sends the 12-bit words representing the voltage waveform to the file writer unit upon request.

Page 6 The purpose of the file writer unit is to write the sampled 12-bit words to a comma-separated values (CSV) file format. The file is stored on the internal flash memory for review after the black box testing is complete. The CAN bus unit communicates with the keypad subsystem to determine when the ADC subsystem should start/stop sampling and writing to a CSV file. The keypad subsystem sends 0x0A to start/stop the sampling process and 0x0B to close the CSV file. The CSV file needs to be closed in order to review the data afterwards.

Theory of Interfaces
There are two internal interfaces within the ADC subsystem: the sampling unit/file writer unit interface and the file writer/CAN bus unit interface. The file writer unit communicates using an I2C bus. This is a half-duplex communication protocol where the file writer is the master device and the sampling unit is the slave device. As a result, the sampling unit can only transmit data when the file writer initiates the communication. This bus is used to send commands to reconfigure the sampling unit's operations, as well as, to transmit the digitally encoded words representing the sampled analog waveform to the file writer unit. The interface between the file writer and CAN bus unit is a 3.3V TTL logic signal that represents the CAN bus data before it is converted to the standard CAN differential signal. The purpose of this interface is send the demodulated commands from keypad subsystem to the file writer unit. Additionally, there are three external interfaces of the ADC subsystem: the file writer/computer interface, the sampling unit/black box output interface, and the CAN bus unit/keypad subsystem interface. The file writer and computer communicate over the universal serial bus (USB). This has two purposes: to transfer the CSV file to the computer for review, as well as, for testing/debug purposes. For testing, the file writer unit prints the sampled output waveform data to a serial terminal emulator on the computer. The black box output waveform communicates with the sampling unit using just a 0 to 3.3V analog interface. Finally, the CAN bus unit communicates with the keypad subsystem using a CAN bus. The CAN bus unit listens on the bus for commands from the keypad subsystem and demodulates them to a 3.3V TTL logic signal.

Implementation
Code and Circuitry

Figure 2: Initialization Code The mbed program consists of three sections of code: initialization, interrupt routine, and sampling and writing to a file. First, the libraries for the mbed and ADS1015 are included. The ADS1015 is an analog-to-digital converter with 12-bit resolution. The peripherals are assigned to indicate the operation and pin numbers used in the system. Line 5 in Figure 2 sets up the mbed to communicate with a host PC through its two USB pins. Then the I2C interface is set for pins 27 and 28 on the mbed.

Page 7 This interface is used to communicate with the Adafruit ADS1015. Finally, the CAN bus is initialized on pins 29 and 30: TX and RX, respectively. It is important that a 120 pull-up resistor is used at each end of the bus so that it works properly. The two global variables, status and msg, are initialized as well.

Figure 3: CAN Messaging Code Next is the interrupt routine where the sampling status is updated in the program. In line 16 (Figure 3), the CAN transceiver reads the CAN message from the bus and stores it in the variable msg. The char code is then set to the first piece of data in the msg. This message is retrieved from the keypad subsystem. The following sequence of if-else statements controls the state or status of the program. The three statuses in this program are: 1 sampling, 2 pause sampling, and 3 kill/end sampling. If the message from the keypad is 10 and status = 2, then the status will change to 1 and the program will sample the input. If the message is 10 and status = 1, then the status changes to a 2 and sampling is paused. If the message is 11, the program will end sampling. If any other message is sent through the CAN bus, then the status will remain the same.

Figure 4: First Portion of Main Function Within the main section of the program (Figure 4), initialization begins by setting the status to 2, meaning it is in the paused state. The baud rate is set to 115200. The file directory for the CSV file is then initialized. A sequence of three lines is then printed to PuTTY. These statements include the ADC range and channel that is being read from the ADS1015. The function sample_status is then attached to call it whenever a CAN frame receive interrupt is generated. The ADC channel is defined and adc0 is set as an unsigned 16-bit integer. The conversion factor is set at 0.0020488281. The A0 channel on the ADS1015 is then read and converted continuously. The file adc_output.txt is then opened to be written to later.

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Figure 5: Second Portion of Main Function The last section of the code involves the sampling code. If the status is 1 (sampling), then adc0 is set to get the last ADC conversion. The value is multiplied by the conversion factor and printed to the screen. This value is also sent to the text file with a comma separating each subsequent value. If the status is 3 (end sampling), then the file is closed and the program ends by getting out of the while loop. This program meets all of the requirements set forth for the ADC subsystem. The entire program is summarized with the code flow block diagram on the next page (Figure 6):

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Figure 6: Code Flow Block Diagram

Verification Testing
Description of Sensor and Relation to Overall System The purpose of our subsystem is to sample an analog waveform at 100 samples per second. The analog waveform is constricted to a 0 to 3.3V amplitude. The samples are written to a comma-separated values (CSV) file upon command over CAN bus. From a system perspective, our subsystem is just one

Page 10 of four subsystems as shown in Figure 7 on the next page.

Legend: Analog Digital
Keypad Subsystem (Control)

CAN BUS
Digital-to-Analog Converter Subsystem (Waveform Generator) Digital Potentiometer Subsystem (Gain) Analog to Digital Converter Subsystem (Sampling) USB

Black Box

Computer (Data Analysis)

Figure 7: System Diagram The DAC and DigiPot subsystems are responsible to generate sine and square waveforms of multiple amplitudes and frequencies upon command over CAN bus. These waveforms are inputted into the black box circuit. Our subsystems purpose is to record the output of the black box for any input given. The keypad group controls the other subsystems using CAN. Module and Interface Schematics
VCC U1
1 GND 3.3V Out40 2 VIN 5.0V Out39 3 VB IF- 38 IF+ 37 4 nR MOSI RD- 36 5 RD+35 6 MISO TD- 34 7 SCK TD+ 33 8 D- 32 9 TX D+ 31 10 RX CAN rd 30 11 MOSI CAN td 29 12 MISO I2C SDA 28 13 SCK I2C SCL27 14 PwnOut26 15 SCK 16 AnalogIN PwnOut25 17 AnalogIN PwnOut24 18 AnalogIN PwnOut23 19 AnalogIN PwnOut22 20 AnalogIN PwnOut21

VDD 3.3V 5V

U3
1TXD 2VSS 3VDD 4 RXD
RS 8 CANH7 CANL6 VREF5

R3 120

MCP2551 R2 10k R1 U2 10k 1 VDD

2 GND 3 SCL 4 SDA 5 ADDR 6 ALRT 7 A0 8 A1 9 A2 10 A3

mbed XFG1

ADS1015

Figure 8: Subsystem Schematic Figure 8 shows the module schematics of the ADC subsystem. The mbed runs on a 32-bit ARM Cortex-M3 LPC1768 microprocessor with a clock speed of 96 MHz. The 512KB flash memory onboard allowed us to save the CSV files to internal memory, as opposed to, having another discrete

Page 11 chip for memory. The ADS1015 12-bit analog-to-digital converter communicates over I2C with the mbed. The pull-up resistors are required for proper I2C operation. Finally, the MCP2551 high-speed CAN transceiver communicates with the mbed using serial.
Host PC

USBRX USBTX +5V GND

CANH CANL ADC Subsystem Black Box AIN0 AGND

Other Subsystems

CSV File (stored in local FS)

Figure 9: Interface Diagram From an interface perspective, the ADC subsystem has many types of inputs and outputs as shown in Figure 9. The CAN bus output allows our subsystem to communicate with the all the other subsystems in a common, simple protocol. The USB cable for the mbed provides UART serial, as well as, a 5V voltage rail. AIN0 is the input to the analog-to-digital converter, so the output of the black box connects to this. Finally, a CSV file representing the sampled waveform is saved on the internal flash memory that can be read by the user later. Method of Testing A test plan (Table 1 below) was followed to ensure our subsystem was fully functional. Tests A.1-A.3 ensured the ADC operated correctly, configured it for continuous conversion, and tested the functionality of starting and stopping sampling by serial ASCII commands. A square wave and sine wave produced by a function generator were used as sample inputs to the ADC. Tests B.1-B.3 tested writing to a file in the CSV format and when commanded by serial ASCII commands. Tests C.1-C.2 initialized the CAN bus and parsed messages for a start/stop command. Tests AB.1 and ABC.1 integrated these units together.
'A Tests' Test A.1 :: ADC Description Read ADC Single Ended Single Shot Continuous Conversion Mode Test Start/Stop Using Serial Commands

Note Use the provided library function to prove circuitry works Modify library function so the ADC continuously converts samples instead of single-shot conversions Use PC keyboard commands to start and stop sampling

Sample Input DC Rails

A.2 A.3

Function Generator Function Generator

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'B Tests' Test B.1 B.2 B.3 'AB Tests' Test AB.1 'C Tests' Test C.1 C.2 'ABC Tests' Test :: CSV File Description Open, Write, and Close a File Make a CSV File with Generated Data Start/Stop Using Serial Commands :: ADC & CSV File Writing Description ADC Sampling and Writing to a File Using Serial Commands :: CAN Bus Communication Description Sample CAN Bus Communications Parse CAN Messages for Start/Stop Note Use the sample mbed code from the online handbook Use a loop to generate a sequence and then write to a CSV file Use PC keyboard commands to start and stop writing to a file Sample Input Hard coded data Deterministic Data Deterministic Data

Note Integrate the code base from 'A.3' and 'B.3'

Sample Input Function Generator

Note Use two mbeds and the mbed handbook code to prove the circuitry works Parse various messages and ignore anything that isn't start/stop or close file

Sample Input A second mbed with CAN transceiver A second mbed with CAN transceiver

:: Full Subsystem Integration Description Note Start/Stop sampling based on CAN messages and write the samples to a CSV file

ABC.1

Fully Integrated System

Sample Input A second mbed with CAN txr, Function Generator

Table 1: Test Plan This test plan was essential for having a procedure on how to program the mbed. A new code project was created for each test series ('A', 'B', 'C', etc.) to keep everything documented and organized. Additionally, the output data for all of the tests were saved. Testing Results Test A.1 Test A.1 used the default code for continuous conversion from the supplied library. The data was outputted to the terminal and then saved to a file on the host PC. Figure 10 below shows our sampled data. The voltage source was just connecting the AIN0 input of the ADC into the 3.3V and GND voltage rails.
Test A.1 (Manually connecting to DC rails)

Voltage (V)

4 3 2 1 0 0 5 10 15 20

Samples (n)

Figure 10: Test A.1

Page 13 Test A.2 For Test A.2, we changed the code to have a dynamic change of +/- 4.096V and a sample rate of 128 samples per second. For an input, we used a signal generator to produce low frequency (1-10 Hz) sine and square waves. The expected results below in Figure 11 and Figure 12 proved that our custom code worked correctly.
Test A.2 (Sine Wave)
2.5 2.5 2 1.5 1 0.5 0 0 20 40 60 80 100 2 1.5 1 0.5 0 0 20 40 60 80 100 120

Test A.2 (Square Wave)

Voltage (V)

Voltage (V)

Samples (n)

Samples (n)

Figure 11: Test A.2

Figure 12: Test A.2

Test A.3 For Test A.3, we included serial start and stop commands in order to control the sampling process of the subsystem. For an input, we used a signal generator to produce low frequency (1-10 Hz) sine and square waves. The red circles on Figure 13 and Figure 14 below indicate where the sampling was started and stopped. On the sine wave, discontinuities show start/stop points. On the square wave, the differing lengths of high and low voltages indicate the start/stop points. After Test A.3, the sampling portion of the subsystem was proven to work correctly.
Test A.3 (Square Wave)
2.5 2 1.5 1 0.5 0 -25 25 75 125 175 2.5

Test A.3 (Sine Wave) Votltage (V)

2 1.5 1 0.5 10 30 50 70 90 110

0 -10

Samples (n)

Figure 13: Test A.3

Figure 14: Test A.3

Test B.1 Similar to Test A.1, Test B.1 used sample code from mbeds website for writing Hello World! to a file. Each time this program was executed, Hello World! was written on a new line. The file was saved as OUT.TXT on the mbeds files ystem. Figure 15 below is a screenshot of the file after the program was run four times. Line 1 of the file was added on the host PC afterwards to identify the data:

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Figure 15: Test B.1 Test B.2 We modified the code from Test B.1 so that given an array of numbers, it generated a comma-separated values (CSV) file. Our code just created an array from 0 to 9 and wrote it to OUT2.TXT as shown below in Figure 16. Line 1 of the file was added on the host PC afterwards to identify the data:

Figure 16: Test B.2 Test B.3 The purpose of Test B.3 was to start and stop writing to a file using serial commands. To test this function, our program wrote 1 to the file every second until commanded to stop writing. After executing the program, we counted the amount of 1s written to ensure the code executed correctly. The file shown below in Figure 17 is formatted as a CSV. Line 1 of the file was added on the host PC afterwards to identify the data:

Figure 17: Test B.3 Test AB.1 Test AB.1 integrated the code from Tests A.3 and B.3 to create a program that could sample and record to a CSV file using serial commands. 1 was sent to start sampling; 2 was sent to stop sampling; and 3 was sent to close the file and exit the program. A sine wave was used as the sample input into the ADC. The integration of these two units went smoothly, and the recorded data is plotted below in Figure 18. The discontinuity circled in the sine wave below is where the subsystem was commanded to stop sampling and then start again.

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Test AB.1
2.5 2

Voltage (V)

1.5 1 0.5 0 -5

15

35

55

75

95

115

Samples (n)

Figure 18: Test AB.1 Test C.1 The purpose of Test C.1 is to prove the functionality of the CAN bus circuitry. We connected another mbed with a CAN bus transceiver to emulate the keypad subsystem. Test C.1 just used the prewritten code available on mbed.org to make sure everything was wired correctly. The output was just a simple statement that printed to terminal that a message was transmitted and/or received. Test C.2 Test C.2 modified the CAN bus code in order to parse messages over the CAN bus for start/stop and close file commands. Due to the limited amount of keys on the keypad, we changed our commanding scheme to have one message that toggles starting and stopping sampling and another message to close the file. This test worked as expected with our keypad emulator circuitry. Test ABC.1 Test ABC.1 is the full subsystem test. The subsystem can be commanded to start/stop sampling and recording to a CSV file using CAN bus messages. Our keypad emulator circuit was used once again to verify that when we integrated with the keypad subsystem, there would be no issues. It was during this test that we tried many different frequencies and boosted the sampling rate to over 100 Hz as required. As shown in Figure 19 and Figure 20, we got some unexpected results:

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Test ABC.1
2.5 2.5 2 1.5 1 0.5 0 200 400 600 800 0 -0.5 0 50 100 150 200

Test ABC.1

Voltage (V)

2 1.5 1 0.5 0

Samples (n)

Figure 19: Test ABC.1

Figure 20: Test ABC.1

In Figure 19, there are discontinuities in a regular interval circled in green. The data plotted in Figure 20 looks very jagged and also has discontinuities. When the same data was taken from the terminal and plotted, the plots looked smooth and continuous. After debugging and researching, it was determined that fprintf has a different write buffer size than printf. Printf and fprintf also flush their write buffers under different conditions. What ended up happening is that the discontinuities is when the data is actually being written to the file unlike how we thought our code was executed. In order to fix this, we forced a buffer flush after every single write to the file. This fixed the discontinuity problem but caused the effective sampling rate to be under 100 Hz because the file system on the mbed was too slow. As a result, the requirement for writing to a CSV was removed as a requirement for the project by the TAs. Requirements Verification The requirements relevant to the ADC subsystem were Requirements 3a, 3b, 3c, 5b, and 6. Requirements 3a and 3b were verified prior to integration through Test ABC.1. Requirement 3c was verified when our subsystem integrated to the keyboard subsystem. Even prior to integration, we used another mbed and serial keyboard input to send CAN messages to our subsystems to simulate the keyboard subsystem. Requirement 5b was satisfied by configuring the ADS1015 for a dynamic range of +/- 4.096 V. Therefore, any output of the black box would be sampled correctly. Finally, Requirement 6 was verified by inspection once all of the subsystems integrated together.

Validation Testing
The ADC is an essential part of the entire system. Given a specific input signal with a specified voltage and frequency from the DAC subsystem and DigiPot subsystem, our module is the last component needed to determine the transfer function. The transfer function is the output of the system over the input of the system. Once the transfer function is figured out, the components within the black box are identified to complete the mission. The module is able to communicate this data to visually see the response of the system. Through analysis and basic circuit knowledge the particular components in the black box can be easily identified. This module is useful since it offers real-time sampling and accurate data to determine the output of this mystery circuit.

Results from Integrated System

Integration went pretty smoothly for our full system team. Before trying to analyze the data, we inputted every possible waveform that could be generated by the DAC/Potentiometer subsystems and recorded the data. The outputs of the black box given various 1 Hz sine wave inputs are below:

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Output of 1Vpp, 1 Hz Sine Waveform Input 1.05 Voltage (V) 1 0.95 0.9 0 50 100 150 200 250 Samples (n) Voltage (V) 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n) Output of 4Vpp, 1 Hz Sine Waveform Input

Figure 21: Output of 1Vpp, 1 Hz Sine Waveform Input

Output of 2Vpp, 1 Hz Sine Waveform Input 1 Voltage (V) 0.95 0.9 0.85 0.8 0 50 100 150 200 250 Samples (n)

Figure 24: Output of 4Vpp, 1 Hz Sine Waveform Input

Output of 5Vpp, 1 Hz Sine Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Figure 22: Output of 2Vpp, 1 Hz Sine Waveform Input

Output of 3Vpp, 1 Hz Sine Waveform Input 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n) Voltage (V)

Figure 25: Output of 5Vpp, 1 Hz Sine Waveform Input

Figure 23: Output of 3Vpp, 1 Hz Sine Waveform Input Because PuTTY only saves the most recent 223 lines of text, we couldnt actually save an entire period of the 1 Hz sine waves. This made these plots worth little value. The following plots show the output of the black box given various 10 Hz sine waveforms. These waveforms ended up giving us a lot more insightful information on the inner workings of the black box.

Voltage (V)

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Output of 1Vpp, 10 Hz Sine Waveform Input 1.05 Voltage (V) 1 0.95 0.9 0 50 100 150 200 250 Samples (n) Voltage (V) Output of 4Vpp, 10 Hz Sine Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Figure 26: Output of 1Vpp, 10 Hz Sine Waveform Input

Output of 2Vpp, 10 Hz Sine Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Figure 29: Output of 4Vpp, 10 Hz Sine Waveform Input

Output of 5Vpp, 10 Hz Sine Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Voltage (V)

Figure 27: Output of 2Vpp, 10 Hz Sine Waveform Input

Output of 3Vpp, 10 Hz Sine Wavform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Figure 30: Output of 5Vpp, 10 Hz Sine Waveform Input

Figure 28: Output of 3Vpp, 10 Hz Sine Waveform Input From this data we could clearly see that there was some sort of amplifier circuit in the black box. Using the oscilloscope, we plotted the input and output voltage waveforms together (Figure 31) that the black box is actually inverting the waveform.

Voltage (V)

Votlage (V)

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Figure 31: Oscilloscope Capture of Input/Output Waveform Using this inverting characteristic along with the data from the sine waves, the output voltage was characterized by the following transfer function: V o=1V 0.1Vin This was determined by looking at the minimum and maximum voltages of the output waveform. If the input voltage was 0V, then the output voltage was 1V regardless of the input voltage. If the input voltage was the maximum of the waveform (1V, 2V, 3V, 4V, 5V), we observed the output of the waveform to be 10% of the value (0.1V, 0.2V, 0.3V, 0.4V, 0.5V). A possible circuit to create this transfer function is the differential amplifier circuit below:

Figure 32: Black Box Op-Amp Schematic The resistor values can be derived using the following derivation:

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R3 R4 R1 + R3 )+ V 2 ( )( ) R1 R2 + R4 R1 R 3=0.l R1 R4 V 2( )( 1.1 )=1V R 2+ R 4 Let V 2=15V R4 = 0.606 R2 + R 4 0.606 R4= R =0.0645 R2 10.606 2 V o=V 1 ( Therefore, possible values are: R1=10 k R2=10 k R3=1 k R 4=645 V 1=V in V 2=15V V out =V ( 1 k 645 10 k + 1 k )+ 15 ( )( )=0.1 V in + 1V 10 k 10 k + 645 10 k

The input sine waveforms used do not show all of the characteristics of the circuit, however. The outputs to the input square waveforms reveal that there is more than just a differential amplifier in the black box. Below are the black box responses to input 1 Hz square waveforms:
Output of 1Vpp, 1 Hz Square Waveform Input 1.04 1.02 Voltage (V) 0.98 0.96 0.94 0.92 0.9 0 50 100 150 200 250 Samples (n) Voltage (V) 1 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n) Output of 2Vpp, 1 Hz Square Waveform Input

Figure 33: Output of 1Vpp, 1 Hz Square Waveform Input

Figure 34: Output of 2Vpp, 1 Hz Square Waveform Input

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Output of 3Vpp, 1 Hz Square Waveform Input 1.2 1 Voltage (V) 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n) Voltage (V) 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n) Output of 5Vpp, 1 Hz Square Waveform Input

Figure 35: Output of 3Vpp, 1 Hz Square Waveform Input

Output of 4Vpp, 1 Hz Square Waveform Input 1.2 1 Voltage (V) 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Figure 37: Output of 5Vpp, 1 Hz Square Waveform Input

Figure 36: Output of 4Vpp, 1 Hz Square Waveform Input From the figures above, we can see that there is a rise time associated with each square waveform. Because PuTTY only saves the most recent 223 lines of text, we couldnt actually save an entire period of the 1 Hz square waves. The following plots show the output of the black box given various 10 Hz square waveforms. These waveforms made the RC component of the circuit more obvious.

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Output of 1Vpp, 10 Hz Square Waveform Input 1.05 Voltage (V) 1 0.95 0.9 0 50 100 150 200 250 Samples (n) Voltage (V) Output of 4Vpp, 10 Hz Square Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Figure 38: Output of 1Vpp, 10 Hz Square Waveform Input

Output of 2Vpp, 10 Hz Square Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n) Voltage (V)

Figure 41: Output of 4Vpp, 10 Hz Square Waveform Input

Output of 5Vpp, 10 Hz Square Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n) Voltage (V)

Figure 39: Output of 2Vpp, 10 Hz Square Waveform Input

Output of 3Vpp, 10 Hz Square Waveform Input 1.2 1 0.8 0.6 0.4 0.2 0 0 50 100 150 200 250 Samples (n)

Figure 42: Output of 5Vpp, 10 Hz Square Waveform Input

Figure 40: Output of 3Vpp, 10 Hz Square Waveform Input Using an oscilloscope our system group measured the rise time of the square pulse to be 9.9 ms. In order for the black box to have an RC property, it must have capacitance in the circuit. Our group decided to put a capacitor at the output of the differential amplifier. The updated black box schematic is below:

Voltage (V)

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Figure 43: Black Box Schematic Using a multimeter, we measured the output voltage and current of the black box to determine the output resistance of the op-amp circuit. Using the output resistance of the op-amp along with the time constant, the capacitor value was determined. The derivation is shown below:
= 9.9 ms V out =1.024414V I out =0.05 A V out R= = 20.48 M I out C = / R= 483.2 pF

There are numerous implementations that an input signal could be transformed with the derived transfer function and exhibit an RC characteristic. Our implementation using a differential amplifier and a filtering capacitor is just one.

Discussion
The CAN bus is an effective way to communicate between each subsystem. It requires very little components just a transceiver and a resistor. Although not needed for this project, CAN also allows for very fast data rates. Since CAN is a bus protocol, one user can talk to many different other users at the same time and using the same physical wires. Although CAN was used for this project to communicate between the subsystems, many other protocols could have been used. For example, I2C is another bus protocol that generally uses lower data rates with one master and many slaves. I2C uses slave addresses to differentiate who the master is communicating with. I2C just requires an SDA and SCL line with pull-up resistors. It doesnt require an external transceiver like CAN. SPI is another protocol that could be used for this project. SPI uses MOSI, MISO, and SCL lines to communicate. The master of the system communicates with the multiple slaves by driving the appropriate slaves chip select GPIO line low. Once again, SPI doesnt require an external transceiver unlike CAN. In terms of hardware, I2C requires the least amount of hardware. During integration of our units in our subsystem, we encountered very few problems. One issue we ran

Page 24 into during the testing and integration dealt with writing to the CSV file. After testing some signals from the waveform generator, the waveform we plotted from the CSV file in Excel showed several discontinuities about every 100 samples. We tested several frequencies from the waveform generator and each time this problem was prominent. However, if we copied, pasted, and plotted the sample data from PuTTY, the output waveform had no discontinuities. Therefore, there must have been an issue with writing to the CSV file. We investigated the issue and found that the fprintf does not actually write directly to the file system; it writes to a write buffer. The write buffer is flushed by filling up the buffer or by manually flushing it. When the write buffer is flushed and the data is actually written to a file, there is a delay in the code which causes the jump discontinuity seen in the data in Test ABC.1. To avoid this problem, we tried manually flushing the buffer after each write to the buffer. This eliminated the discontinuities but at the expense of lowering the sampling rate to less than 100 Hz. The reason that this problem doesnt show up in PuTTY is because the printf write buffer is much longer than the fprintf buffer and also automatically flushes on \n characters. If we had to complete this lab again, we would not change that much regarding the organization of our group. One thing that would have benefitted us this time around would have been to get together with every group before diving into our subsystems. We could have discussed each others initial plans and the testing procedures for integration. The keypad commands would have been initialized so that each group knows which commands to be looking for to initiate tasks. While the lab went really smoothly, it would have been better to communicate early on with all groups to set the expectations for the system of subsystems.

Value Statement
The end product of this laboratory project is a very applicable and useful device. The full system our team created is a scaled down signal generator and oscilloscope controlled by a keypad that can be used to test circuitry and characterize other black box devices. This is a very low cost test -bench set-up that can be used if funds are insufficient for the full featured instruments or when in the field. Instead of lugging around two expensive, fragile devices, you can just bring this system that runs on USB and will do the rudimentary tasks of a function generator and oscilloscope. If you then paired this system with MATLAB, you could potentially have a basic spectrum analyzer as well, along with many other tools that MATLAB provides. Of the three projects we did this semester in the EE 300W laboratory component, this project is the most useful and valuable.

Conclusion
In conclusion, this laboratory project created a full system that can generate analog waveforms and sample an analog waveform by using a keypad control. Specifically, our subsystem was responsible for sampling and recording the input analog waveform. The subsystem uses an ADC to sample and quantize the input and an mbed microcontroller to collect and store the data to a CSV file and print it to a serial terminal. The mbed along with a CAN transceiver are used to parse messages over the system CAN bus for commands to start/stop sampling and close the CSV file. This project created a low cost, basic signal generator and oscilloscope that can be used for simple projects or in the field where bringing these expensive, fragile instruments may be infeasible. The issues our subsystem faced ended up helping us more deeply understand what we were coding and building, specifically the fprintf write buffer issue. In the future, our subsystem could be improved by making some design changes. For our subsystem,

Page 25 an external data logger could be used so that the mbed doesnt have to collect the data from the ADC and write the data to the filesystem. When the mbed collects the data from the ADC, it would send the data straight to the data logger, which would asynchronously write it to a file. This would eliminate the issue of jump discontinuities or manually flushing the write buffer. Furthermore, if we need a higher resolution ADC, the subsystem should use a 16 bit ADC. From a system perspective, the end product could be improved by implementing more outputted waveforms, such as triangle and ramp waveforms. Additionally, the user should be able to choose from a larger array of waveform frequency values. This would greatly increase the usefulness of this system. The potentiometer group could allow for a larger range of waveform amplitudes, rather than just integer values from 0V to 5V. Finally, an LCD screen could be added to the system that could display the current output configuration and input sampling status. This would make the system easier to use, and the user would be less prone to errors.

Appendix
Product mbed ADS1015 MCP2551 120 Resistor 10 k Resistor Unit Price ($) 64.00 9.95 1.22 0.10 0.10 Quantity 1 1 1 1 2 Total Cost ($) 64.00 9.95 1.22 0.10 0.20 Vendor Digi-Key Adafruit Digi-Key Digi-Key Digi-Key

Table 2: Bill of Materials