Published in IET Microwaves, Antennas & Propagation

Received on 12th May 2009

Revised on 8th July 2010
doi: 10.1049/iet-map.2009.0292
ISSN 1751-8725
0.56 GHz low-voltage low-power mixer
using a modied cascode topology
in 0.18 mm CMOS technology
K.-H. Liang H.-Y. Chang
Department of Electrical Engineering, National Central University, Jhongli, Taoyuan, 32001, Taiwan
E-mail: hychang@ee.ncu.edu.tw
Abstract: A broadband low-voltage low-power down-conversion mixer using a 0.18 mm standard CMOS process is
presented. The proposed mixer uses a modied cascode topology with a bulk-injection technique to achieve low-
voltage and low-power performance. The mixer features a maximum conversion gain of 6 dB at a radio frequency
(RF) of 2.4 GHz, a single-sideband (SSB) noise gure of 15.2 dB, and an input third-order intercept point (IIP3) of
0 dBm. Moreover, the chip area of the mixer core is only 0.15 0.23 mm
2
. The measured 3 dB RF bandwidth is
from 0.5 to 6 GHz with an intermediate frequency (IF) of 100 MHz. The optimum DC supply voltage (V
DD
) can be
scaled down to 0.7 V with a drain current within 0.4 mA. The supply voltage and DC power of this circuit can be
compatible with an advanced 90 or 65 nm CMOS technology.
1 Introduction
CMOS technology down-scaling yields an increase of
operating speed and a reduction of power consumption
and area for integrated circuits [1]. Low-cost CMOS
technology is benecial for integrating broadband
communication transceivers in a single chip. The low-
voltage and low-power design issues are crucial for mobile
wireless communication systems because of the limitation
of battery capacity, and therefore the volume and weight of
transceivers can be further reduced using low-voltage low-
power techniques.
A mixer is an essential component for wireless transceivers.
In general, Gilbert-cell mixers are widely used as down-
converters in CMOS transceivers, since they are broadband
with good conversion gain [2, 3]. Owing to the stacked
structure in a Gilbert-cell mixer, low-voltage applications
are limited to voltage drops across the load resistors and the
local-oscillator (LO) switching stage [3]. Recently, a few
low-voltage and low-power operation topologies using
CMOS technologies have been proposed in [412] for
radio frequency (RF) mixer circuits. Inductor capacitor
tanks are used to achieve low-power operation in [4], but
the inductor occupies a relatively large area on the chip.
A transformer-based architecture is adopted to reduce DC
power consumption in [6], but the 3 dB bandwidth is quite
narrow because of the bandwidth limitation of the
transformer. Folded and switched-transconductance mixers
were published in [810]; they demonstrated low-voltage
operation but consumed more DC current. Active mixers
were also reported using advanced GaAs HBT [1315],
HEMT [16] or InP HBT [17], HEMT [18] technologies,
but the DC power consumptions of these is usually higher
than 100 mW because of the monolithic microwave
integrated circuit (MMIC) processes and the circuit
topologies used. The conventional Gilbert-cell topology can
be employed to achieve high gain [1315, 17], but the
noise gure is usually up to 10 dB because of the
transconductance stage of the Gilbert-cell mixer. To
achieve broad bandwidth, a distributed topology can be
adopted for mixer design [16, 18]. However, distributed
mixers consume large DC power with conversion loss.
Here, we propose a modied bulk-injection cascode mixer
to achieve low-voltage and low-power operation. In the mixer
design, the RF stage is stacked upon the LO stage to reduce
voltage drops for low-voltage operation. The bulk-injection
technique is used to modulate the threshold voltage of the
LO stage. The mixer can be operated in ultra low DC
IET Microw. Antennas Propag., 2011, Vol. 5, Iss. 2, pp. 167174 167
doi: 10.1049/iet-map.2009.0292 & The Institution of Engineering and Technology 2011
www.ietdl.org
power consumption. In addition, comparing with a previously
reported bulk-injection mixer [12], the isolation between
the RF and LO ports of this work is improved signicantly
because of the proposed cascode conguration.
This paper is organised as follows. In Section 2, we
describe the mixer core and the working principle of the
mixer. In Section 3, the complete mixer schematic will be
shown along with the design details. Insight into the mixer
operation is given by analysing conversion gain, linearity
and isolation. In Section 4, the experimental results of the
fabricated mixer will be given. In Section 5, the conclusions
and performance benchmarks are summarised.
2 Mixer core and operating
principle
The schematic of the mixer core is shown in Fig. 1a, which
consists of an LO switch stage (M
1
), an RF
transconductance ( g
m
) stage (M
2
) and a PMOS transistor
(M
3
) as an active load. The corresponding functional
model is illustrated in Fig. 1b. The RF stage performs as a
voltage-to-current converter, which is essentially biased in
the active region to achieve high-conversion gain with low
noise gure. The LO switch stage is designed as two
functions, a switching function and a current-steering
function. The gate voltage V
G
of the LO stage is biased
below the threshold voltage (V
TH
), where the V
TH
is about
0.5 V in the 0.18 mm CMOS process. Since the threshold
voltage (V
TH
) of the transistor is a function of the voltage
between bulk and source (V
BS
), the threshold voltage can
be represented as
V
TH
(LO) = V
T0
+g

2f
F
V
BS
(LO)

2f
F

(1)
where V
T0
is the zero substrate bias threshold voltage, f
F
is
the surface potential and g is the body effect factor. The
LO signal as a function of bulk-to-source voltage is
injected into the bulk of the transistors, and then the
threshold voltage is modulated with the LO signals [12].
Fig. 2 illustrates the threshold voltage as it varies from
0.3 to 0.6 V with a 0 dBm sine wave LO signal. The
device is turned on or off alternately as the LO signal is on
a positive or negative cycle. Hence, the switching
mechanism of the mixer is achieved by the LO-controlled
threshold voltage. In Fig. 1a the bottom transistor (i.e. M
1
)
of the mixer core is biased at 0.45 V, which is below 0.5 V
(V
T0
). Therefore the switching stage is nearly in the turn-
off condition with almost no DC current through the
mixer core. The low power performance of the proposed
mixer core is accomplished in this bias condition. The high
output impedances PMOS transistors are used as an active
load to transfer current to voltage for the intermediate
frequency (IF) output signals. The cascode connection
mixer core is composed of two NMOS transistors with the
same size. Corresponding to different bias conditions, there
are three possible operation modes for the upper and lower
transistors, including linear active, activeactive and
activelinear modes. The activelinear mode is the
optimum operation for this design, and the mixer will
achieve high conversion gain with low noise gure in this
mode. In addition, the linearity of the mixer is good
because of the lower transistor being used as a degeneration
resistor [19]. Moreover, the cascode structure provides good
inherent LO-to-RF isolation as compared with the single-
gate bulk-injection topology [12].
3 Mixer structure and
performance analysis
The complete schematic diagram of the proposed mixer is
shown in Fig. 3, and a doubly balanced structure is used to
enhance the port-to-port isolations. The four major parts
of the mixer are the LO switching stage (M
1
M
4
), the RF
transconductance stage (M
5
M
8
), the PMOS transistors
(M
9
M
10
) in use as active loads and the output buffers
(M
11
M
12
). The NMOS device sizes of the cascode
connection (M
1
M
8
) are all ten-nger with a total gate
width of 25 mm. The PMOS transistors (M
9
M
10
) with a
total gate width of 22 mm are biased in the active region as
Figure 1 Schematic of the bulk-injection cascode Mixer
a Single-ended mixer core
b Functional representation
Figure 2 LO-controlled threshold voltage realised switching
mechanism
168 IET Microw. Antennas Propag., 2011, Vol. 5, Iss. 2, pp. 167174
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-map.2009.0292
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load resistors. The output buffers (M
11
M
12
) with a total
gate width of 200 mm are used to achieve the impedance
matching for driving 50 V loads. The three stacked levels
of transistors (M
1
, M
5
and M
9
) are operated in the linear,
active and active regions with drain-to-source voltages of
50, 425 and 225 mV, respectively. Therefore the supply
voltage of the mixer is only 0.7 V with a 0.3 mA drain
current. The output buffers consume only 0.1 mA DC
current because the gate bias is smaller than the threshold
voltage. The DC voltage at the node a is only 475 mV. A
more detailed analysis of the circuit design is given below.
The analysis of this circuit focuses on conversion gain,
linearity and port-to-port isolations.
3.1 Conversion gain
According to the small signal equivalent circuit of the
NMOS device, a simple embodiment of the proposed
mixer is shown in Fig. 4. The input RF signal is amplied
by a common-source transistor with a source degeneration
resistance r
on
and a output load r
op
. Hence, the small-
signal voltage gain G
V
can be derived as
G
V
=
g
m
r
op-active
1 +g
m
r
on-linear
+(r
on-linear
/r
on-active
)
(2)
where r
on
and r
op
are the output resistance of the NMOS and
PMOS transistors, respectively. The sufx of linear and
active denotes the operating region of the transistor. Since
r
o-active
is greater then r
o-linear
, the switching transistor
should be biased in the linear region. The output active
load needs to be biased in the active region to optimise the
small-signal gain. In Fig. 3, the differential RF currents are
associated with the transconductances ( g
m5
g
m8
) and the
RF input signal (y
RF
1/2 A
RF
cos(v
RF
t)) [10]. Assuming
that the LO voltage is an ideal square wave, the IF
generated signal can be expressed as
i
IF7,8
(t) = g
m7,8
A
RF
cos(v
IF
t) and (3)
i
IF5,6
(t) = g
m5,6
A
RF
cos(v
IF
t) (4)
where v
IF
is the IF angular frequency(v
RF
v
LO
). Assuming
the transconductance of M
5
, M
6
, M
7
and M
8
are all
identical, the overall differential IF output voltage can
therefore be expressed as
y
IF
(t) =
g
m
r
op-active
1 +g
m
r
on-linear
+(r
on-linear
/r
on-active
)
A
RF
cos(v
IF
t)
(5)
Thus, the voltage conversion gain of the proposed mixer can
be expressed as
CG =
2
p
g
m
r
op-active
1 +g
m
r
on-linear
+(r
on-linear
/r
on-active
)
(6)
To simplify the expression of the conversion gain, we assume
that
g
m
r
on-linear
1 and g
m
r
on-linear
r
on-linear
/r
on-active
(7)
Hence (6) can be approximated by
CG
2
p
r
op-active
r
on-linear
(8)
From (8), we see that the conversion gain is proportional to
the output resistance ratio of the active-load PMOS
transistor to the switching stage NMOS transistor. The
output resistance of the switching stage and the active-load
transistors against the drain-to-source voltage is plotted in
Fig. 5. In this design, the output resistance of the
switching stage and the active load is 220 and 1600 V,
respectively. The calculated power conversion gain is
approximately 5.5 dB from (8), and the result is close to
the experimental result of 6 dB. For optimum conversion
gain, the switching transistor is operated in the linear
region to reduce the output resistance. Therefore the active
load should be biased in the active region to increase the
output resistance. Since the voltage drop cross the active
load is proportional to the output resistance, the optimum
bias point is near the triode region to ensure the RF stage
is in the active region. In addition, the voltage drop should
be chosen as a tradeoff between the active load and the
transconductance stage.
Figure 4 Small-signal equivalent circuit of the source-
degenerated common-source amplier
Figure 3 Schematic of the proposed mixer
IET Microw. Antennas Propag., 2011, Vol. 5, Iss. 2, pp. 167174 169
doi: 10.1049/iet-map.2009.0292 & The Institution of Engineering and Technology 2011
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3.2 Linearity
In general, the distortion of an active mixer is dominated by
the non-linearity of the transconductance stage. For the
normal operation of the proposed mixer, the equivalent
circuit is as shown in Fig. 4, which is composed of a
common-source amplier and a source degeneration
resistor. The transconductance of the device with a source
degeneration resistor can be derived as
G
m
=
g
m
1 +g
m
r
on-linear
+(r
on-linear
/r
on-active
)
(9)
where g
m
is the transconductance of the common-source
transistor. The linearity can be improved by introducing a
source degeneration resistor but the conversion gain of the
mixer is decreased (i.e. g
m
greater than G
m
). Therefore the
linearity should be a tradeoff between the conversion gain
and the DC power consumption. In order to verify the
analysis for conversion gain, noise gure and linearity, the
experimental data are summarised in Table 1. In the rst
case, with a DC supply voltage of 0.65 V, the switching
stage, the transconductance stage and the active load are
operated in the linear, linear and active regions,
respectively. The conversion gain is obviously reduced
because of the transconductance stage operating in the
linear region (V
DS
55 mV). The optimum design for
circuit performance is biased with a DC supply voltage of
0.7 V. The operating conditions of the three stacked
transistors are linear, active and active regions, respectively.
In the last case, the supply voltage is 0.75 V and the
devices are operated in the linear, active and linear regions,
respectively. From (6), the value of the denominator g
m
r
op-linear
is smaller than g
m
r
op-active
and therefore the conversion gain
is low. Since r
op-active
is greater then r
op-linear
, the
conversion gain is increased by 2 dB for the optimum design.
3.3 Isolation
The cascode topology is proposed to further improve the
isolation between the LO and RF ports of the previously
reported bulk-injection mixer [12]. Fig. 6 shows the device
Figure 7 Comparison of the measured RF-to-LO and LO-to-RF
isolations at 3 dB bandwidth frequency with a LO power of
0 dBm
Table 1 Design principle and experimental results of the proposed mixer
V
DS
, mV
(SW+G
m
+load)
a
Operation region (SWG
m
load) Conversion gain,
dB
Mixer current,
mA
Noise gure,
dB
IIP3,
dBm
650 (37 +55 +558) linearitylinearityactive 228 305 32.5
700 (50 +425 +225) linearityactiveactive 6 400 15.2 0
750 (58 +577 +115) linearityactivelinearity 4.2 425 16.4 2
a
Switch stage, transconductance stage and active load
Figure 6 Cross-section of the bulk-injection single-ended
mixer and the signal leakage path
Figure 5 Output resistance of the switching stage and the
active load transistors against the drain-to-source voltage
170 IET Microw. Antennas Propag., 2011, Vol. 5, Iss. 2, pp. 167174
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-map.2009.0292
www.ietdl.org
cross-section of a single-ended bulk-injection mixer. The RF
and LO ports are isolated using only a p-well, and the signals
directly couple with each other. Therefore the isolation
between RF and LO ports cannot be maintained at a
sufciently high level at high frequencies. Hence, the
cascode conguration is utilised to increase the port-to-port
isolations of the mixer. Fig. 7 compares the measured
RF-to-LO and LO-to-RF isolations of the single-gate
mixer [12] and the proposed cascode mixer. The
improvement is higher than 15 dB and the proposed mixer
features an isolation of better than 40 dB over the 3 dB RF
bandwidth.
4 Experimental results
of the mixer
The above mixer concept has been realised using a TSMC
0.18 mm CMOS standard bulk process. Fig. 8 shows
the chip photograph of the mixer with a chip area of
150 230 mm
2
. The chip was measured via on-wafer
probing with groundsignal groundsignal ground
(GSGSG) probes in RF and LO input ports. The RF
bandwidth was measured using off-chip broadband baluns.
The IF output differential signals were connected to a
spectrum analyser through two off-chip DC blocking
capacitors. The measured and simulated conversion gains
against LO power are plotted in Fig. 9, which shows a
Figure 11 Measured and simulated SSB noise gure
against RF frequency
Figure 12 Measured and simulated conversion gain against
RF frequency
Figure 8 Chip photo of the mixer with a core area of
150 230 mm
2
Figure 9 Measured and simulated conversion gains against
LO Power
Figure 10 Measured IIP
3
with a RF input frequency spacing
of 10 MHz and a DC supply voltage of 0.7 V
IET Microw. Antennas Propag., 2011, Vol. 5, Iss. 2, pp. 167174 171
doi: 10.1049/iet-map.2009.0292 & The Institution of Engineering and Technology 2011
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conversion gain of 6.2 dB with an LO power of 0 dBm. At an
RF frequency of 2.4 GHz, the measured third-order
intermodulation with a frequency spacing of 10 MHz is
plotted in Fig. 10 for the proposed mixer, which features
an input third-order intercept point (IIP3) of 0 dBm, and
an input 1 dB compression point (P
1dB
) of greater than
210 dBm. The measured and simulated single-sideband
(SSB) noise gures against RF frequency from 0.5 to
6 GHz are plotted in Fig. 11 where the IF frequency is
xed at 100 MHz. The measured SSB noise gure is
15.2 dB when the RF frequency is 2.5 GHz with an LO
power of 0 dBm. The measured and simulated conversion
gains against RF frequency from 0.5 to 6 GHz are plotted
in Fig. 12, which shows a measured RF bandwidth of
5.5 GHz. The measured RF port input return loss is about
3 dB over the bandwidth, and the input match of the RF
port is not good since no matching network is employed at
Figure 13 Benchmarks of recently reported low-voltage
low-power CMOS mixers and this work
Table 2 Comparisons of previously reported mixers and this work
Reference Process Approach RF 3 dB
frequency, GHz
NF,
dB
Gain,
dB
IIP3,
dBm
Power consumption,
(mW)/V
DD
(V)
FOM,
dB
[5] 0.18 mm
CMOS
passive 2.45 16 13.3
a
21 7.2/1.8 6.6
[6] 0.13 mm
CMOS
transformer-
based
2.13 14.8 5.4 22.8 1.6/0.6 9.45
[8] 0.18 mm
CMOS
folded-cascode 5.25 24.5 8.3 0.03 4.95/0.9 22.3
[9] 0.18 mm
CMOS
folded-switching 2.4 12.9 15.7
a
1 8.1/1.8 11.3
[10] 0.18 mm
CMOS
switched G
m
0.34 14 11
a
4.1 6.6/1 10.3
[11] 0.18 mm
CMOS
bias-offset 8 11 6.5 3.5 6.9/1 10.6
[12] 0.18 mm
CMOS
bulk-injection 0.57.5 15 5.7 25.7 0.48/0.77 13.2
[13] GaAs HBT Gilbert cell DC 10 9 1 90/9
[14] GaAs HBT Gilbert cell 117 9.3 6 148/5.6
[15] GaAs HBT Gilbert
micromixer
DC 8 11 27 2/5
[16] GaAs
PHEMT
distributed drain
mixer
333 24 10 77/1.1
[17] InP HBT Gilbert cell DC 15 23.9 9 1000/10
[18] InP HEMT distributed
Gilbert cell
DC 38 25 2500/-
this work 0.18 mm
CMOS
cascode bulk-
injection
0.56 15.2 6 0 0.28/0.7 18.3
a
Voltage conversion gain
172 IET Microw. Antennas Propag., 2011, Vol. 5, Iss. 2, pp. 167174
& The Institution of Engineering and Technology 2011 doi: 10.1049/iet-map.2009.0292
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the input port in order to minimise the chip area. The
optimum DC supply voltage (V
DD
) is 0.7 V with a drain
current of 0.4 mA. The dynamic current is within 0.4 mA.
The supply voltage and consuming DC power of the
proposed mixer are compatible with a 65 nm CMOS
technology. The performance of proposed mixer can be
evaluated using a gure of merit (FOM) which is dened
as following [9]
FOM= 10 log
10
G/20
10
(IIP310)/20
10
NF/10
P

(13)
where G and NF represent the conversion gain and noise
gure in dB, respectively. The DC power consumption
(P) and IIP3 are expressed by W and dBm, respectively.
The benchmarks of recently reported low-voltage low-
power mixers and this work are plotted in Fig. 13. To the
best of the authors knowledge, this work demonstrates
the highest FOM of 18.3 dB with broadband 3 dB RF
bandwidth among all the reported mixers in CMOS
processes.
5 Conclusions
A broadband low-voltage low-power mixer is presented. A
modied cascode topology with a bulk-injection technique is
proposed to achieve the low-voltage and low-power
performance with competitive conversion gain and good
port-to-port isolations. A switch stage is used as a current-
steering device as well as a source degeneration resistor for the
linearity improvement. In order to evaluate the performance
of the proposed mixer, the previously reported CMOS mixers
and this work are compared in Table 2. This work represents
the widest 3 dB bandwidth and the highest FOM among all
reported mixers in CMOS processes. For the demands of
modern wireless communications, such as wireless local area
network and mobile phone, this RF mixer is suitable as a
building block in low-voltage and low-power transceiver
design owing to its superior performance.
6 Acknowledgments
This work was supported in part by the National Science
Council of Taiwan, R.O.C., under Grant NSC 96-2221-
E-008-117-MY3, and Grant NSC 99-2221-E-008-097-MY3.
The authors thank the staff of TSMC and the Chip
Implementation Center (CIC), Hsinchu, Taiwan, R.O.C.,
for fabricating this chip.
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