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CS2071_Computer Architecture
I.INTRODUCTION TO COMPUTER ARCHITECTURE
1. Why we study computer architecture?
The purposes of studying architecture are
To gain knowledge about designing / building a new computer
To gain knowledge about designing / building a new version of computer
To improve software performance
To find solution with embedded computer system
To purchase a new computer
2. History of computer
Generation Processor Memory I/O devices introduced Dominant look & fell
technology innovations
0 (1600s) (Electro)- mechanical Wheel, card Lever, dial, punched card Factory equipment
1 (1950s) Vacuum tube Magnetic drum Paper tape, magnetic tape Hall-size cabinet
64kb
kIPS kb
1980 1990 2000 2010
Calendar year
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CS2071_Computer Architecture
3. Basic units of a digital computer:
1. Input unit
2.
Arithmetic & logic unit
3. Data path & Control CPU (central processing unit)} Control Input
S o ftw a r e H a rd w a re
Electronic components
Applicati on domai ns
Applicati on designer
Computer designer
System designer
Circuit designer
Logic designer
H ig h - Low -
le ve l C o m p u t e r a rc h i t e c tu r e le ve l
v ie w v ie w
C o m p u t e r o r g a n iz a tio n
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CS2071_Computer Architecture
5. COMPUTER ARCHITECTURE & COMPUTER ORGANIZATION
Computer organization:
Computer organization deals with operational units and interconnections that realize computer architectural
specifications.
Architectural specifications refers to control signal, interface between computers, interface between CPU,
memory, input/output peripherals.
Microarchitecture, also known as Computer organization is a lower level, a detailed description of the system
that is sufficient for completely describing the operation of all parts of the computing system, and how they are
inter-connected and inter-operate in order to implement the ISA.
Computer architecture:
Computer Architecture is an area of study that deals with the computer at the interface between hardware and
software.
Computer Architecture deals with the structure and behavior of a computer including the information formats.
Computer Architecture encompasses a set of ideas that are applicable to design or understand any computer
virtually from tiniest embedded microprocessors to most powerful supercomputers
Computer architecture is more hardware oriented than computer systems.
AC - Accumulator
MQ – multiplier quotient
MBR (DR) – memory buffer register /
data register
IBR – instruction buffer register
PC – program counter
IR – instruction register
MAR (AR) – memory address register
Fig.3. Expanded model of von Neumann architecture or IAS (Institute For Advance Studies) computer
MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced instruction
set computer (RISC) instruction set architecture (ISA) developed by MIPS Technologies (formerly MIPS
Computer Systems, Inc.).
The early MIPS architectures were 32-bit, with 64-bit versions added later. Multiple revisions of the MIPS
instruction set exist, including MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64.
The current revisions are MIPS32 (for 32-bit implementations) and MIPS64 (for 64-bit implementations). MIPS32
and MIPS64 define a control register set as well as the instruction set.
Fig.4.
The first commercial MIPS model, the R2000, was announced in 1985. It added multiple-cycle multiply and
divide instructions in independent on-chip unit.
New instructions were added to retrieve the results from this unit back to the register file and these result-
retrieving instructions were interlocked.
It had thirty-one 32-bit general purpose registers, but no condition code register. Unlike other registers, the
program counter is not directly accessible. The R2000 could be booted either big-endian or little-endian.
The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled
exceptions, traps and memory management, while the other three were left for other uses. One of these could be
filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit
registers for double-precision.
MIPSel refers to a MIPS architecture using a little endian byte order. Since almost all MIPS microprocessors have
the capability of operating with either little endian or big endian byte order, the term is used only for processors
where little endian byte order has been pre-determined.
7. b. MEMORY AND PROCESSING SUBSYSTEMS FOR miniMIPS.
...
Loc 0 Loc 4 Loc 8 m 2 32
4 B / location Memory
up to 2 30words Loc Loc
m 8 m 4
...
$31 $31
Integer FP
ALU
mul/div arith
Hi Lo
TMU BadVaddr Trap &
(Coproc. 0) Status memory
Cause unit
Design of mul & divide EPC
Data size
In miniMIPS, there are 3 datasize as follows,
1. Byte –8 bits
2. Word – 4 bytes (32 bits)
3. Double word – 8 bytes (64 bits)
word
In computer architecture, word can be defined as a 32-bit data element stored in a register or memory
location with an address.
A word is a unit of data of a defined bit length (32 bit in miniMIPS) that can be addressed and moved
between storage and the computer processor.
A word can hold
Instruction
Signed integer
Unsigned integer
Floating point number
Strings of ASCII characters
ord length
Word length is defined as the total number of bits used to represent. In general 1 word equals 32 bits.
Usually, the defined bit length of a word is equivalent to the width of the computer's data bus so that a word
can be moved in a single operation from storage to a processor register.
For any computer architecture with an eight-bit byte, the word will be some multiple of eight bits.
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CS2071_Computer Architecture
Byte Addressability:
Byte Addressability is used for assigning successive memory address to successive memory location. This
type of assigning is used in modern computers.
One byte=8 bits. Example:32bits Address:0,4,8....
Bid-Endian format
The name big-Endian is used when lower byte addresses are used for the most significant bytes (the left most
bytes) of the word. (most significant byte has lowest address)
Data types
S.no. Data types Datasize
1 Signed integer byte word -
2 Unsigned integer byte word -
3 Floating point number - word doubleword
4 Bit string byte word doubleword
Example:
Type 8-bit number Value32-bit version of the number
Unsigned 0010 1011 43 0000 0000 0000 0000 0000 0000 0010 1011
Unsigned 1010 1011 171 0000 0000 0000 0000 0000 0000 1010 1011
Signed 0010 1011 +43 0000 0000 0000 0000 0000 0000 0010 1011
Signed 1010 1011 –85 1111 1111 1111 1111 1111 1111 1010 1011
V e ry H ig h- le ve l A s se m b ly M a c hi ne
hig h -le ve l la ng ua g e la ng ua g e la ng ua g e
la ng ua g e s ta te m e n ts instr uc tio ns , ins tr uc tio ns ,
o b je c tive s m ne m o nic b ina r y ( he x)
Assembler
Interpreter
Compiler
o r ta s k s
Machine lan gua ge ins truction: 00 000 0 10 010 100 01 1100 0 0 0000 10 0000
A LU-ty pe Regis ter Regis ter Regis ter A ddition
ins truc tion 18 17 24 Unus ed opc ode
P $17 A LU
C $18
$24
2. INSTRUCTION SET ARCHITECTURE (ISA) & INSTRUCTION SET DESIGN AND EVOLUTION:
Ins truction-s et
definition
New Im ple-
m achine m en-
Pro- project tation Fabrica- Sales
cessor Performance tion & &
design objectives tes ting use
team
?
Tuning &
bug fixes
Feedback
Combination of instruction set, parts of machine, its functionality will produce correct, compact, fast programs.
The instruction set / instruction set architecture we are going to discuss is instruction set of miniMIPS
Mini- minimal, MIPS – microprocessor without interlocked pipeline stages.
Registers, memory location (data storage), machine instruction are concerned by the complier and assembly
programmer.
Machine instruction:
Machine instruction typically contains
an opcode
one or more source operands
possibly a destination operand
Opcode:
An opcode (operational code) is a binary code or bit pattern that defines an operation.
An opcode (operation code) is the portion of a machine language instruction that specifies the
operation to be performed.
Example: opcode for Addition operation is 32 100010 in binary
Operand
In computer programming languages, the definitions of operator and operand are almost the same.
In computing, an operand is the part of a computer instruction which specifies what data is to be
manipulated or operated on, whilst at the same time representing the data itself.
In assembly language, an operand is a value (an argument) on which the instruction, named by
mnemonic, operates. The operand may be a processor register, a memory address, a literal constant,
or a label.
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CS2071_Computer Architecture
Classification of instruction sets.
A complex instruction set computer (CISC) has many specialized instructions, which may only be rarely
used in practical programs.
A reduced instruction set computer (RISC) simplifies the processor by only implementing instructions
that are frequently used in programs; unusual operations are implemented as subroutines, where the extra
processor execution time is offset by their rare use.
Theoretically important types are the minimal instruction set computer (MISC) and the one instruction
set computer (IISC) but these are not implemented in commercial processors.
Another variation is the very long instruction word (VLIW) where the processor receives many
instructions encoded and retrieved in one instruction word.
Simplicity and uniformity of instruction formats is common in modern RISC designs that aim to execute the most
commonly used operations as fast as possible at less expense.
There are 3 instruction formats in miniMIPS. They are
Register
Immediate
Jump
Fn- (Opcode extension) function field serves as an extension of opcode, to allow more than one operations to be
defined.
Sh – (Shift amount) field is used in instructions that specify a constant shift amount
Example: sll $t0, $s1, 2 ---- this value 2 will be specified in “sh” field
$to = ($s1) left –shifted by 2
4.INSTRUCTION TYPES
ARITHMETIC INSTRUCTIONS:
Arithmetic instructions follow R-format and I-format instruction.
The arithmetic instructions ADD and SUB have a format that is common to all two-operand ALU instructions.
For these, the fn field specifies the arithmetic/logic operation to be performed.
op rs rt rd sh fn
add $t0,$s0,$s1 # set $t0 = ($s0)+($s1) 31 25 20 15 10 5 0
op rs rt o p e ra n d / o ffs et
31 25 20 15 0
Instructions such as addi allow us to perform an arithmetic or logic operation for which one operand is a small
constant
o When used as immediate operand:
Holds an integer that is constant throughout the operation
Works same as rt in register format
Example: addi t0, s0, 61 (to = rt, s0 = rs and Operand = 61), Therefore, t0 = (s0) + 61
Operand field is only 16 bits long.
So the valid range is (-32768 to 32767) for signed integer and
[0 x 0000, 0x ffff] for hexadecimal contants
There is no SUBI instructions, but it can be accomplished by adding a negative value.
miniMIPS has a 32-bit adder and all inputs should be 32 bit long. So, the 16-bit immediate operand must be
converted to 32-bit value before it is given as input to adder. This is done by SE (sign extenion) by taking 2’s
Multiply & Divide instruction:
op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 x 0
ALU Source Source Unused Unused mult = 24
instruction register 1 register 2 di v = 26
mfhi and mflo instructions: MiniMIPS instructions for copying the contents of Hi and Lo registers into general
registers op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 x 0
ALU Unused Unused Destination Unused mfhi = 16
instruction register mflo = 18
LOGIC INSTRUCTIONS:
Logic instructions operate on a pair of operands on a bit-by-bit basis
The key difference between andi, ori, xori and addi is that 16-bit operand of a logical instruction is 0-
extended from left to turn it into 32-bit format for processing.
LOGICAL SHIFTS:
op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 x 0
ALU Unused Source Destination Shift sll = 0
instruction register register amount srl = 2
op rs rt rd sh fn
31 25 20 15 10 5 0
R 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 x 0
ALU Amount Source Destination Unused sllv = 4
instruction register register register srl v = 6
LOAD AND STORE INSTRUCTIONS:
lui $s0,61 # The immediate value 61 is loaded in upper half of $s0 with lower 16 bit set to 0’s
op rs rt operand / offset
31 25 20 15 0
I 0 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
lui = 15 Unused Destination
Imm ediate operand
0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Load and store instructions for byte-size data elements.
o Bytes can be used to store ASCII characters or small integers.
o MiniMIPS addresses refer to bytes, but registers hold words.
lb $t0,8($s3) # load rt with mem[8+($s3)] and sign-extend to fill reg
lbu $t0,8($s3) # load rt with mem[8+($s3)] and zero-extend to fill reg
sb $t0,A($s3) # LSB of rt to mem[A+($s3)]
op rs rt immediate / offset
31 25 20 15 0
I 1 0 x x 0 0 1 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0
lb = 32 Base Data Address offset
lbu = 36 register register
sb = 40
x x x x 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
From PC
Effecti ve tar get address (32 bits)
BRANCH INSTRUCTIONS:
Conditional branch instructions allow us to transfer control to given address when a condition of interest is met.
bltz $s1,L # branch on ($s1)< 0 (branch when less than zero)
op rs rt operand / offset
31 25 20 15 0
I 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1
bltz = 1 Source Zero Relative branch distance in words
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CS2071_Computer Architecture
6. PSEUDO-INSTRUCTION
Pseudoinstructions allow us to formulate computations and decisions in alternative forms that are
not directly supported by hardware .
MiniMIPS assembler takes care of translating these alternative forms to basic form that is supported
by existing hardware instruction (hardware supported instruction).
Some pseudo instruction should be replaced by one or more than one instruction .
Pseudoinstruction are predefined, fixed, and look like machine instructions
o Example of One-To-One Pseudoinstruction:
Write a macro to determine the largest of three values in registers and to put the result in a fourth register.
Solution:
.macro mx3r(m,a1,a2,a3) # macro and arguments named
move m,a1 # assume (a1) is largest; m = (a1)
bge m,a2,+4 # if (a2) is not larger, ignore it
move m,a2 # else set m = (a2)
bge m,a3,+4 # if (a3) is not larger, ignore it
move m,a3 # else set m = (a3)
.endmacro # macro terminator
If the macro is used as mx3r($t0,$s0,$s4,$s3), the assembler replaces the arguments m, a1, a2, a3 with $t0, $s0, $s4,
$s3, respectively.
III. ADDRESSING and ADDRESSING MODES.
1. ADDRESSING:
Addressing is the method by which location of an operand is specified within an instruction.
Extend,
Imm ediate if required
Constant offset Me m
Base
Reg Add addr Me m
Reg base Reg f ile Me mory
data data
Constant offset
PC-relative Me m
Add addr Me m
Me mory data
PC
Pseudodirect PC Me m
addr Me mory Me m
data
Fig.10. Addressing modes
4. Base addressing
Operand is stored in memory and the corresponding memory location is computed by adding an offset
(16-bit signed integer) with content of specified base register.
Example:
5. PC-Relative addressing.
Operand is stored in memory and the corresponding memory location is computed by adding an offset
(16-bit signed integer) with content of program counter.
Here the offset is appended with 2 0’s at the right end.
Example:
o bltz $s1, imm [imm + content of program counetr] gives the memory location.
x x x x 0 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
F ro m P C
E ff e c t i ve ta r g e t a d d re s s (3 2 b it s )
IV. PROCEDURES AND DATA
Defn.:A procedure is a subprogram that when called or initiated performs a specific task, leading to one or
more results, based on the input parameters (arguments) with which it is provided and returns to the point of
call.
Instruction used for invoking a procedure call : “ jal proc”
jal jump and link. i.e., jump to (transfer the control) the specified location “proc” and link back (return the
control) to the next instruction from where the procedure is invoked (called).
When
Opcode for jal instruction = 3 (000011)
Using a procedure involves the following sequence of actions:
1. Initialize input parameters (arguments) in places known to procedure (reg’s $a0-$a3)
2. Transfer control to procedure, saving the return address (jal)
3. Acquire storage space, if required, for use by the procedure
4. Perform the desired task
5. Put results in places known to calling program (reg’s $v0-$v1)
6. Return control to calling point (jr)
m ai n
P repa re
to c all
PC jal pr oc
P repa re
to c ontinue p r oc
S a ve, etc .
Res tor e
jr $ra
Fig.11. Illustrating a Procedure Call --- Relationship between the main program and a procedure
main
Prepare
to c all
PC jal ab c Procedure
Prep are abc
to c ontinue abc Procedure
Save xyz
xyz
jal xy z
Restore
jr $ra jr $ra
Fig.12. Illustrating a nested Procedure Call --- Relationship between the main program, procedures
As a procedure is executed, it makes use of registers to hold operands and partial results. Upon returning
from the procedure, the calling program might reasonably expect to find its own operands and partial results
where they were prior to procedure call.
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CS2071_Computer Architecture
To avoid the overhead associated with large number of register save and restore operations during procedure
calls the following set of registers are used by procedure.
o $v0-$v1
o $t0 - $t9
The division of responsibility between calling program and called program is quite sensible
calling program main program
called program callee program procedure
caller-saved registers: $v0-$v1, $t0 - $t9
o these registers are not disturbed by main program
o results of procedure execution are to be saved in these registers
o no need to restore the original content of the registers that was before the execution of procedure.
callee-saved registers: $a0-$a3, $s0-$s7, $gp, $sp, $fp, $ra
o These registers are not disturbed by procedure
o results of main memory are to be saved in these registers
o The original content of the registers that was before the execution of procedure are to be restored
after execution of procedure.
Saving of register content is required only if it will be used in future by caller / callee.
A single procedure can accept upto 4 arguments (input parameters), return upto 2 results and many
intermediate values
In Fig.12, the procedure “abc” calls procedure “xyz”. Before calling “xyz”, the calling procedure “abc”
performs some preparatory actions such as
o putting arguments in registers $a0-$a3
o saving any of the registers $v0-$v1, $t0 - $t9
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CS2071_Computer Architecture
Note: please refer chapter 6, section 6.2 and 6.3, 6.5 (arrays) for detailed description.
Hex address 00000000
Reserved 1 M words
4 MB
00400000
Text segment
Program
63 M words (252 MB)
10000000
Addressable Static data
with 16-bit 10008000
signed offset Data segm ent
1000ffff
Dynamic data
7ffffffc
Fig.13. Memory Map in MiniMIPS - Overview of the memory address space in MiniMIPS
$sp z
Local y Frame for
variables . current
Saved procedure
registers
Old ($fp)
$sp c $fp c
b Frame for b Frame for
a current a previous
procedure procedure
. ..
$fp
sp b
a
Push c Pop x
sp c
b b
a sp a x = mem[sp]
sp = sp – 4
sp = sp + 4
mem[sp] = c
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CS2071_Computer Architecture
Example of Using the Stack:
Saving $fp, $ra, and $s0 onto the stack and restoring them at the end of the procedure
A 32-bit word has no inherent meaning and can be interpreted in a number of equally valid ways in
the absence of other cues (e.g., context) for the intended meaning.
Bit pattern
0000 0010 0001 0001 0100 0000 0010 0000
(02114020) hex
00000010000100010100000000100000
Positive integer
Defn.: Assembly language is a low level language in which there is a very strong one-to-one
correspondence between language and computer architecture’s machine code instruction.
Example: add $to, $s8, $s5
addi $t1, $s7, 43
The advantage of assembly language.
o Extreme efficiency
o An assembly language program uses up much less memory
o Runs much faster.
Assembly language programs are divided roughly into 5 parts
o Header
o Equates
o Data
o Body
o Closing
Assembly language allows use of symbolic names for instructions and operands.
Assembly languages (assembler) accepts numbers in a variety of number representation
Executable
Assembly Machi ne machi ne
language language language Memory
Assembler
Loader
program program
Linker
program content
add $2, $5,$5 00a51020
add $2, $2,$2 00421020
add $2, $4,$2 00821020
lw $15 ,0($2) 8c620000
lw $16 ,4($2) 8cf20004
sw $16 ,0($2) ac f20000
sw $15 ,4($2) ac 620004
jr $31 03e00008
Overall process:
Multiple program modules that are independently assembled are linked together and combined with pre-
developed library routines to form a complete executable machine language program which is then
loaded into computer’s memory
Steps:
1. Assembler converts assembly language program into machine language program.
2. Linker links multiple machine language program modules together to form an executable machine
language program.
3. Loader loads executable machine language program into memory.
ASSEMBLER
Defn.: Assembler is program that translates instruction sequences written in symbolic assembly
language into machine language
Assembler accepts numbers in a variety of number representation and automatically convert thgem to
required machine formats
Assembler allows the use of pseudo instructions and macroinstructions.
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CS2071_Computer Architecture
Steps carried by assembler to translate assembly language into machine language are as follows
o Step1: Reads source file containi9ng assembly language program
Reads instruction and identifies operation symbols, registers, instruction label.
Assigns approx. opcode for instruction symbol from corresponding opcode table
Finds meaning of registers by referring corresponding reference table
o Step2: Creates a symbol table containing name and corresponding address
o Step3: Builds program text and data segment
o Step4: Forms a object file containing header, text, data and relocation information.
Relocation information: produced by assembler that contains the information for relocation of various
modules of same program and used by loader to relocate, link all modules with correct memory address
into one executable machine language program
Instruction location counter: determines relative position of instruction in machine language program
that gives numeric equivalent of instruction’s lable
Fig.16. An assembly-language program, its machine-language version, and the symbol table
created during the assembly process.
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CS2071_Computer Architecture
LOADER
Transfers the program from secondary memory to main memory for execution
Function of loader
Determining the memory needs of the program from its header.
Copying text and data from the executable program file into memory.
Modifying / shifting addresses, where needed during copying.
Placing program parameters onto stack.
Initializing all machine registers, including stack pointer
Jumping to a startup routine that calls the main routine.
3. ASSEMBLER DIRECTIVES:
(Refer section 7.2/page no. 126 in text book 1 by B.Parhami for more detailed description )
Assembler directives provide assembler with information on how to translate the program but do not
lead to generation of corresponding machine instruction.
Assembler directives specify the layout of data in the program’s data segment or define the variables
with symbolic names and desired initial values.
In MIPS, assembler directives begins with a period “.” To distinguish them from instruction.
.macro name(args) # macro and arguments named
... # instr’s defining the macro
.end_macro # macro terminator
.text beginning of program’s text
.end end of segment
.data beginning of data segment
(Refer section 7.6/page no. 133 in text book 1 by B.Parhami for more detailed description)
In below figure,
Register contents are shown in top panel
The program’s text segment is shown in second panel with each line containing [hex memory
address], hex instruction content, opcode and parameters
The program’s data segment is shown in third panel with each line containing a hex memory
address and conyents of 4 words (16 bytes) in hex format.
Message produced by SPIM are displayed in fourth panel
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CS2071_Computer Architecture
PCSpim User Interface
ClearRegisters
Reinitialize Text Segment
Reload
[0x00400000] 0x0c100008 jal 0x00400020 [main] ; 43
Go [0x00400004] 0x00000021 addu $0, $0, $0 ; 44
Break [0x00400008] 0x2402000a addiu $2, $0, 10 ; 45
Continue [0x0040000c] 0x0000000c syscall ; 46
Single Step [0x00400010] 0x00000021 addu $0, $0, $0 ; 47
Multiple Step ...
Breakpoints ...
Set Value ... Data Segment
Disp Symbol Table
Settings ... DATA
[0x10000000] 0x00000000 0x6c696146 0x20206465
[0x10000010] 0x676e6974 0x44444120 0x6554000a
Window [0x10000020] 0x44412067 0x000a4944 0x74736554
Tile
1 Messages Messages
2 Tex t Segment
3 Data Segment See the file README for a full copyright notice.
4 Regis ters Memory and registers have been cleared, and the simulator rei
5 Console
ClearConsole D:\temp\dos\TESTS\Alubare.s has been successfully loaded
Toolbar
Status bar
For Help, press F1 Base=1; Pseudo=1, Mapped=1; LoadTrap=0
Status bar
1. COMPLEX INSTRUCTIONS
MiniMIPS instruction performs relatively simple task such as single arithmetic / logic operations, copying of
basic data elements or transfer of control.
Defn.: a complex instruction is one that can potentially perform multiple memory accesses in course of its
execution
There is no standard definition for complex instruction.
Some instructions may be quite complex to describe and understand but easy to decode and excute
Don’t confuse pseudoinstruction and macro instruction with complex instruction
Example:
o Chksum regd, reg1, reg2
Set regd to checksum (XOR) of all bytes in array whose start address is in reg1 and end
address is in reg2
Steps involved in chksum instruction
XORing the next byte to a running checksum
Incrementing a pointer
Comparing the pointer with end address
Repeating if the comparison is unequal.
o sortup reg1, reg2
Arrange the integer words in array whose start address is in reg1 and end address is in reg2.
Merits:
o Use of more complex instruction leads to shorter text (i.e., reduces number of lines in a program)
o Less memory requirements
o Programs may become easier to write/read/understand
o Fewer memory accesses for instructions
o Potentially faster execution (complex steps are still done sequentially in multiple cycles, but
hardware control can be faster than software loops)
Demerits:
o Mastering more number of complex instruction and its usuage in appox. places in quite challenging
o Complex instruction will be rarely used.
o Makes instruction set more complex
o More complex format (slower decoding)
o Less flexible (one algorithm for polynomial evaluation or sorting may not be the best in all cases)
o If interrupts are processed at the end of instruction cycle, machine may become less responsive to
time-critical events (interrupt handling)
Examples of complex instructions in two popular modern microprocessors and two computer families of
historical significance
Machine Instruction Effect
Move one element in a string of bytes, words, or doublewords using addresses
Pentium MOVS specified in two pointer registers; after the operation, increment or decrement the
registers to point to the next element of the string
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CS2071_Computer Architecture
Polynomial evaluation with double flp arithmetic: Evaluate a polynomial in x,
Digital VAX POLYD with very high precision in intermediate results, using a coefficient table whose
location in memory is given within the instruction
Constant offset Me m
Base addr
Reg base Reg Add Me m
Reg f ile data Me mory data
Add addr Me m
Me mory data
PC
Pseudodirect PC Me m
addr Me mory Me m
data
With 6 addressing modes already seen include 4 more addressing modes as follows’
Indexed addresing
Update (with base) addresing
Update (with indexed) addresing
Indirect addresing
Addressing Instruction Other el ements invol ved Operand
Mem data
Indirect PC
Memory
Mem addr Memory
This part maybe replaced w ith any Mem addr, Mem data,
other f orm of address specif ication 2nd access 2nd access
If a variable is used again, you may have to push it multiple times
Special instructions such as “Duplicate” and “Swap” are helpful
A variation is to use one of the addresses as in a one-address machine and the second one to
specify a branch in every instruction
Example 80x86 instructions ranging in width from 1 to 6 bytes; much wider instructions (up to 15 bytes) also
exist
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CS2071_Computer Architecture
Instruction format and hardware structure for URISC.
Com p
C PC in MDR in MAR in
0 in
Write
0
Read
1
R R’ Adder P D A
C
N Z
in in unit
R in N Z 1 Mux 0 PC
out
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CS2071_Computer Architecture