Lab. de Diseo de Circuitos y Sistemas Electrnicos. 4 Ing.

Electrnica

Profesores: Alfredo Rosado. Manuel Bataller.
1
PRCTICA 2. Programacin de un sumador-restador de 3 bits.
1. Introduccin.

Para la realizacin de clculos binarios, es imprescindible la utilizacin de elementos capaces de realizar
operaciones matemticas. Las unidades aritmtico-lgicas (ALU) contienen esencialmente capacidades
aritmticas de suma y multiplicacin. En esta prctica se desea disear un mdulo sumador-restador de 3 bits
sin signo de acarreo encadenado basado en un sumador de un bit con acarreo de entrada y salida. Este
sumador de un bit se puede enlazar de modo que se puede construir un sumador de tantos bits como se desee
de forma rpida y sencilla. La estructura de nivel superior de este sumador es la que se muestra en la figura
siguiente

Figura 1. Esquema de un sumador-restador de 3 bits.

Cada mdulo de 1 bit posee cuatro entradas (A, B, CIN y ADDSUB) y dos salidas (S, COUT). La
entrada ADDSUB controla el resultado de la salida, efectuando la suma si su nivel lgico es 1, y la resta si
su nivel lgico es 0, en cualquier caso, la operacin se realiza entre los operandos A, B y CIN. Como
ejemplo de funcionamiento, si A=3, B=6, el resultado de la suma es 9, y dado que la resta siempre se realiza
como A-B, el resultado es: D=13. Un ejemplo de simulacin es:


Figura 2. Simulacin de las operaciones del sumador-restador de 3 bits.
2. Objetivo de la prctica.

En esta prctica vamos a realizar la implementacin sobre un dispositivo lgico programable, en este caso
sobre una FPGA Xilinx de la familia VirtexE modelo XCV100EPQ240-6. Los pasos a realizar son:


Lab. de Diseo de Circuitos y Sistemas Electrnicos. 4 Ing. Electrnica

Profesores: Alfredo Rosado. Manuel Bataller.
2
1. Diseo del mdulo sumador-restador de un bit.
2. Simulacin del mdulo sumador-restador de un bit.
3. Creacin de un elemento de librera para obtener un smbolo capaz de ser utilizado como un elemento
ms.
4. Simulacin funcional del mdulo de 3 bits, probando los diversos modos de operacin, es decir, en
modo suma, en modo resta, y con varias combinaciones de entrada para A y B.
5. Generacin de un mdulo de nivel superior donde se realice una decodificacin de las salidas para ser
mostradas en un display de 7 segmentos, en este nivel tambin se incluir una seal de entrada que
permita visualizar un nuevo resultado de la suma de los elementos de entrada cada vez que ocurre el
paso de estado bajo a alto para esta entrada. Se incluye una entrada de reset por la que cuando se
activa, la salida toma un valor cero.
6. Simular el sistema total.

El aspecto del dispositivo a nivel de entradas y salidas externas es el siguiente:


Figura 3. Smbolo completo con entradas y salidas del sistema final a disear.
4. Diseo y simulacin.

Primeramente se debe disear el sumador-restador de un bit, una vez simulado, se genera un elemento de
librera para el mismo. A continuacin se disea el sistema sumador-restador de 3 bit empleando el smbolo
de librera que se acaba de crear. Una vez diseado y simulado correctamente se genera otro smbolo de
librera para el mdulo de 3 bits. Como se desea visualizar el resultado en un display de 7 segmentos, se debe
incluir en el proyecto el fichero hex2led.vhdproporcionado. Para este fichero VHDL, tambin se genera el
smbolo esquemtico. En nuevo esquema se incluye el mdulo de 3 bits, el decodificador a 7 segmentos y la
lgica necesaria para hacer que el sistema slo actualice el clculo cuando se le proporcione la orden desde
la entrada Actualiza. Se simula el sistema completo y se comprueba que funciona correctamente.

NOTA: Si se necesita poner seales de entrada a nivel lgico cero uno, en la librera de smbolos se
dispone de los smbolos GND y VCC respectivamente.
5. Implementacin.

Una vez simulado, para que el diseo disponga de las entradas y salidas que corresponden a la ubicacin
de los interruptores y LED que existen en la placa, es necesario conocer el nmero de patilla donde cada uno
se ubica. En los anexos a esta memoria se muestran unos esquemas y una descripcin de la placa donde,
junto con la exploracin fsica de la placa disponible en el laboratorio, debis ser capaces de encontrar el
nmero de patilla que demos asignar a cada entrada y salida del diseo.

Escribe a continuacin la asignacin de cada patilla:
NET "suma<6>" LOC = ;
NET "suma<5>" LOC = ;
NET "suma<4>" LOC = ;
NET "suma<3>" LOC = ;

Lab. de Diseo de Circuitos y Sistemas Electrnicos. 4 Ing. Electrnica

Profesores: Alfredo Rosado. Manuel Bataller.
3
NET "suma<2>" LOC = ;
NET "suma<1>" LOC = ;
NET "suma<0>" LOC = ;
NET "reset" LOC = ;
NET "a<2>" LOC = ;
NET "a<1>" LOC = ;
NET "a<0>" LOC = ;
NET "addsub" LOC = ;
NET "actualiza" LOC = ;
NET "b<2>" LOC = ;
NET "b<1>" LOC = ;
NET "b<0>" LOC = ;

Para realizar la asignacin de patillas es necesario que en la ventana de fuentes aadamos una nueva
fuente (New Source), en este caso del tipo User Constraint File. Una vez creada, aparece un fichero con
extensin .ucf, que tenindolo seleccionado ejecutaremos la opcin de la ventana de procesos llamada User
Constraints ->Assign Package Pins. Esta opcin nos abre el editor PACE, donde tenemos las entradas y
salidas que podemos llevar a la patilla a asignar.


Figura 4. Imagen de PACE, editor de restricciones, empleado en este caso para asignar patillas
en el dispositivo FPGA a emplear.

Una vez realizada la asignacin de patillas ya podremos proceder a la implementacin del sistema. Para
ello, ejecutaremos la opcin Implement Design que automticamente realizar el proceso de asignar los
recursos lgicos. Si el proceso finaliza correctamente, visualizar los informes y buscar la informacin que se
solicita a continuacin:

Number of Slices: out of 1,200
Number of 4 input LUTs: out of 2,400
Number of bonded IOBs: out of 158
IOB Flip Flops:
6. Programacin de la placa.

Para generar el fichero que sirve para descargar el programa en la placa se ejecuta la accin Generate
Programming File.


Lab. de Diseo de Circuitos y Sistemas Electrnicos. 4 Ing. Electrnica

Profesores: Alfredo Rosado. Manuel Bataller.
4

Figura 5. Ventanas de fuentes y procesos para el diseo de esta sesin.

Una vez finalizado el proceso estaremos en disposicin de encender la fuente de alimentacin de la placa
para posteriormente entrar dentro del programa iMPACT que es el encargado de configurar el proceso de
programacin.

Al arrancar este programa aparece un asistente que solicita informacin acerca del tipo de programacin que
se desea realizar. Las opciones que se deben elegir son:


Figura 6. Opciones a seleccionar en iMPACT para programar el dispositivo.

El proceso de reconocimiento automtico debe reconocer dos dispositivos de programacin, una memoria
EEPROM XC18v01 que no vamos a emplear y la FPGA, para ello, nos pedir el fichero de programacin de
cada dispositivo, para el caso de la memoria, le decimos que lo ignore (Bypass), y para el caso de la FPGA
procederemos a indicarle el fichero .bit que se nos ha generado en la carpeta de nuestro proyecto.

Finalmente, el aspecto de iMPACT es el que sigue:


Lab. de Diseo de Circuitos y Sistemas Electrnicos. 4 Ing. Electrnica

Profesores: Alfredo Rosado. Manuel Bataller.
5

Figura 7. Ventana principal de iMPACT.

Se selecciona la FPGA (se selecciona en un color verde), y se ejecuta la opcin Operations ->Program,
procediendo a la verificacin de la misma.
Xilinx Virtex -E Evaluation Kit
November 28, 2000 (Version 1.1) DRAFT Advance Product Specification
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 1
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Features
FPGA
Xilinx Virtex-E XCV100E-6PQ240C
SPROM
Xilinx XC18V01SO20C
Board I/O Connectors
Two 50-pin, 0.1 Header connector
Pads for three MICTOR connectors
Pads for one 140 pin General Purpose I/O
interface
Power
+5.0 Power Connector
+3.3 V Regulated Supply
+1.8 V Regulated Supply
Full Bypass Capacitance
Communication
RS232 Serial Port
Configuration
JTAG Header Connector
In-System Programmable PROM
JTAG Download Cable
Miscellaneous
8 DIP switches
2 Push-buttons,
Dual Digit 7 Segment LED, right hand decimal
Infrared Transceiver
8 LEDs
40 MHz Oscillator
Digital Thermometer
Demonstration application (Source VHDL)
Simple RS232
Digital Thermometer
LED Patterns
Description
The Evaluation Virtex-E Kit is used by engineers as a
platform to test FPGA designs that are targeted to the
Xilinx Virtex-E device. It is also a great tool for beginners
to get aquatinted with FPGAs and VHDL.
The Virtex-E device is located in the center of the board. It
can be configured via a JTAG download or from the on
board configuration PROM. The configuration PROM is
also programmable through the JTAG cable. Over 85 IO
signals are connected from the FPGA to 0.1 header
connectors for user connections. Other IO are connected
to 8 LED, 8 dip switches, Two push buttons, RS-232 line
driver/receiver, and a digital thermometer.
Demo Application.
The board is supplied with complete VHDL source code
that:
1) Sequences LEDs
2) Reads Dip Switches/push buttons
3) Senses Temperature and displays value on
dual 7 segment LED
4) Transmits startup message through RS-232
connector.
5) Echoes RS-232 commands. (Serial cable not
included)
Ordering Information
The following table lists the development system part
numbers and available software options.
Internet Link at http://www.em.avnet.com/.
Table 1 Evaluation Virtex-E Board
Part Number Hardware
ADS-XLX-VE-EVL Xilinx Virtex-E Evaluation Kit
Xilinx Virtex-E Evaluation Kit
Page - 2 Literature # ADS-001205 November 28, 2000 (Version 1.1)
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
ADS Evaluation Virtex-E Board
This section provides information basic to the design of
Evaluation Virtex-E Board board.
Power
The majority of the design is powered at 3.3V with the
Virtex-E FPGA core powered at 1.8V. The board should
be powered by a 5-volt bench supply. The 3.3V is derived
via a linear regulator. A linear regulator from the 3.3V
provides the 1.8V Xilinx core voltage. A barrel connector
J3 (RAPC712) is provided on the board for lab supply
connections. The center tap is +5.0 volts and the outer is
GND. Note: The lab supply should be regulated at 5.0
volts. While current requirements are dependent on the
user application, it is suggested to limit your supply to 1.5
amps on initial power up.
0.098 in
pin diameter
0.25 in
housing diameter
+5.0 Volts GND
Printed Circuit Board
The Evaluation Virtex-E Board printed circuit board is an
6-layer board with four signal layers, a full 3.3V power
plane incorporating an isolated 1.8V mini-plane, and full
ground plane. The board stack-up layers 1 through 6 is:
1) Component side/signal
2) Ground Plane
3) Signal
4) Signal
5) Power: 3.3V and 1.8V
6) Solder side/signal
Virtex-E FPGA
The Virtex-E Field-Programmable Gate Array device (U1)
utilized in this design is the 100+K-system gate device
(XCV100E) in a PQ240 package.
FPGA Configuration
Configuration information is provided from two sources;
the JTAG Connector (JTAG0), and configuration PROM.
Table 2 JTAG Connector
Signal Name JTAG Connector Pin #
VCC 1
TDI 2
TMS 3
TCK 4
TDO 5
GND 6
Jumpers JP1, JP2 and JP3 select the configuration mode of
the Virtex. The following table shows the jumper setting
needed for each mode.
Table 3 Mode Select
Configuration
Mode
Pull-
ups
JP3/M2 JP2/M1 JP1/M0
Master-serial No OFF /LOW OFF /LOW OFF /LOW
Boundary-scan No ON /HIGH OFF /LOW ON /HIGH
SelectMAP No ON /HIGH ON /HIGH OFF /LOW
Slave-serial No ON /HIGH ON /HIGH ON /HIGH
Master-serial Yes ON /HIGH OFF /LOW OFF /LOW
Boundary-scan Yes OFF /LOW OFF /LOW ON /HIGH
SelectMAP Yes OFF /LOW ON /HIGH OFF /LOW
Slave-serial Yes OFF /LOW ON /HIGH ON /HIGH
The LED D1 indicates the output level of the DONE pin of
the Virtex-E device. It will illuminate when the Virtex-E
configuration is complete.
System Clock
An oscillator socket clock output is connected to the
Virtex-E device. U5 is connected to Global Clock Input #0
(PQ240 pin #P92), The U5 socket is populated with a 40
MHz oscillator.
Asynchronous (RS232) Communication
Interface
The ADM3222 device provides level translation for a
single RS232 interface (DB9 connector). The second
translation port on the device is terminated and unused.
Xilinx Virtex-E Evaluation Kit
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 3
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Table 4 RS232 Interface Signals
RS232 SIGNAL Virtex-E PIN #
R1OUT P216
T1IN P217
EN_N P218
SD_N P219
Table 5 RS232 Connector Pinout
Signal Name P2 (DB9) connector Pin #
TX out 2
RX in 3
GND 5
Miscellaneous
The Miscellaneous interfaces on the Virtex-E board
consist of a single 8-position DIP switch (8-individual
SPST switches), 8 LEDs, and two push-button switches.
Table 6 Dip Switch Signals
DIP SW Virtex-E PIN #
#1 P194
#2 P195
#3 P199
#4 P200
#5 P201
#6 P202
#7 P203
#8 P205
Table 7 Push Button Switch Signals
BUTTON Virtex-E PIN #
SW1 P206
SW2 P208
Table 8 LED Control Signals
LED
Virtex-E PIN #
D2 P27
D3 P28
D4 P3
D5 P4
D6 P5
D7 P6
D8 P7
D9 P9
Table 9 Dual Segmented LED Signals
LED
Virtex-E PIN #
A1 P221
B1 P222
C1 P223
D1 P224
E1 P228
F1 P229
G1 P230
Dp1 P231
A2 P234
B2 P235
C2 P236
D2 P237
E2 P238
F2 P186
G2 P187
Dp2 P188
Table 10 Infrared Signals
LED
Virtex-E PIN #
TXD P102
RXD P101
SHDN P100
Table 11 Digital Themometer
LED
Virtex-E PIN #
CE P160
SCLK P159
SDI P161
SDO P162
Xilinx Virtex-E Evaluation Kit
Page - 4 Literature # ADS-001205 November 28, 2000 (Version 1.1)
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
I/O Signal Headers
Two 50-pin connectors provides 84 Virtex-E I/O lines and
6 ground pins.
Table 12 GPIO Signals JP5
GPIO CONNECTOR PIN
#
Virtex-E PIN #
1 P86
2 P84
3 P82
4 P81
5 P80
6 P79
7 P78
8 P74
9 P73
10 P72
11 P71
12 P70
13 P68
14 P67
15 P66
16 P65
17 P64
18 P63
19 P99
20 P97
21 P96
22 P95
23 P94
24 P118
25 P117
26 P115
27 P114
28 P113
29 P111
30 P110
31 P109
32 P108
33 P149
34 P147
35 P144
36 P142
37 P141
38 P140
39 P134
40 P133
41 P132
42 P131
43 P130
44 Reserved
45 Reserved
46 Reserved
47 Reserved
48 GND
49 GND
50 GND
Table 13 GPIO Signals JP6
GPIO CONNECTOR PIN
#
Virtex-E PIN #
1 P31
2 P33
3 P34
4 P35
5 P36
6 P38
7 P39
8 P40
9 P41
10 P42
11 P46
12 P47
13 P48
14 P49
15 P50
16 P52
17 P53
18 P54
19 P56
20 P57
21 P10
22 P11
23 P12
24 P13
25 P17
26 P18
27 P19
28 P20
29 P21
30 P23
31 P24
32 P26
33 P128
34 P127
35 P126
36 P125
37 P175
38 P174
39 P173
40 P171
41 P170
42 P169
43 Reserved
44 Reserved
45 Reserved
46 Reserved
47 Reserved
48 GND
49 GND
50 GND
Xilinx Virtex-E Evaluation Kit
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 5
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Logic Analyzer Connector
Three AMP MICTOR connector pads are provided to
connect to a logic analyzers mass termination cable.
Table 14 MICTOR J4
Connector PIN # Virtex-E
PIN #
Name
1 N/C N/C
2 N/C N/C
3 N/C N/C
4 N/C N/C
5 P210* CLK_OUT
6 P92 OSC
7 P108 ADDRESS31
8 P65 ADDRESS15
9 P109 ADDRESS30
10 P66 ADDRESS14
11 P110 ADDRESS29
12 P67 ADDRESS13
13 P111 ADDRESS28
14 P68 ADDRESS12
15 P113 ADDRESS27
16 P70 ADDRESS11
17 P114 ADDRESS26
18 P71 ADDRESS10
19 P115 ADDRESS25
20 P72 ADDRESS9
21 P117 ADDRESS24
22 P73 ADDRESS8
23 P118 ADDRESS23
24 P74 ADDRESS7
25 P94 ADDRESS22
26 P78 ADDRESS6
27 P95 ADDRESS21
28 P79 ADDRESS5
29 P96 ADDRESS20
30 P80 ADDRESS4
31 P97 ADDRESS19
32 P81 ADDRESS3
33 P99 ADDRESS18
34 P82 ADDRESS2
35 P63 ADDRESS17
36 P84 ADDRESS1
37 P64 ADDRESS16
38 P86 ADDRESS0
39 GND GND
40 GND GND
41 GND GND
42 GND GND
43 GND GND
Table 15 MICTOR J5
Connector PIN # Virtex-E
PIN #
Name
1 N/C N/C
2 N/C N/C
3 N/C N/C
4 N/C N/C
5 P213* GCK3
6 P89* GCLK1
7 P26 DATA31
8 P52 DATA15
9 P24 DATA30
10 P50 DATA14
11 P23 DATA29
12 P49 DATA13
13 P21 DATA28
14 P48 DATA12
15 P20 DATA27
16 P47 DATA11
17 P19 DATA26
18 P46 DATA10
19 P18 DATA25
20 P42 DATA9
21 P17 DATA24
22 P41 DATA8
23 P13 DATA23
24 P40 DATA7
25 P12 DATA22
26 P39 DATA6
27 P11 DATA21
28 P38 DATA5
29 P10 DATA20
30 P36 DATA4
31 P57 DATA19
32 P35 DATA3
33 P56 DATA18
34 P34 DATA2
35 P54 DATA17
36 P33 DATA1
37 P53 DATA16
38 P31 DATA0
39 GND GND
40 GND GND
41 GND GND
42 GND GND
43 GND GND
Xilinx Virtex-E Evaluation Kit
Page - 6 Literature # ADS-001205 November 28, 2000 (Version 1.1)
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Table 16 MICTOR J6
Connector PIN # Virtex-E
PIN #
Name
1 N/C N/C
2 N/C N/C
3 N/C N/C
4 N/C N/C
5 P210* CLK_OUT
6 P191* CLK_IN
7 P178 DOUT
8 P175 CNTL15
9 P208 SWITCH9
10 P125 CNTL14
11 P206 SWITCH8
12 P126 CNTL13
13 P162 TEMP_SDO
14 P127 CNTL12
15 P161 TEMP_SDI
16 P128 CNTL11
17 P160 TEMP_CE
18 P130 CNTL10
19 P159 TEMP_SCLK
20 P131 CNTL9
21 P220 RS232SD_N
22 P132 CNTL8
23 P218 RS232EN_N
24 P133 CNTL7
25 P217 RS232TX
26 P139 CNTL6
27 P216 RS232RX
28 P140 CNTL5
29 P169 CNTL20
30 P141 CNTL4
31 P170 CNTL19
32 P142 CNTL3
33 P171 CNTL18
34 P144 CNTL2
35 P173 CNTL17
36 P147 CNTL1
37 P174 CNTL16
38 P149 CNTL0
39 GND GND
40 GND GND
41 GND GND
42 GND GND
43 GND GND
*Note: A zero ohm resistor may be required to access the
noted signals.
AvBus Connector
High-density connector pads are located on bottom of the
board. The signals are listed in the following table.
Table 17 AvBus Connector P2
Name FPGA
PIN #
Connector PIN # FPGA
PIN #
Name
ADDRESS0 P86 71 1 N/C N/C
GND GND 72 2 P84 ADDRESS1
ADDRESS3 P81 73 3 P82 ADDRESS3
ADDRESS4 P80 74 4 GND GND
GND GND 75 5 P79 ADDRESS5
ADDRESS7 P74 76 6 P78 ADDRESS6
ADDRESS8 P73 77 7 GND GND
AUX_+3.3V +3.3V 78 8 P72 ADDRESS9
ADDRESS11 P70 79 9 P71 ADDRESS10
ADDRESS12 P68 80 10 GND GND
GND GND 81 11 P67 ADDRESS13
ADDRESS15 P65 82 12 P66 ADDRESS14
ADDRESS16 P64 83 13 N/C N/C
GND GND 84 14 P63 ADDRESS17
ADDRESS19 P97 85 15 P99 ADDRESS18
ADDRESS20 P96 86 16 GND GND
GND GND 87 17 P95 ADDRESS21
ADDRESS23 P118 88 18 P94 ADDRESS22
ADDRESS24 P117 89 19 GND GND
AUX_+3.3V +3.3V 90 20 P115 ADDRESS25
ADDRESS27 P113 91 21 P114 ADDRESS26
ADDRESS28 P111 92 22 GND GND
GND GND 93 23 P110 ADDRESS29
ADDRESS31 P108 94 24 P109 ADDRESS30
DATA0 P31 95 25 N/C N/C
GND GND 96 26 P33 DATA1
DATA3 P35 97 27 P34 DATA2
DATA4 P36 98 28 GND GND
GND GND 99 29 P38 DATA5
DATA7 P40 100 30 P39 DATA6
DATA8 P41 101 31 GND GND
AUX_+3.3V +3.3V 102 32 P42 DATA9
DATA11 P47 103 33 P46 DATA10
DATA12 P48 104 34 GND GND
GND GND 105 35 P49 DATA13
DATA15 P52 106 36 P50 DATA14
DATA16 P53 107 37 N/C N/C
GND GND 108 38 P54 DATA17
DATA19 P57 109 39 P56 DATA18
DATA20 P10 110 40 GND GND
GND GND 111 41 P11 DATA21
DATA23 P13 112 42 P12 DATA22
DATA24 P17 113 43 GND GND
AUX_+3.3V +3.3V 114 44 P18 DATA25
DATA27 P20 115 45 P19 DATA26
DATA28 P21 116 46 GND GND
GND GND 117 47 P23 DATA29
DATA31 P26 118 48 P24 DATA30
CNTL0 P149 119 49 N/C N/C
GND GND 120 50 P147 CNTL1
CNTL3 P142 121 51 P144 CNTL2
CNTL4 P141 122 52 GND GND
GND GND 123 53 P140 CNTL5
CNTL7 P133 124 54 P139 CNTL6
CNTL8 P132 125 55 GND GND
AUX_+3.3V +3.3V 126 56 P131 CNTL9
CNTL11 P128 127 57 P130 CNTL10
Xilinx Virtex-E Evaluation Kit
November 28, 2000 (Version 1.1) Literature # ADS-001205 Page - 7
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Name FPGA
PIN #
Connector PIN # FPGA
PIN #
Name
CNTL12 P127 128 58 GND GND
GND GND 129 59 P126 CNTL13
CNTL15 P175 130 60 P125 CNTL14
CNTL16 P174 131 61 N/C N/C
GND GND 132 62 P173 CNTL17
CNTL19 P170 133 63 P171 CNTL18
CNTL20 P169 134 64 GND GND
GND GND 135 65 P191* CLK_IN
CLK_OUT P210* 136 66 P210* CLK_OUT_FB
TMS 137 67 GND GND
AUX_+3.3V +3.3V 138 68 TDO
TDI 139 69 TCK
TRS 140 70 GND GND
*Note: A zero ohm resistor may be required to access the
noted signals.
Note: Reference Schematic for current JTAG signal
paths.
Demonstration Program
Supplied with the development system is a demonstration
program file that utilizes several devices on the evaluation
board. The demonstration program uses the evaluation
development board as a standalone platform that is
connected to a lab supply and a terminal emulation
program. On power up the onboard PROM will configure
the FPGA. Upon completion of the configuration the
FPGA functionality and input/output signal will activate.
A start up serial message will be sent to the terminal port
via the RS-232 connection. The LEDs will display a back
and forth scanning pattern or 8-bit value corresponding to
the current temperature. The Dual segmented display will
count up or display the current temperature.
Additional Items Needed:
Lab power supply, 5.0 volts at 1.5 amps.
Serial Terminal or Terminal Emulator.
RS-232 cable
Setup:
1) Attach the lab supply to the power connector on
the Evaluation Board.
2) Attach the serial terminal to the P1 connector of
the Evaluation Board.
3) Set the Serial Terminal to: 8 data bits, 1 stop , No
parity, 9600 baud.
4) Verify jumper are NOT installed on JP1,JP2,and
JP3.
5) Verify JP4 is installed across pins 1 and 2.
Power UP:
6) Apply power to the Evaluation Board.
7) The DONE LED D1 will light on the completion
of the download.
Reset:
8) Press the Soft Reset button SW1 to reset the
board.
Serial Demo
9) Press the button SW2 to send the startup message.
10) The Power up message is displayed on the serial
terminal.
11) All characters typed should be echoed to the
terminal.
12) Press the Reset button again to reset startup
message.
LED SCAN
13) Set the dipswitch S1 dip 1 to ON (rocker up).
14) The LEDs should be blinking such that the
illuminated led should be scanning back and forth
through the LED array.
UP COUNTER
15) Set the dipswitch S1 dip 2 to ON (rocker down).
16) The Dual segmented LEDs should be counting
up.
TEMPERATURE
17) Set the dipswitch S1 dip 1 to OFF (rocker down).
18) The LED should now display the temperature in
C in twos complement binary. See the following
table.
19) Set the dipswitch S1 dip 2 to OFF (rocker down).
20) The Dual segmented LEDs should now display
the temperature in C.
21) Hold your finger on U5 to change the
temperature.
LED Pattern
(D9..D2)
Decimal Value (C)
0111 1000 +120C
0001 1001 +25C
0000 1010 +10C
0000 0000 0C
1111 0101 -10C
1110 0110 -25C
1100 1001 -55C
Xilinx Virtex-E Evaluation Kit
Page - 8 Literature # ADS-001205 November 28, 2000 (Version 1.1)
2000, Avnet, Inc. All rights reserved. Xilinx is a registered trademark of Xilinx, Inc. Virtex is a trademark of Xilinx, Inc.
All other trademarks and registered trademarks are the property of their respective owners.
Relevant Documents
Documents relevant to this application are listed in the
following table.
Table 18. Relevant Documents and Links
Document Source
XILINX VIRTEX-E FPGA Data
Sheet
http://www.xilinx.com/parti
nfo/ds022.pdf
Document Source
XILINX XC18V01 Configuration
PROM Data Sheet
http://www.xilinx.com/parti
nfo/ds026.pdf
Analog Devices ADM3222 3V
RS232 Line Driver/Receiver Data
Sheet
http://www.analog.com/pdf/
ADM3202_0.pdf
Block Diagram
Revisions
Version 1.0 Initial Release.
Version 1.1 Fixed typographical errors.
5
0

P
i
n
H
e
a
d
e
r
XILINX
XC18V01SO20C
Configuration
PROM
8

L
E
D
S
Digital
Thermometer
40MHz
OSC
A
v
B
u
s

B
o
a
r
d

t
o

B
o
a
r
d
1
4
0

P
i
n

C
o
n
n
e
c
t
o
r
RS-232
JTAG Header
3 MICTORs
5
0

P
i
n
H
e
a
d
e
r
8

D
i
p

S
w
i
t
c
h
e
s
2 Push
Buttons
XILINX
VIRTEX-E
XCV100E-6PQ240
FPGA
Dual
8-Segment
LED
Infrared
Transceiver
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
4
Copyright 2000, Avnet, Inc. All Rights Reserved.
This material may not be reproduced, distributed, republished, displayed, posted, transmitted or copied in
any form or by any means without the prior written permission of Avnet, Inc. AVNET and the AV logo are
registered trademarks of Avnet, Inc. All trademarks and trade names are the properties of their respective
owners and Avnet, Inc. disclaims any proprietary interest or right in trademarks, service marks and trade
names otherthan its own.
Avnet is not responsiblefor typographical or other errors or omissions or for direct, indirect, incidental or
consequential damages r elated to this material or resulting from its use. Avnet makes no warranty or
representation respecting this material, which is provided on an "AS IS" basis. AVNET HEREBY
DISCLAIMS ALL WARRANTIES OR LIABILITY OF ANY KIND WITH RESPECT THERETO, INCLUDING,
WITHOUT LIMITATION, REPRESENTATIONS REGARDING ACCURACY AND COMPLETENESS, ALL
IMPLIED WARRANTIES AND CONDITIONS OF MERCHANTABILITY,SUITABILITY OR FITNESS FOR A
PARTICULAR PURPOSE, TITLE AND/OR NON-INFRINGEMENT. This material is not design ed, intended
or authorized for use inmedical, life support, life sustaining or nuclear applications or applications in which
the failure of the product could result in personal injury, death or property damage. Any party using or
selling products for use in any suc h applications do so at their sole risk and agree that Avnet is not liable,
in whole or inpart, for any claim or damage arising from such use, and agree to fully indemnify, defend and
hold harmless Avnet from and ag ainst any and all claims, damages, loss, cost, expense or liability arising
out of or in connection with the use or performance of products in such applications.
Mictor and Header Connectors
2
Mini-Virtex-E Evauation Board
Sheet Number
Power
Function
FPGA, SPROM
www.em.avnet.com
3
1
Avnet Design Services
Switch, LED, OSC 5
Lead Sheet
Initial Release
REV SHEET
DATE
A
DESCRIPTION
ALL 11-OCT-2000
6 Daughter Board Connector
LIT# ADS-001207
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Lead Sheet
B
1 Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOT POPULATED
NOT POPULATED
NOT POPULATED
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Lead Sheet
C
2 Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, I nc. Design Services Copyright 2000
MODE0
TMS
FPGA_TDO
TCK
CCLK
INIT_N
TMS
TCK
D0
DONE
SP_TDI
CONN_TDO
CONN_TDI
TMS
TCK
F
P
G
A
_
T
D
O
S
P
_
T
D
I
C
O
N
N
_
T
D
O
F
P
G
A
_
T
D
O
C
O
N
N
_
T
D
I
S
P
_
T
D
I
MODE2
SP_TDO
CS_N
CONN_TCK
CONN_TCK
CONN_TMS
CONN_TMS
D
A
T
A
3
0
D
A
T
A
1
T
C
K
F
P
G
A
_
T
D
O
D
A
T
A
1
0
D
A
T
A
3
D
O
N
E
D
A
T
A
1
9
D
A
T
A
1
5
D
A
T
A
2
WRITE_N
CS_N
M
O
D
E
2
IN
IT
_
N
D
0
S
P
_
T
D
O
M
O
D
E
0
D
A
T
A
2
8
D
A
T
A
2
1
D
A
T
A
1
7
D
A
T
A
8
D
A
T
A
1
3
D
A
T
A
1
2
M
O
D
E
1
D
A
T
A
2
4
ADDRESS23
C
C
L
K
C
F
_
N
D
A
T
A
2
3
D
A
T
A
2
9
D
A
T
A
2
0
D
A
T
A
0
T
M
S
D
A
T
A
2
5
D
A
T
A
1
8
D
A
T
A
2
6
D
A
T
A
1
6
D
A
T
A
1
4
D
A
T
A
3
1
D
A
T
A
4
D
A
T
A
1
1
D
A
T
A
9
D
A
T
A
5
MODE1
D
A
T
A
2
7
D
A
T
A
7
WRITE_N
D
A
T
A
2
2
D
A
T
A
6
ADDRESS24
ADDRESS29
ADDRESS28
ADDRESS31
ADDRESS25
ADDRESS26
ADDRESS30
ADDRESS27
ADDRESS19
ADDRESS20
ADDRESS22
ADDRESS21
ADDRESS18
ADDRESS10
ADDRESS14
ADDRESS8
ADDRESS9
ADDRESS12
ADDRESS11
ADDRESS13
ADDRESS17
ADDRESS16
ADDRESS15
ADDRESS7
ADDRESS4
ADDRESS3
ADDRESS6
ADDRESS2
ADDRESS5
ADDRESS1
ADDRESS0
C
N
T
L
0
C
N
T
L
1
C
N
T
L
2
C
N
T
L
3
C
N
T
L
4
C
N
T
L
5
C
N
T
L
6
C
N
T
L
7
C
N
T
L
8
C
N
T
L
9
C
N
T
L
1
0
C
N
T
L
1
1
C
N
T
L
1
2
C
N
T
L
1
3
C
N
T
L
1
4
C
N
T
L
1
5
C
N
T
L
1
6
C
N
T
L
1
7
C
N
T
L
1
8
C
N
T
L
1
9
C
N
T
L
2
0
SWITCH9
SWITCH8
SWITCH7
SWITCH6
SWITCH5
SWITCH4
SWITCH3
SWITCH2
SWITCH1
SWITCH0
L
E
D
0
L
E
D
1
L
E
D
2
L
E
D
3
L
E
D
4
L
E
D
5
L
E
D
6
L
E
D
7
CF_N
SWITCH[0:9]
JTAG_TMS
JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TRS
OSC
ADDRESS[0:31]
CNTL[0:20]
GCK3
CLK_OUT_FB
DATA[0:31]
RS232RX
RS232TX
RS232EN_N
RS232SD_N
SEG2_C
SEG1_G
SEG2_G
SEG2_B
SEG1_E
SEG2_Dp
SEG2_A
SEG1_B
SEG1_Dp
SEG1_C
SEG1_D
SEG2_E
SEG1_A
SEG2_D
SEG2_F
SEG1_F
TEMP_CE
TEMP_SDO
TEMP_SDI
TEMP_SCLK
GCK1_FB
GCK1
OSC_FB
DOUT
CLK_OUT
IR_SHDN
IR_RXD
IR_TXD
LED[0:7]
CLK_IN
VCC VCC
VCC
VCC
VCC
VCC
+1.8V
3.3V
R15
Do Not Populate
1 2
U2
XC1801SO20
3
8
10
11
19
20
18
1
16
2
15
7
14
9
12
13
5
6
4
17
CLK
RST/OE
CE
GND
VCCO
VCC
VCC
D0/DATA
D1
D2
D3
D4/CF
D5
D6
D7
CEO
TMS
TCK
TDI
TDO
J2
Do Not Populate
123
A
C
o
mB
U1
VIRTEX E - PQ240
212
213
215
216
217
218
220
221
222
223
224
226
228
229
230
231
232
234
235
236
237
238
180
184
185
186
187
188
189
191
192
193
194
195
197
199
200
201
202
203
205
206
207
208
209
210
1
5
0
1
5
2
1
5
3
1
5
4
1
5
5
1
5
6
1
5
7
1
5
9
1
6
0
1
6
1
1
6
2
1
6
3
1
6
5
1
6
7
1
6
8
1
6
9
1
7
0
1
7
1
1
7
3
1
7
4
1
7
5
1
7
6
1
7
7
1
7
8
1
7
9
1
8
1
1
2
0
1
2
1
1
2
3
1
2
4
1
2
5
1
2
6
1
2
7
1
2
8
1
3
0
1
3
1
1
3
2
1
3
3
1
3
4
1
3
6
1
3
8
1
3
9
1
4
0
1
4
1
1
4
2
1
4
4
1
4
5
1
4
6
1
4
7
1
4
9
100
101
102
103
105
107
108
109
110
111
113
114
115
116
117
118
90
92
93
94
95
96
97
99
61
63
64
65
66
67
68
70
71
72
73
74
76
78
79
80
81
82
84
85
86
87
89
3
0
3
1
3
3
3
4
3
5
3
6
3
8
3
9
4
0
4
1
4
2
4
4
4
6
4
7
4
8
4
9
5
0
5
2
5
3
5
4
5
5
5
6
5
7
1
0
1
1
1
2
1
3
1
5
1
7
1
8
1
9
2
0
2
1
2
3
2
4
2
4
0
2
5
2
6
2
7
2
8
3456791
0
4
1
3
7
1
4
8
1
6
1
6
4
1
9
8
2
1
4
2
2
5
3
2
4
3
7
7
8
8
6
0
5
8
6
2
1
2
2
2
3
9
1
8
3
2
1 1
0
6
1
1
2
1
1
9
1
2
9
1
3
5
1
4
1
4
3
1
5
1
1
5
8
1
6
6
1
7
2
1
8
2
1
9
0
1
9
6
2
0
4
2
1
1
2
1
9
2
2
2
2
7
2
3
3
2
9
3
7
4
5
5
1
5
9
6
9
7
5
8 8
3
9
1
9
8
VCCO
GCK3
IO_LVDS_DLL_L6N
IO_VREF
IO_L5P_Y
IO_VREF_L5N_Y
IO_L4P_Y
IO_L4N_Y
IO
IO_L3P_YY
IO_L3N_YY
VCCO
IO_L2P_YY
IO_VREF_L2N_YY
IO
IO_VREF
VCCO
IO_L1P_YY
IO_L1N_YY
IO_VREF_L0P_Y
IO_L0N_Y
IO
VCCO
IO_CS_L14P_YY
IO_WRITE_L14N_YY
IO_L13P
IO_VREF_L13N
IO_L12P_YY
IO_L12N_YY
IO_VREF_L11P_YY
IO_L11N_YY
IO
IO_VREF_L10P_YY
IO_L10N_YY
VCCO
IO_L9P_YY
IO_L9N_YY
IO
IO_L8P_Y
IO_L8N_Y
IO_VREF_L7P_Y
IO_L7N_Y
VCCO
IO_VREF
IO_LVDS_DLL_L6P
GCK2
V
C
C
O
IO
_
L
2
3
N
_
Y
Y
IO
_
L
2
3
P
_
Y
Y
IO
_
V
R
E
F
_
L
2
2
N
IO
_
L
2
2
P
IO
_
D
3
_
L
2
1
N
_
Y
IO
_
V
R
E
F
_
L
2
1
P
_
Y
IO
_
L
2
0
N
_
Y
IO
_
L
2
0
P
_
Y
IO IO
_
L
1
9
N
_
Y
Y
IO
_
D
2
_
L
1
9
P
_
Y
Y
V
C
C
O
IO
_
D
1
_
L
1
8
N
_
Y
IO
_
V
R
E
F
_
L
1
8
P
_
Y
IO IO
_
L
1
7
N
_
Y
IO
_
V
R
E
F
_
L
1
7
P
_
Y
IO
_
L
1
6
N
_
Y
IO
_
L
1
6
P
_
Y
IO
_
V
R
E
F
V
C
C
O
IO
_
D
IN
_
D
0
_
L
1
5
N
_
Y
Y
IO
_
D
O
U
T
_
B
U
S
Y
_
L
1
5
P
_
Y
Y
C
C
L
K
T
D
O
D
O
N
E
V
C
C
O
IO
_
IN
IT
_
L
3
1
N
_
Y
Y
IO
_
D
7
_
L
3
1
P
_
Y
Y
IO
_
L
3
0
N
IO
_
V
R
E
F
_
L
3
0
P
IO
_
L
2
9
N
_
Y
IO
_
L
2
9
P
_
Y
IO
_
V
R
E
F
_
L
2
8
N
_
Y
IO
_
L
2
8
P
_
Y
IO IO
_
V
R
E
F
_
L
2
7
N
_
Y
IO
_
D
6
_
L
2
7
P
_
Y
V
C
C
O
IO
_
D
5
_
L
2
6
N
_
Y
Y
IO
_
L
2
6
P
_
Y
Y
IO IO
_
L
2
5
N
_
Y
IO
_
L
2
5
P
_
Y
IO
_
V
R
E
F
_
L
2
4
N
_
Y
IO
_
D
4
_
L
2
4
P
_
Y
V
C
C
O
IO
_
V
R
E
F
IO
IO_L37P_Y
IO
IO_L36N_YY
IO_L36P_YY
VCCO
IO_L35N_YY
IO_VREF_L35P_YY
IO
IO_L34N_YY
IO_VREF_L34P_YY
IO_L33N_YY
IO_L33P_YY
IO_VREF
VCCO
IO_L32N_YY
IO_L32P_YY
VCCO
GCK0
IO_LVDS_DLL_L40P
IO_VREF_L39N
IO_L39P
IO_L38N_Y
IO_VREF_L38P_Y
IO_L37N_Y
VCCO
IO_L47N_YY
IO_L47P_YY
IO_L46N_Y
IO_VREF_L46P_Y
IO_L45N_YY
IO_L45P_YY
IO_VREF_L44N_YY
IO_L44P_YY
IO
IO_VREF_L43N_YY
IO_L43P_YY
VCCO
IO_L42N_YY
IO_L42P_YY
IO
IO
IO_L41N
IO_VREF_L41P
VCCO
IO_VREF
IO_LVDS_DLL_L40N
GCK1 V
C
C
OIO
IO
_
V
R
E
F
_
L
5
5
P
IO
_
L
5
5
N
IO
_
L
5
4
P
_
Y
IO
_
V
R
E
F
_
L
5
4
N
_
Y
IO
_
L
5
3
P
_
Y
IO
_
L
5
3
N
_
YIO
IO
_
L
5
2
P
_
Y
Y
IO
_
L
5
2
N
_
Y
Y
V
C
C
O
IO
_
L
5
1
P
_
Y
IO
_
V
R
E
F
_
L
5
1
N
_
YIO
IO
_
L
5
0
P
_
Y
IO
_
V
R
E
F
_
L
5
0
N
_
Y
IO
_
L
4
9
P
_
Y
IO
_
L
4
9
N
_
Y
IO
_
V
R
E
F
V
C
C
O
IO
_
L
4
8
P
_
Y
Y
IO
_
L
4
8
N
_
Y
Y
IO
_
L
6
1
N
_
YIO
IO
_
V
R
E
F
_
L
6
0
P
_
Y
IO
_
L
6
0
N
_
Y
V
C
C
O
IO
_
L
5
9
P
_
Y
Y
IO
_
L
5
9
N
_
Y
YIO
IO
_
L
5
8
P
_
Y
IO
_
L
5
8
N
_
Y
IO
_
V
R
E
F
_
L
5
7
P
_
Y
IO
_
L
5
7
N
_
Y
V
C
C
O
V
C
C
O
IO
_
V
R
E
F
IO
_
L
5
6
P
_
Y
Y
IO
_
L
5
6
N
_
Y
YIO
IO
_
L
6
3
P
IO
_
V
R
E
F
_
L
6
3
N
IO
_
L
6
2
P
_
Y
IO
_
L
6
2
N
_
Y
IO
_
V
R
E
F
_
L
6
1
P
_
Y
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
V
C
C
IN
T
M
0
M
1
M
2
P
R
O
G
R
A
M
T
C
K
T
D
I
T
M
S
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
D1
QTLP650C-4
R6
0R0/0805
1 2
R13
1K
1
2
R12
0R0/0805
1 2
JTAG1
JTAG Header
1
2
3
4
5
6
J1
Do Not Populate
123
A
C
o
mB
R2
Do Not Populate
1 2
R11
0R0/0805
1 2
JP1
HEADER 2x1
1
2
R10
Do Not Install
1
2
R7
Do Not Install
1
2
R1
Do Not Populate
1 2
R9
Do Not Install
1
2
R5
10K
1 2
JP2
HEADER 2x1
1
2
R4
10K
1 2
R3
10K
1 2
C1
0.1uF
1
2
R8
Do Not Install
1
2
JP3
HEADER 2x1
1
2
R14
4.7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
AVNET, INC. CONFIDENTIAL
Virtex-E Decoupling Caps
0.1 uf per Vccco
47uf per Bank
Virtex-E Decoupling Caps
0.1uf per Vccint
four 47uF per device
one 470uF per device
3.3V
1.8V
H394-XLX5-MVE-1002
A
Mini-Virtex-E Board - Power
B
3 Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
3.3V
+1.8V
5V
+1.8V
VCC
AUX+3.3V
3.3V
C7
0.1uF
1
2
+ C37
TANC_47uF
1
2
R16
D
o
N
o
t P
o
p
u
la
te
1
2
C28
0.1uF
1
2
C16
0.1uF
1
2
C15
0.1uF
1
2
C38
0.1uF
1
2
C9
0.1uF
1
2
C39
0.1uF
1
2
C22
0.1uF
1
2
C40
0.1uF
1
2
C13
0.1uF
1
2
+ C2
TANB_10uF
1
2
C41
0.1uF
1
2
+ C46
TANC_47uF
1
2
C11
0.1uF
1
2
U4
TPS76718QPWP
3
5
6
7 13
14
15
16
1
2
9
10 11
12
19
20
4
8
18
17
GND
EN
IN
IN OUT
OUT
FB
RST
GND/HS
GND/HS
GND/HS
GND/HS GND/HS
GND/HS
GND/HS
GND/HS
NC
NC
NC
NC
C42
0.1uF
1
2
R18
D
o
N
o
t P
o
p
u
la
te
1
2
C51
0.1uF
1
2
C43
0.1uF
1
2
C52
0.1uF
1
2
C44
0.1uF
1
2
C53
0.1uF
1
2
C45
0.1uF
1
2
C54
0.1uF
1
2
J3
RAPC712
1
2
C19
0.1uF
1
2
C5
0.1uF
1
2
C18
0.1uF
1
2
C23
0.1uF
1
2
C10
0.1uF
1
2
+ C47
TANC_47uF
1
2
R17
270K 10%
1
2
C29
0.1uF
1
2
+ C48
TANC_47uF
1
2
+ C3
TANC_22uF
1
2
C8
0.1uF
1
2
C14
0.1uF
1
2
+ C49
TANC_47uF
1
2
+ C4
TANC_22uF
1
2
+ C30
TANC_47uF
1
2
C6
0.1uF
1
2
+ C50
TAND_470uF
1
2
+ C31
TANC_47uF
1
2
C27
0.1uF
1
2
JP4
HEADER 3
123
U3 L4955V3.3
1
2
3
4
IN
G
N
D
OUT
T
A
B
+ C32
TANC_47uF
1
2
C24
0.1uF
1
2
C20
0.1uF
1
2
+ C33
TANC_47uF
1
2
C25
0.1uF
1
2
+ C34
TANC_47uF
1
2
C21
0.1uF
1
2
+ C35
TANC_47uF
1
2
C17
0.1uF
1
2
C26
0.1uF
1
2
+ C36
TANC_47uF
1
2
C12
0.1uF
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
NOT POPULATED
N
O
T

P
O
P
U
L
A
T
E
D
H394-XLX5-MVE-1002
A
Mini-Virtex-E Board - Connectors
B
4 Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
ADDRESS18
ADDRESS12
ADDRESS8
ADDRESS0 ADDRESS1
ADDRESS30
ADDRESS20
ADDRESS28
ADDRESS16
ADDRESS3
ADDRESS9
ADDRESS4
ADDRESS26
ADDRESS16
ADDRESS7
ADDRESS22
ADDRESS21
ADDRESS22
ADDRESS10 ADDRESS5
ADDRESS28
ADDRESS27
ADDRESS7
ADDRESS1
ADDRESS13
ADDRESS23
ADDRESS9
ADDRESS2
ADDRESS10
ADDRESS8
ADDRESS26
ADDRESS4
ADDRESS13
ADDRESS20
ADDRESS11
ADDRESS19
ADDRESS11
ADDRESS24
ADDRESS5
ADDRESS15
ADDRESS12
ADDRESS17
ADDRESS0
ADDRESS25
ADDRESS6
ADDRESS29
ADDRESS14
ADDRESS31
ADDRESS2
ADDRESS6
ADDRESS30 ADDRESS14
ADDRESS18
ADDRESS3
ADDRESS24
DATA4
DATA13
DATA9
DATA8
DATA3
DATA6
DATA22
DATA11
DATA16
DATA31
DATA12
DATA11
DATA5
DATA25
DATA0
DATA10
DATA7
DATA14
DATA18
DATA10
DATA20
DATA5
DATA22
DATA30
DATA0
DATA13
DATA2
DATA1
DATA14
DATA3
DATA9
DATA16
DATA17
DATA2
DATA19
DATA24
DATA23
DATA8
DATA30
DATA26
DATA6
DATA27
DATA15
DATA1
DATA28
DATA24
DATA29 DATA18
DATA28
DATA12
DATA21
DATA7
DATA26
DATA20
DATA4
ADDRESS15
ADDRESS17
ADDRESS19
ADDRESS21
ADDRESS23
ADDRESS25
ADDRESS27
ADDRESS29
ADDRESS31
DATA15
DATA17
DATA19
DATA21
DATA23
DATA25
DATA27
DATA29
DATA31
CNTL14
CNTL2
CNTL16
CNTL17
CNTL7
CNTL10
CNTL12
CNTL6
CNTL6
CNTL13
CNTL4
CNTL0
CNTL15
CNTL3
CNTL15
CNTL1
CNTL7
CNTL19
CNTL17
CNTL5
CNTL0
CNTL3
CNTL4
CNTL10
CNTL20
SWITCH9
CNTL1
CNTL19
SWITCH8
CNTL13
CNTL2
CNTL8
CNTL9
CNTL11
CNTL5
CNTL11
CNTL12
CNTL14
CNTL18
CNTL9
CNTL16
CNTL8
CNTL18
CNTL20
ADDRESS[0:31] ADDRESS[0:31]
OSC
CLK_OUT
GCK3
GCK1
DATA[0:31]
DATA[0:31]
CNTL[0:20]
CNTL[0:20]
CNTL[0:20]
CNTL[0:20]
SWITCH[0:9]
DOUT
TEMP_SCLK
RS232RX
CLK_OUT
TEMP_SDO
RS232TX
RS232EN_N
TEMP_SDI
RS232SD_N
TEMP_CE
CLK_IN
CLK_OUT
CLK_IN
OSC
C
L
K
_
O
U
T
_
F
B
G
C
K
1
G
C
K
3
DOUT
CNTL[0:20]
GCK1_FB
OSC_FB
J5
MICTOR(AMP 2-767004-2)
1 2
3 4
5
6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
3
9
4
0
4
1
4
2
4
3
n/c n/c
GND n/c
CLK:0/Q0
CLK:1/Q1
A/D3:7 A/D1:7
A/D3:6 A/D1:6
A/D3:5 A/D1:5
A/D3:4 A/D1:4
A/D3:3 A/D1:3
A/D3:2 A/D1:2
A/D3:1 A/D1:1
A/D3:0 A/D1:0
A/D2:7 A/D0:7
A/D2:6 A/D0:6
A/D2:5 A/D0:5
A/D2:4 A/D0:4
A/D2:3 A/D0:3
A/D2:2 A/D0:2
A/D2:1 A/D0:1
A/D2:0 A/D0:0
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
R19
0R0/0805
1 2
J4
MICTOR(AMP 2-767004-2)
1 2
3 4
5
6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
3
9
4
0
4
1
4
2
4
3
n/c n/c
GND n/c
CLK:0/Q0
CLK:1/Q1
A/D3:7 A/D1:7
A/D3:6 A/D1:6
A/D3:5 A/D1:5
A/D3:4 A/D1:4
A/D3:3 A/D1:3
A/D3:2 A/D1:2
A/D3:1 A/D1:1
A/D3:0 A/D1:0
A/D2:7 A/D0:7
A/D2:6 A/D0:6
A/D2:5 A/D0:5
A/D2:4 A/D0:4
A/D2:3 A/D0:3
A/D2:2 A/D0:2
A/D2:1 A/D0:1
A/D2:0 A/D0:0
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
R21
0R0/0805
1 2
J6
MICTOR(AMP 2-767004-2)
1 2
3 4
5
6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
3
9
4
0
4
1
4
2
4
3
n/c n/c
GND n/c
CLK:0/Q0
CLK:1/Q1
A/D3:7 A/D1:7
A/D3:6 A/D1:6
A/D3:5 A/D1:5
A/D3:4 A/D1:4
A/D3:3 A/D1:3
A/D3:2 A/D1:2
A/D3:1 A/D1:1
A/D3:0 A/D1:0
A/D2:7 A/D0:7
A/D2:6 A/D0:6
A/D2:5 A/D0:5
A/D2:4 A/D0:4
A/D2:3 A/D0:3
A/D2:2 A/D0:2
A/D2:1 A/D0:1
A/D2:0 A/D0:0
G
N
D
G
N
D
G
N
D
G
N
D
G
N
D
R22
0R0/0805
1 2
JP5
2-102977-5
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
R23
0R0/0805
1 2
R20
0R0/0805
1 2
JP6
2-102977-5
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
R25
0R0/0805
1
2
R26
0R0/0805
1
2R24
0R0/0805
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H394-XLX5-MVE-1002
A
Mini-Virtex-E Board - Switch, LED, OSC
B
5 Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
L
E
D
0
L
E
D
2
L
E
D
3
L
E
D
5
L
E
D
6
L
E
D
1
L
E
D
4
L
E
D
7
SWITCH2
SWITCH5
SWITCH8
SWITCH0
SWITCH1
SWITCH7
SWITCH3
SWITCH6
SWITCH4
SWITCH9
LED[0:7]
SWITCH[0:9]
OSC
RS232TX
RS232RX
RS232SD_N
RS232EN_N
TEMP_CE
TEMP_SDO
TEMP_SDI TEMP_SCLK
SEG1_F
SEG1_G
SEG1_A
SEG1_B
SEG1_E
SEG1_D
SEG1_C
SEG1_Dp
SEG2_E
SEG2_D
SEG2_G
SEG2_C
SEG2_Dp
SEG2_B
SEG2_F
SEG2_A
IR_TXD
IR_RXD
IR_SHDN
VCC
VCC
VCC
VCC
VCC
VCC
R29 10K
1 2
R49
0R0/0805
1 2
D9
Q
T
L
P
6
5
0
C
-
2
+ C58
4.7uF, TAN
1
2
R28 10K
1 2
R27 10K
1 2
S1
3-435640-9
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
U7
MAN6141C
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
17
18
19
20
E1
D1
C1
Dp1
E2
D2
G2
C2
Dp2
B2 A2
F2
S2
S1
B1
A1
G1
F1
N/C1
N/C2
C55
0.1uF
1
2
C60
0.1uF
1
2
R34
1K
1
2
R39 10K
1 2
SW1
7914J-1-000E
3
1
4
2
D6
Q
T
L
P
6
5
0
C
-
2
R38
1K
1
2
R43 10K
1 2
R50
220
1 2
R52
220
1 2
OSC
U5
OSC/SOCKET
8
1
4
5
VCC
ENABLE
GND
OUT
C61
0.1uF
1 2
R41 10K
1 2
R54
220
1 2
C62
0.1uF
1 2
R44 10K
1 2
R53
220
1 2
R56
220
1 2
R45 10K
1 2
R55
220
1 2
R58
220
1 2
U9
DS1722U
1
2
3
4 5
6
7
8
VDDD
CE
SCLK
GND SDO
SDI
SERMODE
VDDA
R30 10K
1 2
R57
220
1 2
R61
220
1 2
R46
1206, 1.8R
1
2
D3
Q
T
L
P
6
5
0
C
-
2
R35
1K
1
2
SW2
7914J-1-000E
3
1
4
2
R59
220
1 2
R64
220
1 2
C56
0.1uF
1
2
R47
1206, 1.8R
1
2
R31
1K
1
2
R48 10K
1 2
R60
220
1 2
R65
220
1 2
C57
0.1uF
1
2
D7
Q
T
L
P
6
5
0
C
-
2
R63
220
1 2
R66
220
1 2
R40 0R0/0805
1 2
U8
ADM3222ARS
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EN
C1+
V+
C1-
C2+
C2-
V-
T2OUT
R2IN
R2OUT
SD
VCC
GND
T1OUT
R1IN
R1OUT
n/c
T1IN
T2IN
n/c
P1
747844-6
5
9
4
8
3
7
2
6
1
R32
1K
1
2
D2
Q
T
L
P
6
5
0
C
-
2
R42
Do Not Populate
1 2
R51
220
1 2
D4
Q
T
L
P
6
5
0
C
-
2
R36
1K
1
2
U6
TFDU6101E
1
2
6
8 7
5
4
3
LEDA
LEDC
VCC
GND Mode
SHDN
RXD
TXD
D8
Q
T
L
P
6
5
0
C
-
2
R67
DO NOT POPULATE
1
2
R62
0R0/0805
1
2
C59
0.1uF
1 2
C63
0.1uF
1 2
R33
1K
1
2
D5
Q
T
L
P
6
5
0
C
-
2
R37
1K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NOT POPULATED
NOT POPULATED
NOT POPULATED
H394-XLX5-MVE-1002 A
Mini-Virtex-E Board - Daughter Board Connector
B
6 Tuesday, October 17, 2000 6
Title
Size Document Number Rev
Date: Sheet of
Avnet, Inc. Design Services Copyright 2000
ADDRESS15
ADDRESS9
ADDRESS1
ADDRESS8
ADDRESS21
ADDRESS28
ADDRESS4
ADDRESS23
ADDRESS20
ADDRESS24
ADDRESS25
ADDRESS3
ADDRESS0
ADDRESS16
ADDRESS11
ADDRESS26
ADDRESS5
ADDRESS13
ADDRESS27
ADDRESS19
ADDRESS7
ADDRESS31
ADDRESS17
ADDRESS12
ADDRESS6
ADDRESS2
ADDRESS10
ADDRESS14
ADDRESS18
ADDRESS22
ADDRESS29
ADDRESS30
DATA6
DATA22
DATA18
DATA9
DATA25
DATA10
DATA17
DATA21
DATA2
DATA1
DATA30
CNTL0
CNTL3
CNTL4
CNTL7
CNTL8
CNTL11
CNTL12
CNTL15
CNTL16
CNTL19
CNTL20
CNTL1
CNTL2
CNTL5
CNTL6
CNTL9
CNTL10
CNTL13
CNTL14
CNTL17
CNTL18
DATA15
DATA27
DATA4
DATA5
DATA19
DATA12
DATA8
DATA7
DATA28
DATA16
DATA24
DATA0
DATA11
DATA31
DATA3
DATA20
DATA13
DATA29
DATA14
DATA23
DATA26
ADDRESS[0:31]
DATA[0:31]
CNTL[0:20]
CNTL[0:20]
CLK_OUT
CLK_IN
CLK_OUT_FB
JTAG_TMS
JTAG_TDI
JTAG_TRS
JTAG_TDO
JTAG_TCK
DATA[0:31]
AUX+3.3V
R68
0R0/0805
1 2
R70
0R0/0805
1 2
P2
5-179010-6
1
4
2
3
5
6
8
9
7
10
11
12
13
14
15
17
18
20
21
23
24
16
19
22
25
26
27
29
30
32
33
28
31
34
35
36
37
71
72
75
78
73
74
76
77
79
80
82
83
85
86
88
89
91
92
94
95
97
98
100
101
103
104
106
107
81
84
87
93
96
99
105
90
102
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
38
39
40
41
42
43
44
45
46
47
48
50
51
52
53
54
55
56
57
58
59
60
62
63
64
65
66
67
68
69
70
61
49
+5V
GND
IO
IO
IO
IO
IO
IO
GND
GND
IO
IO
+5V
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
GND
+5V
IO
IO
IO
IO
IO
IO
GND
GND
GND
IO
IO
+5V
IO
GND
GND
+3.3V
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
GND
GND
GND
GND
GND
GND
GND
+3.3V
+3.3V
GND
IO
IO
GND
IO
IO
+3.3V
IO
IO
GND
IO
IO
GND
IO
IO
GND
IO
IO
+3.3V
IO
IO
GND
IO
IO
GND
IO
IO
GND
IO
TMS
+3.3V
TDI
TRST
IO
IO
GND
IO
IO
GND
IO
IO
GND
IO
IO
IO
IO
GND
IO
IO
GND
IO
IO
GND
IO
IO
IO
IO
GND
IO
IO
GND
TDO
TCK
GND
+5V
+5V
R69 0R0/0805
1 2