Moore Machine

Mealy Machine
ReadOnly Memory (ROM)
Serial-to-Parallel Converter Counting Bits
Serial-to-Parallel Converter Shifting Bits
Programmale !ogic "rray (P!")
Ing. Amador Humberto Vivar Recarte VHDL : Sistemas Digitales II
#stado
Presente
#stado
Siguiente
Salida
($)
%&' %&( %&'
S'
S(
S)
S*
S' S)
S' S)
S) S*
S* S(
'
(
(
'
Mquina de Moore
+igure "( es un diagrama de una sencilla m,-uina de Moore.
/iene una entrada (X)0 cuatro estados internos (S0 a S3)0 y
una salida (Z).
Figure A1 Especificaciones de la mquina de Moore
'
S'
'
'
(
S(
(
S)
(
(
'
( (
S*
'
'
#l c1digo 234! -ue im5lementa 6sta m,-uina de estado finito es mostrado en el #7em5lo
"-(0 -ue incluye un es-uema del circuito sinteti8ado.
!a m,-uina se descrie con dos 5rocesos. 9n 5roceso define los elementos
sincr1nicos de dise:o (registros de estado); el otro 5roceso define la 5arte
cominacional del dise:o (sentencia case asignaci1n de estados).
Example A1 Implementacin de una mquina de Moore
entity MOORE is Moore machine
port(X, CLOCK: in B!"
Z: o#t B!$"
en%"
architect#re BE&'(OR o) MOORE is
type S!'!E*!+,E is (S0, S-, S., S3$"
si/na0 C1RRE2!*S!'!E, 2EX!*S!'!E: S!'!E*!+,E"
3e/in
,rocess to ho0% com3inationa0 0o/ic
COMB2: process(C1RRE2!*S!'!E, X$
3e/in
case C1RRE2!*S!'!E is
4hen S0 56
Z 75 808"
i) X 5 808 then
2EX!*S!'!E 75 S0"
e0se
2EX!*S!'!E 75 S."
en% i)"
4hen S- 56
Z 75 8-8"
i) X 5 808 then
2EX!*S!'!E 75 S0"
e0se
2EX!*S!'!E 75 S."
en% i)"
4hen S. 56
Z 75 8-8"
i) X 5 808 then
2EX!*S!'!E 75 S."
e0se
2EX!*S!'!E 75 S3"
en% i)"
4hen S3 56
Z 75 808"
i) X 5 808 then
2EX!*S!'!E 75 S3"
e0se
2EX!*S!'!E 75 S-"
en% i)"
en% case"
en% process"
,rocess to ho0% synchrono#s e0ements ()0ip)0ops$
S+2C&: process
3e/in
4ait #nti0 CLOCK8e9ent an% CLOCK 5 8-8"
C1RRE2!*S!'!E 75 2EX!*S!'!E"
en% process"
en% BE&'(OR"
Example A-1 (continuacin) Implementacin de una mquina de Moore
#stado
Presente
#stado
Siguiente
Salida
($)
%&' %&( %&'%&(
S'
S(
S)
S*
S' S)
S' S)
S) S*
S* S(
' (
' '
( '
' (
Mquina de Mealy
+igure ") es un diagrama de una sencilla m,-uina de Mealy.
/he 234! code to im5lement this finite-state machine is
sho<n in #=am5le "). /he machine is descried in t<o
5rocesses0 li>e the 5revious Moore machine e=am5le.
Figure A! Meal" Mac#ine $pecification
'?'
S'
'?'
(?(
S(
(?'
S)
(?(
S*
'?'
(?'
'?(
Example A! Implementacin de una mquina de Meal"
entity ME'L+ is Mea0y machine
port(X, CLOCK: in B!"
Z: o#t B!$"
en%"
architect#re BE&'(OR o) ME'L+ is
type S!'!E*!+,E is (S0, S-, S., S3$"
si/na0 C1RRE2!*S!'!E, 2EX!*S!'!E: S!'!E*!+,E"
3e/in
,rocess to ho0% com3inationa0 0o/ic:
COMB2: process(C1RRE2!*S!'!E, X$
3e/in
case C1RRE2!*S!'!E is
4hen S0 56
i) X 5 808 then
Z 75 808"
2EX!*S!'!E 75 S0"
e0se
Z 75 8-8"
2EX!*S!'!E 75 S."
en% i)"
4hen S- 56
i) X 5 808 then
Z 75 808"
2EX!*S!'!E 75 S0"
e0se
Z 75 808"
2EX!*S!'!E 75 S."
en% i)"
4hen S. 56
i) X 5 808 then
Z 75 8-8"
2EX!*S!'!E 75 S."
e0se
Z 75 808"
2EX!*S!'!E 75 S3"
en% i)"
4hen S3 56
i) X 5 808 then
Z 75 808"
2EX!*S!'!E 75 S3"
e0se
Z 75 8-8"
2EX!*S!'!E 75 S-"
en% i)"
en% case"
en% process"
,rocess to ho0% synchrono#s e0ements ()0ip)0ops$
S+2C&: process
3e/in
4ait #nti0 CLOCK8e9ent an% CLOCK 5 8-8"
C1RRE2!*S!'!E 75 2EX!*S!'!E"
en% process"
en% BE&'(OR"
Example A-! (continued) Implementation of a Meal" Mac#ine
Memoria de Solo Lectura. Read!nly Memory "R!M#
#=am5le "* muestra como 5uede ser definida en 234! una ROM.
!a ROM es definida como un arreglo o array constante. Cada l@nea de
es5ecificaci1n del array constante define el contenido de direcci1n de
una ROM.
Para !eer la ROM0 sim5lemente inde=amos dentro del array.
/he ROMAs numer of storage locations and it <idth can e
easily changed. /he suty5e ROM*R'2;E s5ecifies that the
ROM contains storage locations 0 to <. /he constant
ROM*=>!& s5ecifies that the ROM is five its <ide.
"fter you define a ROM constant0 you can inde= into that
constant many times to read many values from the ROM. Bf
the ROM address is com5utale (see CCCom5utale O5er-
andsD in Cha5ter E)0 no logic is uilt. /he a55ro5riate data
value is sim5ly inserted. Bf the ROM address is not com5ut-
ale0 logic is uilt for each inde= into the value. +or this rea-
son0 you need to consider resource sharing <hen using a
ROM (see Cha5ter F0 CCResource SharingD). Bn the e=am5le0
'>>R is not com5utale0 so logic is synthesi8ed to com5ute
the value.
234! Com5iler does not actually instantiate a ty5ical array-
logic ROM0 such as those availale from "SBC vendors.
Bnstead0 the ROM is created from random logic gates ("G40
OR0 GO/0 and so on). /his ty5e of im5lementation is 5refera-
le for small ROMs0 or for ROMs that are very regular. +or very
large ROMs0 consider using an array-logic im5lementation
su55lied y your "SBC vendor.
#=am5le "* sho<s the 234! source code and the synthe-
si8ed circuit schematic.
Example A% Implementation of a &'M in &andom (ogic
pac?a/e ROMS is
%ec0are a @AB ROM ca00e% ROM
constant ROM*=>!&: 2!E;ER :5 @"
s#3type ROM*=OR> is B!*(EC!OR (- to ROM*=>!&$"
s#3type ROM*R'2;E is 2!E;ER ran/e 0 to <"
type ROM*!'BLE is array (0 to <$ o) ROM*=OR>"
constant ROM: ROM*!'BLE :5 ROM*!'BLE8(
ROM*=OR>8(C-0-0-C$, ROM contents
ROM*=OR>8(C-0000C$,
ROM*=OR>8(C-----C$,
ROM*=OR>8(C-----C$,
ROM*=OR>8(C-0000C$,
ROM*=OR>8(C-0-0-C$,
ROM*=OR>8(C-----C$,
ROM*=OR>8(C-----C$$"
en% ROMS"
#se 4or?:ROMS:a00" Entity that #ses ROM
entity ROM*@AB is
port('>>R: in ROM*R'2;E"
>'!': o#t ROM*=OR>$"
en%"
architect#re BE&'(OR o) ROM*@AB is
3e/in
>'!' 75 ROM('>>R$" Rea% )rom the ROM
en% BE&'(OR"
' ( ) * H E I J K F (' (( ()
$ave%orm &enerator
/his e=am5le sho<s ho< to use the 5revious ROM e=am5le to
im5lement a <aveform generator.
"ssume you <ant to 5roduce the <aveform out5ut sho<n in
+igure "*. +irst0 declare a ROM <ide enough to hold the
out5ut signals (four its)0 and dee5 enough to hold all time
ste5s (' to ()0 for a total of (*).
Ge=t0 define the ROM so that each time ste5 is re5resented
y an entry in the ROM.
+inally0 create a counter that cycles through the time ste5s
(ROM addresses)0 generating the <aveform at each time
ste5.
Figure A% )a*eform Example
(
)
*
H
#=am5le "H sho<s an im5lementation for the <aveform
generator. Bt consists of a ROM0 a counter0 and some sim5le
reset logic.
Example A+ Implementation of a )a*eform ,enerator
pac?a/e ROMS is
a DA-3 ROM ca00e% ROM that contains the 4a9e)orm
constant ROM*=>!&: 2!E;ER :5 D"
s#3type ROM*=OR> is B!*(EC!OR (- to ROM*=>!&$"
s#3type ROM*R'2;E is 2!E;ER ran/e 0 to -."
type ROM*!'BLE is array (0 to -.$ o) ROM*=OR>"
constant ROM: ROM*!'BLE :5 ROM*!'BLE8(
C--00C, time step 0
C--00C, time step -
C0-00C, time step .
C0000C, time step 3
C0--0C, time step D
C0-0-C, time step @
C0---C, time step E
C--00C, time step <
C0-00C, time step B
C0000C, time step F
C0--0C, time step -0
C0-0-C, time step --
C0---C$" time step -.
en% ROMS"
#se 4or?:ROMS:a00"
entity ='(EGORM is =a9e)orm /enerator
port(CLOCK: in B!"
RESE!: in BOOLE'2"
='(ES: o#t ROM*=OR>$"
en%"
architect#re BE&'(OR o) ='(EGORM is
si/na0 S!E,: ROM*R'2;E"
3e/in
!MES!E,*CO12!ER: process !ime steppin/ process
3e/in
4ait #nti0 CLOCK8e9ent an% CLOCK 5 8-8"
i) RESE! then >etect reset
S!E, 75 ROM*R'2;E80o4" Restart
e0si) S!E, 5 ROM*R'2;E8hi/h then Ginishe%H
S!E, 75 ROM*R'2;E8hi/h" &o0% at 0ast 9a0#e
S!E, 75 ROM*R'2;E80o4" Contin#o#s 4a9e
e0se
S!E, 75 S!E, I -" Contin#e steppin/
en% i)"
en% process !MES!E,*CO12!ER"
='(ES 75 ROM(S!E,$"
en% BE&'(OR"
Example A-+ (continued) Implementation of a )a*eform ,enerator
Gote that <hen the counter S!E, reaches the end of the
ROM0 S!E, sto5s0 generates the last value0 then <aits until a
reset. /o ma>e the se-uence automatically re5eat0 remove
the statementL
S!E, 75 ROM*R'2;E8hi/h" &o0% at 0ast 9a0#e
and use the follo<ing statement instead (commented out in
#=am5le "H)L
S!E, 75 ROM*R'2;E80o4" Contin#o#s 4a9e
Smart $ave%orm &enerator
/his e=am5le is an e=tension of the <aveform generator in the
5revious e=am5le. /his smart <aveform generator is ca5ale
of holding the <aveform at any time ste5 for several cloc>
cycles.
+igure "H sho<s a <aveform similar to the <aveform of the
5revious e=am5le0 <here several of the time ste5s are held
for multi5le cloc> cycles.
Figure A+ )a*eform for $mart )a*eform ,enerator Example
' ( ) * H E I J K F (' (( ()
(
)
*
H
K' E )' E
/he im5lementation of the smart <aveform generator is
sho<n in #=am5le "E. Bt is similar to the <aveform generator
of the 5revious e=am5le0 ut <ith t<o additions. " ne< ROM0
>*ROM0 has een added to hold the length of each time ste5.
" value of - s5ecifies that the corres5onding time ste5 should
e one cloc> cycle long; a value of B0 s5ecifies that the time
ste5 should e K' cloc> cycles long. /he second addition to
the 5revious <aveform generator is a delay counter that
counts out the cloc> cycles et<een time ste5s.
Gote that in the architecture of this e=am5le0 a selected
signal assignment determines the value of the 2EX!*S!E,
counter.
Example A- Implementation of a $mart )a*eform ,enerator
pac?a/e ROMS is
a DA-3 ROM ca00e% =*ROM containin/ the 4a9e)orm
constant =*ROM*=>!&: 2!E;ER :5 D"
s#3type =*ROM*=OR> is B!*(EC!OR (- to =*ROM*=>!&$"
s#3type =*ROM*R'2;E is 2!E;ER ran/e 0 to -."
type =*ROM*!'BLE is array (0 to -.$ o) =*ROM*=OR>"
constant =*ROM: =*ROM*!'BLE :5 =*ROM*!'BLE8(
C--00C, time step 0
C--00C, time step -
C0-00C, time step .
C0000C, time step 3
C0--0C, time step D
C0-0-C, time step @
C0---C, time step E
C--00C, time step <
C0-00C, time step B
C0000C, time step F
C0--0C, time step -0
C0-0-C, time step --
C0---C$" time step -.
a <A-3 ROM ca00e% >*ROM containin/ the %e0ays
s#3type >*ROM*=OR> is 2!E;ER ran/e 0 to -00"
s#3type >*ROM*R'2;E is 2!E;ER ran/e 0 to -."
type >*ROM*!'BLE is array (0 to -.$ o) >*ROM*=OR>"
constant >*ROM: >*ROM*!'BLE :5 >*ROM*!'BLE8(
-,B0,@,-,-,-,-,.0,@,-,-,-,-$"
en% ROMS"
#se 4or?:ROMS:a00"
entity ='(EGORM is Smart =a9e)orm ;enerator
port(CLOCK: in B!" RESE!:
in BOOLE'2" ='(ES: o#t
=*ROM*=OR>$"
en%"
architect#re BE&'(OR o) ='(EGORM is
si/na0 S!E,, 2EX!*S!E,: =*ROM*R'2;E"
si/na0 >EL'+: >*ROM*=OR>"
3e/in
>etermine the 9a0#e o) the neAt time step
2EX!*S!E, 75 =*ROM*R'2;E8hi/h 4hen
e0se
S!E, 5 =*ROM*R'2;E8hi/h
S!E, I -"
Keep trac? o) 4hich time step 4e are in
!MES!E,*CO12!ER: process
3e/in
4ait #nti0 CLOCK8e9ent an% CLOCK 5 8-8"
i) RESE! then >etect reset
S!E, 75 0" Restart 4a9e)orm
e0si) >EL'+ 5 - then
S!E, 75 2EX!*S!E," Contin#e steppin/
e0se
n#00" =ait )or >EL'+ to co#nt %o4n"
en% i)" %o nothin/ here
en% process"
Co#nt the %e0ay 3et4een time steps:
>EL'+*CO12!ER: process
3e/in
4ait #nti0 CLOCK8e9ent an% CLOCK 5 8-8"
i) RESE! then >etect reset
>EL'+ 75 >*ROM(0$" Restart
e0si) >EL'+ 5 - then &a9e 4e co#nte% %o4nH
>EL'+ 75 >*ROM(2EX!*S!E,$" 2eAt %e0ay 9a0#e
e0se
>EL'+ 75 >EL'+ -" %ecrement >EL'+ co#nter
en% i)"
en% process"
='(ES 75 =*ROM(S!E,$" O#tp#t 4a9e)orm 9a0#e
en% BE&'(OR"
De%inable$idt' AdderSubtracter
234! lets you create functions for use <ith array o5erands of
any si8e. /his e=am5le sho<s an adder-sutracter circuit that0
<hen called0 is ad7usted to fit the si8e of its o5erands.
#=am5le "I sho<s an adder-sutracter defined for t<o
unconstrained arrays of its (ty5e B!*(EC!OR)0 in a 5ac>age
named M'!&. Mhen an unconstrained array ty5e is used for
an argument to a su5rogram0 the actual constraints of the
array are ta>en from the actual 5arameter values in a su-
5rogram call.
#=am5le "J sho<s ho< to use the addersutracter defined
in the M'!& 5ac>age. Bn this e=am5le the vector arguments
to functions 'R;- and 'R;. are declared as B!*(EC!OR(- to
E$. /his declaration causes '>>*S1B to <or> <ith si=-it arrays.
" schematic of the synthesi8ed circuit follo<s.
Example A. MA/0 1ac2age for Example A3
pac?a/e M'!& is
)#nction '>>*S1B(L, R: B!*(EC!OR" '>>: BOOLE'2$
ret#rn B!*(EC!OR"
'%% or s#3tract t4o B!*(EC!ORs o) eJ#a0 0en/th
en% M'!&"
pac?a/e 3o%y M'!& is
)#nction '>>*S1B(L, R: B!*(EC!OR" '>>: BOOLE'2$
ret#rn B!*(EC!OR is
9aria30e C'RR+: B!"
9aria30e ', B, S1M:
B!*(EC!OR(L80en/th- %o4nto 0$"
3e/in
i) '>> then
,repare )or an Ca%%C operation
' :5 L"
B :5 R"
C'RR+ :5 808"
e0se
,repare )or a Cs#3tractC operation
' :5 L"
B :5 not R"
C'RR+ :5 8-8"
en% i)"
Create a ripp0ecarry chain" s#m #p 3its
)or i in 0 to '80e)t 0oop
S1M(i$ :5 '(i$ Aor B(i$ Aor C'RR+"
C'RR+ :5 ('(i$ an% B(i$$ or
('(i$ an% C'RR+$ or
(C'RR+ an% B(i$$"
en% 0oop"
ret#rn S1M" Res#0t
en%"
en% M'!&"
Mithin the function '>>*S1B0 t<o tem5orary variales0 ' and
B0 are declared. /hese variales are declared to e the
same length as L (and necessarily0 R)0 ut have their inde=
constraints normali8ed to L80en/th- %o4nto 0. "fter the
arguments are normali8ed0 you can create a ri55le-carry
adder y using a )or loo5.
Gote that no e=5licit references to a fi=ed array length are in
the function '>>*S1B. Bnstead0 the 234! array attriutes 80e)t
and 80en/th are used. /hese attriutes allo< the function to
<or> on arrays of any length.
Example A3 Implementation of a $ix-4it Adder-$u5tracter
#se 4or?:M'!&:a00"
entity EX'M,LE is
port('R;-, 'R;.: in B!*(EC!OR(- to E$"
'>>: in BOOLE'2"
RES1L! : o#t B!*(EC!OR(- to E$$"
en% EX'M,LE"
architect#re BE&'(OR o) EX'M,LE is
3e/in
RES1L! 75 '>>*S1B('R;-, 'R;., '>>$"
en% BE&'(OR"
(ount )eros*(ombinational Version
/his e=am5le illustrates a design 5rolem <here an eight-it-
<ide value is given0 and the circuit determines t<o thingsL
/hat no more than one se-uence of 's is in the value.
/he numer of 's in that se-uence (if any). /his com-
5utation must e com5leted in a single cloc> cycle.
/he circuit 5roduces t<o out5utsL the numer of 8eros found0
and an error indication.
" legal in5ut value can have at most one consecutive series
of 8eros. " value consisting entirely of ones is defined as a
legal value. Bf a value is illegal0 the 8ero counter resets to '.
+or e=am5le0 the value 00000000 is legal and has eight 8eros;
value --000--- is legal and has three 8eros; value 00----00 is
not legal.
#=am5le "K sho<s the 234! descri5tion for the circuit. Bt
consists of a single 5rocess <ith a )or loo5 that iterates across
each it in the given value. "t each iteration0 a tem5orary
2!E;ER variale (!EM,*CO12!) counts the numer of 8eros
encountered. /<o tem5orary BOOLE'2 variales (SEE2*ZERO
and SEE2*!R'L2;)0 initially G'LSE0 are set to !R1E <hen the
eginning and end of the first se-uence of 8eros is detected.
Bf a 8ero is detected after the end of the first se-uence of
8eros (after SEE2*!R'L2; is !R1E)0 the 8erocount is reset
(to
')0 ERROR is set to !R1E0 and the )or loo5 is e=ited.
/his e=am5le sho<s a cominational (5arallel) a55roach to
counting the 8eros. /he ne=t e=am5le sho<s a se-uential
(serial) a55roach.
Example A6 7ount 8eros97om5inational
entity CO12!*COMB*(&>L is
port(>'!': in B!*(EC!OR(< %o4nto 0$"
CO12!: o#t 2!E;ER ran/e 0 to B"
ERROR: o#t BOOLE'2$"
en%"
architect#re BE&'(OR o) CO12!*COMB*(&>L is
3e/in
process(>'!'$
9aria30e !EM,*CO12! : 2!E;ER ran/e 0 to B"
9aria30e SEE2*ZERO, SEE2*!R'L2; : BOOLE'2"
3e/in
ERROR 75 G'LSE"
SEE2*ZERO :5 G'LSE"
SEE2*!R'L2; :5 G'LSE"
!EM,*CO12! :5 0"
)or in 0 to < 0oop
i) (SEE2*!R'L2; an% >'!'($ 5 808$ then
!EM,*CO12! :5 0"
ERROR 75 !R1E"
eAit"
e0si) (SEE2*ZERO an% >'!'($ 5 8-8$ then
SEE2*!R'L2; :5 !R1E"
e0si) (>'!'($ 5 808$ then
SEE2*ZERO :5 !R1E"
!EM,*CO12! :5 !EM,*CO12! I -"
en% i)"
en% 0oop"
CO12! 75 !EM,*CO12!"
en% process"
en% BE&'(OR"
Example A-6 (continued) 7ount 8eros97om5inational
(ount )eros*Sequential Version
/his e=am5le sho<s a se-uential (cloc>ed) variant of the
5receding design (Count $erosCominational 2ersion).
/he circuit no< acce5ts the eight-it data value serially0 one
it 5er cloc> cycle0 y using the >'!' and CLK in5uts. /he
other t<o in5uts are
RESE!0 <hich resets the circuit.
RE'>0 <hich causes the circuit to egin acce5ting data
its.
/he circuitAs three out5uts are
S*LE;'L0 <hich is !R1E if the data <as a legal value.
CO12!*RE'>+0 <hich is !R1E at the first illegal it or <hen all
eight its have een 5rocessed.
CO12!0 the numer of 8eros (if S*LE;'L is !R1E).
Gote that the out5ut 5ort CO12! is declared <ith mode
B1GGER so that it can e read inside the 5rocess. O1! 5orts
can only e <ritten to0 not read.
Example A: 7ount 8eros9$equential
entity CO12!*SEK*(&>L is
port(>'!', CLK: in B!"
RESE!, RE'>: in BOOLE'2"
CO12!: 3#))er 2!E;ER ran/e 0 to B"
S*LE;'L: o#t BOOLE'2"
CO12!*RE'>+: o#t BOOLE'2$"
en%"
architect#re BE&'(OR o) CO12!*SEK*(&>L is
3e/in
process
9aria30e SEE2*ZERO, SEE2*!R'L2;: BOOLE'2"
9aria30e B!S*SEE2: 2!E;ER ran/e 0 to <"
3e/in
4ait #nti0 CLK8e9ent an% CLK 5 8-8"
i)(RESE!$ then
CO12!*RE'>+ 75 G'LSE"
S*LE;'L 75 !R1E"
SEE2*ZERO :5 G'LSE"
SEE2*!R'L2; :5 G'LSE"
CO12! 75 0"
B!S*SEE2 :5 0"
e0se
i) (RE'>$ then
i) (SEE2*!R'L2; an% >'!' 5 808$ then
S*LE;'L 75 G'LSE"
CO12! 75 0"
CO12!*RE'>+ 75 !R1E"
e0si) (SEE2*ZERO an% >'!' 5 8-8$ then
SEE2*!R'L2; :5 !R1E"
e0si) (>'!' 5 808$ then
SEE2*ZERO :5 !R1E"
CO12! 75 CO12! I -"
en% i)"
i) (B!S*SEE2 5 <$ then
CO12!*RE'>+ 75 !R1E"
e0se
B!S*SEE2 :5 B!S*SEE2 I -"
en% i)"
en% i)" i) (RE'>$
en% i)" i) (RESE!$
en% process"
en% BE&'(OR"
Example A-: (continued) 7ount 8eros9$equential
So%t Drin+ Mac'ine*State Mac'ine Version
/his e=am5le is a control unit for a soft drin> vending machine.
/he circuit reads signals from a coin in5ut unit and sends
out5uts to a change dis5ensing unit and a drin> dis5ensing
unit. /his e=am5le assumes that only one >ind of soft drin> is
dis5ensed.
/his is a cloc>ed design <ith CLK and RESE! in5ut signals.
/he 5rice of the drin> is *E cents. Bn5ut signals from the coin
in5ut unit are 2CKEL*2 (nic>el de5osited)0 >ME*2 (dime
de5osited)0 and K1'R!ER*2 (-uarter de5osited).
Out5ut signals to the change dis5ensing unit are 2CKEL*O1!
and >ME*O1!.
/he out5ut signal to the drin> dis5ensing unit is >S,E2SE
(dis5ense drin>).
/he first 234! descri5tion for this design uses a state
machine descri5tion style. /he second 234! descri5tion is in
the ne=t e=am5le section.
Example A1; $oft <rin2 Mac#ine9$tate Mac#ine
0i3rary synopsys" #se synopsys:attri3#tes:a00"
entity >R2K*S!'!E*(&>L is
port(2CKEL*2, >ME*2, K1'R!ER*2, RESE!: BOOLE'2"
CLK: B!"
2CKEL*O1!, >ME*O1!, >S,E2SE: o#t BOOLE'2$"
en%"
architect#re BE&'(OR o) >R2K*S!'!E*(&>L is
type S!'!E*!+,E is (>LE, G(E, !E2, GG!EE2,
!=E2!+, !=E2!+*G(E, !&R!+, O=E*>ME$"
si/na0 C1RRE2!*S!'!E, 2EX!*S!'!E: S!'!E*!+,E"
attri3#te S!'!E*(EC!OR : S!R2;"
attri3#te S!'!E*(EC!OR o) BE&'(OR : architect#re is
CC1RRE2!*S!'!EC"
attri3#te sync*sync*reset o) reset : si/na0 is Ctr#eC"
3e/in
process(2CKEL*2, >ME*2, K1'R!ER*2,
C1RRE2!*S!'!E, RESE!, CLK$
3e/in
>e)a#0t assi/nments
2EX!*S!'!E 75 C1RRE2!*S!'!E"
2CKEL*O1! 75 G'LSE"
>ME*O1! 75 G'LSE"
>S,E2SE 75 G'LSE"
Synchrono#s reset
i)(RESE!$ then
2EX!*S!'!E 75 >LE"
e0se
State transitions an% o#tp#t 0o/ic
case C1RRE2!*S!'!E is
4hen >LE 56
i)(2CKEL*2$ then
2EX!*S!'!E 75 G(E"
e0si)(>ME*2$ then
2EX!*S!'!E 75 !E2"
e0si)(K1'R!ER*2$ then
2EX!*S!'!E 75 !=E2!+*G(E"
en% i)"
4hen G(E 56
i)(2CKEL*2$ then
2EX!*S!'!E 75 !E2"
e0si)(>ME*2$ then
2EX!*S!'!E 75 GG!EE2"
e0si)(K1'R!ER*2$ then
2EX!*S!'!E 75 !&R!+"
en% i)"
4hen !E2 56
i)(2CKEL*2$ then
2EX!*S!'!E 75 GG!EE2"
e0si)(>ME*2$ then
2EX!*S!'!E 75 !=E2!+"
e0si)(K1'R!ER*2$ then
2EX!*S!'!E 75 >LE"
>S,E2SE 75 !R1E"
en% i)"
4hen GG!EE2 56
i)(2CKEL*2$ then
2EX!*S!'!E 75 !=E2!+"
e0si)(>ME*2$ then
2EX!*S!'!E 75 !=E2!+*G(E"
e0si)(K1'R!ER*2$ then
2EX!*S!'!E 75 >LE"
>S,E2SE 75 !R1E"
2CKEL*O1! 75 !R1E"
en% i)"
4hen !=E2!+ 56
i)(2CKEL*2$ then
2EX!*S!'!E 75 !=E2!+*G(E"
e0si)(>ME*2$ then
2EX!*S!'!E 75 !&R!+"
e0si)(K1'R!ER*2$ then
2EX!*S!'!E 75 >LE"
>S,E2SE 75 !R1E"
>ME*O1! 75 !R1E"
en% i)"
4hen !=E2!+*G(E 56
i)(2CKEL*2$ then
2EX!*S!'!E 75 !&R!+"
e0si)(>ME*2$ then
2EX!*S!'!E 75 >LE"
>S,E2SE 75 !R1E"
e0si)(K1'R!ER*2$ then
2EX!*S!'!E 75 >LE"
>S,E2SE 75 !R1E"
>ME*O1! 75 !R1E"
2CKEL*O1! 75 !R1E"
en% i)"
4hen !&R!+ 56
i)(2CKEL*2$ then
2EX!*S!'!E 75 >LE"
>S,E2SE 75 !R1E"
e0si)(>ME*2$ then
2EX!*S!'!E 75 >LE"
>S,E2SE 75 !R1E"
2CKEL*O1! 75 !R1E"
e0si)(K1'R!ER*2$ then
2EX!*S!'!E 75 O=E*>ME"
>S,E2SE 75 !R1E"
>ME*O1! 75 !R1E"
en% i)"
4hen O=E*>ME 56
2EX!*S!'!E 75 >LE"
>ME*O1! 75 !R1E"
en% case"
en% i)"
en% process"
SynchroniLe state 9a0#e 4ith c0oc?:
!his ca#ses it to 3e store% in )0ip )0ops
process
3e/in
4ait #nti0 CLK8e9ent an% CLK 5 8-8"
C1RRE2!*S!'!E 75 2EX!*S!'!E"
en% process"
en% BE&'(OR"
So%t Drin+ Mac'ine*(ount ,ic+els Version
/his e=am5le uses the same design 5arameters as the 5re-
ceding e=am5le (Soft 4rin> Machine State Machine 2er-
sion) <ith the same in5ut and out5ut signals.
Bn this version0 a counter counts the numer of nic>els de5os-
ited. /his counter is incremented y ( if the de5osit is a nic>el0
y ) if it is a dime0 and y E if it is a -uarter.
Example A11 $oft <rin2 Mac#ine97ount =ic2els
entity >R2K*CO12!*(&>L is
port(2CKEL*2, >ME*2, K1'R!ER*2, RESE!: BOOLE'2"
CLK: B!"
2CKEL*O1!, >ME*O1!, >S,E2SE: o#t BOOLE'2$"
en%"
architect#re BE&'(OR o) >R2K*CO12!*(&>L is
si/na0 C1RRE2!*2CKEL*CO12!,
2EX!*2CKEL*CO12!: 2!E;ER ran/e 0 to <"
si/na0 C1RRE2!*RE!1R2*C&'2;E, 2EX!*RE!1R2*C&'2;E : BOOLE'2"
3e/in
process(2CKEL*2, >ME*2, K1'R!ER*2, RESE!, CLK,
C1RRE2!*2CKEL*CO12!, C1RRE2!*RE!1R2*C&'2;E$
9aria30e !EM,*2CKEL*CO12!: 2!E;ER ran/e 0 to -."
3e/in
>e)a#0t assi/nments
2CKEL*O1! 75 G'LSE"
>ME*O1! 75 G'LSE"
>S,E2SE 75 G'LSE"
2EX!*2CKEL*CO12! 75 0"
2EX!*RE!1R2*C&'2;E 75 G'LSE"
Synchrono#s reset
i) (not RESE!$ then
!EM,*2CKEL*CO12! :5 C1RRE2!*2CKEL*CO12!"
Chec? 4hether money has come in
i) (2CKEL*2$ then
2O!E: !his %esi/n 4i00 3e )0attene%, so
these m#0tip0e a%%ers 4i00 3e optimiLe%
!EM,*2CKEL*CO12! :5 !EM,*2CKEL*CO12! I -"
e0si)(>ME*2$ then
!EM,*2CKEL*CO12! :5 !EM,*2CKEL*CO12! I ."
e0si)(K1'R!ER*2$ then
!EM,*2CKEL*CO12! :5 !EM,*2CKEL*CO12! I @"
en% i)"
Eno#/h %eposite% so )arH
i)(!EM,*2CKEL*CO12! 65 <$ then
!EM,*2CKEL*CO12! :5 !EM,*2CKEL*CO12! <"
>S,E2SE 75 !R1E"
en% i)"
Ret#rn chan/e
i)(!EM,*2CKEL*CO12! 65 - or
C1RRE2!*RE!1R2*C&'2;E$ then
i)(!EM,*2CKEL*CO12! 65 .$ then
>ME*O1! 75 !R1E"
!EM,*2CKEL*CO12! :5 !EM,*2CKEL*CO12! ."
2EX!*RE!1R2*C&'2;E 75 !R1E"
en% i)"
i)(!EM,*2CKEL*CO12! 5 -$ then
2CKEL*O1! 75 !R1E"
!EM,*2CKEL*CO12! :5 !EM,*2CKEL*CO12! -"
en% i)"
en% i)"
Example A-11 (continued) $oft <rin2 Mac#ine97ount =ic2els
2EX!*2CKEL*CO12! 75 !EM,*2CKEL*CO12!"
en% i)"
en% process"
Remem3er the ret#rnchan/e )0a/ an%
the nic?e0 co#nt )or the neAt cyc0e
process
3e/in
4ait #nti0 CLK8e9ent an% CLK 5 8-8"
C1RRE2!*RE!1R2*C&'2;E 75 2EX!*RE!1R2*C&'2;E"
C1RRE2!*2CKEL*CO12! 75 2EX!*2CKEL*CO12!"
en% process"
en% BE&'(OR"
(arryLoo+a'ead Adder
/his e=am5le uses concurrent 5rocedure calls to uild a *)-it
carry-loo>ahead adder. /he adder is uilt y 5artitioning the
*)-it in5ut into eight slices of four its each. #ach of the
eight slices com5utes 5ro5agate and generate values y
using the ,; 5rocedure. +igure "E sho<s the overall struc-
ture.
Pro5agate (out5ut , from ,;) is 8-8 for a it 5osition if that
5osition 5ro5agates a carry from the ne=t lo<er 5osition to
the ne=t higher 5osition. Nenerate (out5ut ;) is 8-8 for a it
5osition if that 5osition generates a carry to the ne=t higher
5osition0 regardless of the carry-in from the ne=t lo<er 5osi-
tion.
/he carry-loo>ahead logic reads the carry-in0 5ro5agate0 and
generate information com5uted from the in5uts. Bt com5utes
the carry value for each it 5osition. /his logic ma>es the
addition o5eration 7ust an %OR of the in5uts and the carry
values.
(arry Value (om-utations
/he carry values are com5uted y a three-level tree of four-
it carry-loo>ahead loc>s.
(. /he first level of the tree com5utes the *) carry values
and the eight grou5-5ro5agate and generate values.
#ach of the first-level grou5-5ro5agate and generate
values tells if that four-it slice 5ro5agates and gener-
ates carry values from the ne=t lo<er grou5 to the ne=t
higher. /he first-level loo>ahead loc>s read the grou5
carry com5uted at the second level.
). /he second-level loo>ahead loc>s read the grou5-
5ro5agate and generate information from the four
first-level loc>s0 then com5ute their o<n grou5-5ro5a-
gate and generate information. /hey also read grou5
carry information com5uted at the third level to com-
5ute the carries for each of the third-level loc>s.
*. /he third-level loc> reads the 5ro5agate and generate
information of the second level to com5ute a 5ro5a-
gate and generate value for the entire adder. Bt also
reads the e=ternal carry to com5ute each second-level
carry. /he carry-out for the adder is 8-8 if the third-level
generate is 8-80 or if the third-level 5ro5agate is 8-8 and
the e=ternal carry is 8-8.
/he third-level carry-loo>ahead loc> is ca5ale of
5rocessing four second-level loc>s. Since there are only
t<o0 the high-order t<o its of the com5uted carry are
ignored0 the high-order t<o its of the generate in5ut to
the third-level are set to 8ero 000 and the 5ro5agate
high-order its are set to --. /hese settings cause the
unused 5ortion to 5ro5agate carries0 ut not to gener-
ate them.
Figure A- 7arr"-(oo2a#ead Adder 4loc2 <iagram (s#o>n on next page)
B "
firstlevel
loc>s
CBG
J CBG CO9/ *(L)K
secondlevel
" *(L)K
P
B *(L)K N
PN
P
(LA
NP J
N NN
J
loc>s
D((D
*L)
NNP
I
CBG CO9/ )JL)H
*L)
" )JL)H P
B )JL)H
N
PN
P
(LA
NP
N NN
I
I
(
CBG
D''D
CO9/
NNN
E
CBG CO9/ )*L)'
NP JLH
P
(LA
NP
(
" )*L)'
P
B )*L)'
N
PN
P
(LA
NP
N NN
E
NN JLH
N
E
NN
(
thirdlevel
H
CBG CO9/ (FL(I
loc>
" (FL(I P
B (FL(I N
PN
P
(LA
NP
H
N NN
H
NC JLH
CBG
NNC
CO9/
* CBG CO9/ (EL()
NC *L'
P
(LA
NP
N NN
NNNP
" (EL() P
B (EL() N
PN
P
(LA
NP *
N NN
*
NNNN
) CBG CO9/ ((LK
" ((LK P
B ((LK N
PN
P
(LA
NP
N NN
)
)
'
CBG
CO9/
(
CBG CO9/ JLH
(LA
NP *L'
P
(LA
NP
'
N NN '
" JLH P
P
B JLH N
N
PN
NP
(
NN
NN *L'
(
' CBG CO9/ *L'
%OR
S
" *L' P
B *L' N
PN
P
(LA
NP
'
N NN
'
NNNN or (NNNP and CBG)
CO9/
/he 234! im5lementation of the design in +igure "E is done
<ith four 5roceduresL
CL' a four-it carry-loo>ahead loc>.
,; com5utes first-level 5ro5agate and generate informa-
tion.
S1M com5utes the sum y %ORing the in5uts <ith the carry
values com5uted y CL'.
B!SLCE
collects the first-level CL' loc>s0 the ,;
com5utations0 and the S1M. /his 5rocedure 5erforms
all the <or> for a four-it value e=ce5t for the second-
and third-level loo>aheads.
#=am5le "() sho<s a 234! descri5tion of the adder.
Example A1! 7arr"-(oo2a#ead Adder
pac?a/e LOC'L is
constant 2: 2!E;ER :5 D"
proce%#re B!SLCE(
', B: in B!*(EC!OR(3 %o4nto 0$"
C2: in B!"
si/na0 S: o#t B!*(EC!OR(3 %o4nto 0$"
si/na0 ;,, ;;: o#t B!$"
proce%#re ,;(
', B: in B!*(EC!OR(3 %o4nto 0$"
,, ;: o#t B!*(EC!OR(3 %o4nto 0$$"
)#nction S1M(', B, C: B!*(EC!OR(3 %o4nto 0$$
ret#rn B!*(EC!OR"
proce%#re CL'(
,, ;: in B!*(EC!OR(3 %o4nto 0$"
C2: in B!"
C: o#t B!*(EC!OR(3 %o4nto 0$"
si/na0 ;,, ;;: o#t B!$"
en% LOC'L"
pac?a/e 3o%y LOC'L is

Comp#te s#m an% /ro#p o#tp#ts )rom a, 3, cin

proce%#re B!SLCE(
', B: in B!*(EC!OR(3 %o4nto 0$"
C2: in B!"
si/na0 S: o#t B!*(EC!OR(3 %o4nto 0$"
si/na0 ;,, ;;: o#t B!$ is
9aria30e ,, ;, C: B!*(EC!OR(3 %o4nto 0$"
3e/in
,;(', B, ,, ;$"
CL'(,, ;, C2, C, ;,, ;;$"
S 75 S1M(', B, C$"
en%"

Comp#te propa/ate an% /enerate )rom inp#t 3its

proce%#re ,;(', B: in B!*(EC!OR(3 %o4nto 0$"

,, ;: o#t B!*(EC!OR(3 %o4nto 0$$ is
3e/in
, :5 ' or B"
; :5 ' an% B"
en%"

Comp#te s#m )rom the inp#t 3its an% the carries

)#nction S1M(', B, C: B!*(EC!OR(3 %o4nto 0$$

ret#rn B!*(EC!OR is
3e/in
ret#rn(' Aor B Aor C$"
en%"

D3it carry0oo?ahea% 30oc?

proce%#re CL'(
,, ;: in B!*(EC!OR(3 %o4nto 0$"
C2: in B!"
C: o#t B!*(EC!OR(3 %o4nto 0$"
si/na0 ;,, ;;: o#t B!$ is
9aria30e !EM,*;,, !EM,*;;, L'S!*C: B!"
3e/in
!EM,*;, :5 ,(0$"
!EM,*;; :5 ;(0$"
L'S!*C :5 C2"
C(0$ :5 C2"
)or in - to 2- 0oop
!EM,*;, :5 !EM,*;, an% ,($"
!EM,*;; :5 (!EM,*;; an% ,($$ or ;($"
L'S!*C :5 (L'S!*C an% ,(-$$ or ;(-$"
C($ :5 L'S!*C"
en% 0oop"
;, 75 !EM,*;,"
;; 75 !EM,*;;"
en%"
en% LOC'L"
#se =ORK:LOC'L:'LL"

' 3.3it carry0oo?ahea% a%%er

entity '>>ER is
port(', B: in B!*(EC!OR(3- %o4nto 0$"
C2: in B!"
S: o#t B!*(EC!OR(3- %o4nto 0$"
CO1!: o#t B!$"
en% '>>ER"
architect#re BE&'(OR o) '>>ER is
si/na0 ;;,;,,;C: B!*(EC!OR(< %o4nto 0$"
Girst0e9e0 /enerate, propa/ate, carry
si/na0 ;;;, ;;,, ;;C: B!*(EC!OR(3 %o4nto 0$"
Secon%0e9e0 /en, prop, carry
si/na0 ;;;;, ;;;,: B!"
!hir%0e9e0 /en, prop
3e/in
Comp#te S#m an% -st0e9e0 ;enerate an% ,ropa/ate
1se inp#t %ata an% the -st0e9e0 Carries comp#te%
0ater:
B!SLCE('( 3 %o4nto 0$,B( 3 %o4nto 0$,;C(0$,
S( 3 %o4nto 0$,;,(0$, ;;(0$$"
B!SLCE('( < %o4nto D$,B( < %o4nto D$,;C(-$,
S( < %o4nto D$,;,(-$, ;;(-$$"
B!SLCE('(-- %o4nto B$,B(-- %o4nto B$,;C(.$,
S(-- %o4nto B$,;,(.$, ;;(.$$"
B!SLCE('(-@ %o4nto -.$,B(-@ %o4nto -.$,;C(3$,
S(-@ %o4nto -.$,;,(3$, ;;(3$$"
B!SLCE('(-F %o4nto -E$,B(-F %o4nto -E$,;C(D$,
S(-F %o4nto -E$,;,(D$, ;;(D$$"
B!SLCE('(.3 %o4nto .0$,B(.3 %o4nto .0$,;C(@$,
S(.3 %o4nto .0$,;,(@$, ;;(@$$"
B!SLCE('(.< %o4nto .D$,B(.< %o4nto .D$,;C(E$,
S(.< %o4nto .D$,;,(E$, ;;(E$$"
B!SLCE('(3- %o4nto .B$,B(3- %o4nto .B$,;C(<$,
S(3- %o4nto .B$,;,(<$, ;;(<$$"
Comp#te )irst0e9e0 Carries an% secon%0e9e0
/enerate an% propa/ate:
1se )irst0e9e0 ;enerate, ,ropa/ate, an%
secon%0e9e0 carry:
process(;,, ;;, ;;C$
9aria30e !EM,: B!*(EC!OR(3 %o4nto 0$"
3e/in
CL'(;,(3 %o4nto 0$, ;;(3 %o4nto 0$, ;;C(0$, !EM,,
;;,(0$, ;;;(0$$"
;C(3 %o4nto 0$ 75 !EM,"
en% process"
process(;,, ;;, ;;C$
9aria30e !EM,: B!*(EC!OR(3 %o4nto 0$"
3e/in
CL'(;,(< %o4nto D$, ;;(< %o4nto D$, ;;C(-$, !EM,,
;;,(-$, ;;;(-$$"
;C(< %o4nto D$ 75 !EM,"
en% process"
Comp#te secon%0e9e0 Carry an% thir%0e9e0
;enerate an% ,ropa/ate
1se secon%0e9e0 ;enerate, ,ropa/ate an% Carryin
(C2$
process(;;,, ;;;, C2$
9aria30e !EM,: B!*(EC!OR(3 %o4nto 0$"
3e/in
CL'(;;,, ;;;, C2, !EM,, ;;;,, ;;;;$"
;;C 75 !EM,"
en% process"
'ssi/n #n#se% 3its o) secon%0e9e0 ;enerate an%
,ropa/ate
;;,(3 %o4nto .$ 75 C--C"
;;;(3 %o4nto .$ 75 C00C"
Comp#te Carryo#t (CO1!$
1se thir%0e9e0 ;enerate an% ,ropa/ate an%
Carryin (C2$:
CO1! 75 ;;;; or (;;;, an% C2$"
en% BE&'(OR"
Im-lementation
Bn the carry-loo>ahead adder im5lementation0 5rocedures
are used to 5erform the com5utation of the design. /he
5rocedures can also e <ritten as se5arate entities and used
y com5onent instantiation0 5roducing a hierarchical design.
234! Com5iler does not colla5se a hierarchy of entities0 ut
it does colla5se the 5rocedure call hierarchy into one design.
Gote that the >ey<ord si/na0 is included efore some of
the interface 5arameter declarations. /his >ey<ord is
re-uired for o#t formal 5arameters <hen the actual
5arameters must e signals.
/he out5ut 5arameter C from the CL' 5rocedure is not de-
clared as a signal; thus it is not allo<ed in a concurrent 5ro-
cedure call; only signals can e used in such calls. /o over-
come this 5rolem0 su5rocesses are used0 declaring a
tem5orary variale !EM,. !EM, receives the value of the C
5arameter and assigns it to the a55ro5riate signal (a gener-
ally useful techni-ue).
Serialto.arallel (onverter*(ounting /its
/he e=am5le elo< sho<s the design of a serial-to-5arallel
converter that reads a serial0 it-stream in5ut and 5roduces
an eight-it out5ut.
/he design reads the follo<ing in5utsL
SER'L*2
Serial in5ut data.
RESE!
Mhen 8-80 causes the converter to reset. "ll out5uts are
set to '0 and the converter is 5re5ared to read the ne=t
serial <ord.
CLOCK
/he value of the RESE! and SER'L*2 is read on
the
5ositive transition of this cloc>. Out5uts of the converter
are also valid only on 5ositive transitions.
/he design 5roduces the follo<ing out5utsL
,'R'LLEL*O1!
#ight-it value read from the SER'L*2
5ort.
RE'>*E2'BLE
Mhen this out5ut is 8-8 on the 5ositive transition of CLOCK0
the data on ,'R'LLEL*O1! can e
read.
,'R!+*ERROR
Mhen this out5ut is 8-8 on the 5ositive transition of CLOCK0
a 5arity error has een detected on the SER'L*2 5ort.
Mhen a 5arity error is detected0 the converter halts until
restarted y the RESE! 5ort.
In-ut 0ormat
Mhen no data is eing transmitted to the serial 5ort0 >ee5 it
at a value of 808. #ach eight-it value re-uires (' cloc>
cycles to read. On the ((th cloc> cycle0 the 5arallel out5ut
value can e read.
Bn the first cycle0 a 8-8 is 5laced on the serial in5ut. /his
assign- ment indicates that an eight-it value follo<s. /he ne=t
eight cycles are used to transmit each it of the value. /he
most significant it is transmitted first. /he ('th and final cycle
transmits the 5arity of the eight-it value. Bt must e 808 if an
even numer of 8-8s are in the eight-it data0 and 8-8 other-
<ise. Bf the converter detects a 5arity error0 it sets the ,'RM
!+*ERROR out5ut to 8-8 and <aits until it is reset.
On the ((th cycle0 the RE'>*E2'BLE out5ut is set to 8-8 and
the eight-it value can e read from the ,'R'LLEL*O1! 5ort.
Bf the SER'L*2 5ort has a 8-8 on the ((th cycle0 another
eight-it value is read immediately; other<ise0 the converter
<aits until SER'L*2 goes to 8-8.
+igure "I sho<s the timing of this design.
Figure A. $ample )a*eform t#roug# t#e 7on*erter
C!OCO
S#RB"!PBG
R#S#/
P"R"!!#!PO9/
R#"4P#G"B!#
P"RB/QP#RROR
%% )4 %%
Im-lementation Details
/he converter is im5lemented as a four-state finite-state
machine <ith synchronous reset. Mhen a reset is detected0
the ='!*GOR*S!'R! state is entered. /he descri5tion of
each state is
='!*GOR*S!'R!
Stay in this state until a 8-8 is detected on the serial
in5ut. Mhen a 8-8 is detected0 clear the ,'R'LLEL*O1!
registers and go to the RE'>*B!S state.
RE'>*B!S
Bf the value of the c#rrent*3it*position counter is K0 all
eight its have een read. Chec> the com5uted 5arity
<ith the transmitted 5arity; if it is correct0 go to the
'LLO=*RE'> state0 other<ise go to the ,'R!+*ERROR
state.
Bf all eight its have not yet een read0 set the a55ro5ri-
ate it in the ,'R'LLEL*O1! uffer to the SER'L*2
value0 com5ute the 5arity of the its read so far0 and
incre- ment the c#rrent*3it*position.
'LLO=*RE'>
/his is the state <here the outside <orld reads the ,'RM
'LLEL*O1! value. Mhen that value is read0 the design
returns to the ='!*GOR*S!'R! state.
,'R!+*ERROR*>E!EC!E>
Bn this state the ,'R!+*ERROR out5ut is set to 8-8 and
nothing else is done.
/his design has four values stored in registersL
C1RRE2!*S!'!E
rememers the state as of the last cloc> edge.
C1RRE2!*B!*,OS!O2
rememers ho< many its have een read so far.
C1RRE2!*,'R!+
>ee5s a running %OR of the its read.
C1RRE2!*,'R'LLEL*O1!
stores each 5arallel it as it is found.
/he design is divided et<een t<o 5rocessesL the comina-
tional 2EX!*S! containing the cominational logic0 and the
se-uential S+2C& that is cloc>ed.
2EX!*S! 5erforms all the com5utations and state assignments.
/he 2EX!*S! 5rocess starts y first assigning default values to
all the signals it drives. /his assignment guarantees that all
signals are driven under all conditions. Ge=t0 the RESE! in5ut is
5rocessed. Bf RESE! is not active0 a case statement
determines the current state and its com5utations. State
transitions are 5erformed y assigning the ne=t stateAs value
you <ant to
the 2EX!*S!'!E signal.
/he serial-to-5arallel conversion itself is 5erformed y these
t<o statements in the 2EX!*S! 5rocessL
2EX!*,'R'LLEL*O1!(C1RRE2!*B!*,OS!O2$ 75 SER'L*2"
2EX!*B!*,OS!O2 75 C1RRE2!*B!*,OS!O2 I -"
/he first statement assigns the current serial in5ut it to a
5articular it of the 5arallel out5ut. /he second statement
increments the ne=t it 5osition to e assigned.
S+2C& registers and u5dates the stored values descried
aove. #ach registered signal has t<o 5arts0 2EX!*:::
and C1RRE2!*::::
2EX!*:::
signals hold values com5uted y the 2EX!*S! 5rocess.
C1RRE2!*:::
signals hold the values driven y the S+2C& 5rocess.
/he C1RRE2!*::: signals hold the values of the 2EX!*:::
signals as of the last cloc> edge.
Example A1% $erial-to-1arallel 7on*erter97ounting 4its
Seria0to,ara00e0 Con9erter, co#ntin/ 3its
pac?a/e !+,ES is
>ec0ares types #se% in the rest o) the %esi/n
type S!'!E*!+,E is (='!*GOR*S!'R!,
RE'>*B!S,
,'R!+*ERROR*>E!EC!E>,
'LLO=*RE'>$"
constant ,'R'LLEL*B!*CO12!: 2!E;ER :5 B"
s#3type ,'R'LLEL*R'2;E is 2!E;ER
ran/e 0 to (,'R'LLEL*B!*CO12!-$"
s#3type ,'R'LLEL*!+,E is B!*(EC!OR(,'R'LLEL*R'2;E$"
en% !+,ES"
#se =ORK:!+,ES:'LL" 1se the !+,ES pac?a/e
entity SER*,'R is >ec0are the inter)ace
port(SER'L*2, CLOCK, RESE!: in B!"
,'R'LLEL*O1!: o#t ,'R'LLEL*!+,E"
,'R!+*ERROR, RE'>*E2'BLE: o#t B!$"
en%"
architect#re BE&'(OR o) SER*,'R is
Si/na0s )or store% 9a0#es
si/na0 C1RRE2!*S!'!E, 2EX!*S!'!E: S!'!E*!+,E"
si/na0 C1RRE2!*,'R!+, 2EX!*,'R!+: B!"
si/na0 C1RRE2!*B!*,OS!O2, 2EX!*B!*,OS!O2:
2!E;ER ran/e ,'R'LLEL*B!*CO12! %o4nto 0"
si/na0 C1RRE2!*,'R'LLEL*O1!, 2EX!*,'R'LLEL*O1!:
,'R'LLEL*!+,E"
3e/in
2EX!*S!: process(SER'L*2, C1RRE2!*S!'!E, RESE!,
C1RRE2!*B!*,OS!O2, C1RRE2!*,'R!+,
C1RRE2!*,'R'LLEL*O1!$
!his process comp#tes a00 o#tp#ts, the neAt
state, an% the neAt 9a0#e o) a00 store% 9a0#es
3e/in
,'R!+*ERROR 75 808" >e)a#0t 9a0#es )or a00
RE'>*E2'BLE 75 808" o#tp#ts an% store% 9a0#es
2EX!*S!'!E 75 C1RRE2!*S!'!E"
2EX!*B!*,OS!O2 75 0"
2EX!*,'R!+ 75 808"
2EX!*,'R'LLEL*O1! 75 C1RRE2!*,'R'LLEL*O1!"
i) (RESE! 5 8-8$ then Synchrono#s reset
2EX!*S!'!E 75 ='!*GOR*S!'R!"
e0se
case C1RRE2!*S!'!E is State processin/
4hen ='!*GOR*S!'R! 56
i) (SER'L*2 5 8-8$ then
2EX!*S!'!E 75 RE'>*B!S"
2EX!*,'R'LLEL*O1! 75
,'R'LLEL*!+,E8(others56808$"
en% i)"
4hen RE'>*B!S 56
Example A1% (continued) $erial-to-1arallel 7on*erter97ounting 4its
i) (C1RRE2!*B!*,OS!O2 5
,'R'LLEL*B!*CO12!$ then
i) (C1RRE2!*,'R!+ 5 SER'L*2$ then
2EX!*S!'!E 75 'LLO=*RE'>"
RE'>*E2'BLE 75 8-8"
e0se
2EX!*S!'!E 75 ,'R!+*ERROR*>E!EC!E>"
en% i)"
e0se
2EX!*,'R'LLEL*O1!(C1RRE2!*B!*,OS!O2$ 75
SER'L*2"
2EX!*B!*,OS!O2 75
C1RRE2!*B!*,OS!O2 I -"
2EX!*,'R!+ 75 C1RRE2!*,'R!+ Aor
SER'L*2"
en% i)"
4hen ,'R!+*ERROR*>E!EC!E> 56
,'R!+*ERROR 75 8-8"
4hen 'LLO=*RE'> 56
2EX!*S!'!E 75 ='!*GOR*S!'R!"
en% case"
en% i)"
en% process"
S+2C&: process
!his process remem3ers the store% 9a0#es
across c0oc? cyc0es
3e/in
4ait #nti0 CLOCK8e9ent an% CLOCK 5 8-8"
C1RRE2!*S!'!E 75 2EX!*S!'!E"
C1RRE2!*B!*,OS!O2 75 2EX!*B!*,OS!O2"
C1RRE2!*,'R!+ 75 2EX!*,'R!+"
C1RRE2!*,'R'LLEL*O1! 75 2EX!*,'R'LLEL*O1!"
en% process"
,'R'LLEL*O1! 75 C1RRE2!*,'R'LLEL*O1!"
en% BE&'(OR"
Example A1% (continued) $erial-to-1arallel 7on*erter97ounting 4its
Serialto.arallel (onverter*S'i%ting /its
/his e=am5le descries another im5lementation of the serial-
to-5arallel converter in the last e=am5le. /his design 5erforms
the same function as the 5revious one0 ut uses a different
algorithm to do the conversion.
Bn the 5revious im5lementation0 a counter <as used to indi-
cate the it of the out5ut that <as set <hen a ne< serial it
<as read. Bn this im5lementation0 the serial its are shifted
into 5lace. Before the conversion ta>es 5lace0 a 8-8 is
5laced in the least-significant it 5osition. Mhen that 8-8 is
shifted out of the most significant 5osition (5osition ')0 the
signal 2EX!*&;&*B! is set to 8-8 and the conversion is
com5lete.
/he listing of the second im5lementation follo<s. /he differ-
ences are highlighted in old. /he differences relate to the
removal of the :::*B!*,OS!O2 signals0 the addition of
:::*&;&*B! signals0 and the change in the <ay 2EX!*,'RM
'LLEL*O1! is com5uted.
Example A1+ $erial-to-1arallel 7on*erter9$#ifting 4its
pac?a/e !+,ES is
>ec0ares types #se% in the rest o) the %esi/n
type S!'!E*!+,E is (='!*GOR*S!'R!,
RE'>*B!S,
,'R!+*ERROR*>E!EC!E>,
'LLO=*RE'>$"
constant ,'R'LLEL*B!*CO12!: 2!E;ER :5 B"
s#3type ,'R'LLEL*R'2;E is 2!E;ER
ran/e 0 to (,'R'LLEL*B!*CO12!-$"
s#3type ,'R'LLEL*!+,E is B!*(EC!OR(,'R'LLEL*R'2;E$"
en% !+,ES"
#se =ORK:!+,ES:'LL" 1se the !+,ES pac?a/e
entity SER*,'R is >ec0are the inter)ace
port(SER'L*2, CLOCK, RESE!: in B!"
,'R'LLEL*O1!: o#t ,'R'LLEL*!+,E"
,'R!+*ERROR, RE'>*E2'BLE: o#t B!$"
en%"
architect#re BE&'(OR o) SER*,'R is
Si/na0s )or store% 9a0#es
si/na0 C1RRE2!*S!'!E, 2EX!*S!'!E: S!'!E*!+,E"
si/na0 C1RRE2!*,'R!+, 2EX!*,'R!+: B!" signal
CURRENT_HIGH_BIT, NEXT_HIGH_BIT: BIT; si/na0
C1RRE2!*,'R'LLEL*O1!, 2EX!*,'R'LLEL*O1!:
,'R'LLEL*!+,E"
3e/in
2EX!*S!: process(SER'L*2, C1RRE2!*S!'!E, RESE!,
CURRENT_HIGH_BIT, C1RRE2!*,'R!+,
C1RRE2!*,'R'LLEL*O1!$
!his process comp#tes a00 o#tp#ts, the neAt
state, an% the neAt 9a0#e o) a00 store% 9a0#es
3e/in
,'R!+*ERROR 75 808" >e)a#0t 9a0#es )or a00
RE'>*E2'BLE 75 808" o#tp#ts an% store% 9a0#es
2EX!*S!'!E 75 C1RRE2!*S!'!E"
2EX!*&;&*B! 75 808"
2EX!*,'R!+ 75 808"
2EX!*,'R'LLEL*O1! 75 PARALLEL_TYPE(oth!s"#$%;
i)(RESE! 5 8-8$ then Synchrono#s reset
2EX!*S!'!E 75 ='!*GOR*S!'R!"
e0se
case C1RRE2!*S!'!E is State processin/
4hen ='!*GOR*S!'R! 56
i) (SER'L*2 5 8-8$ then
2EX!*S!'!E 75 RE'>*B!S"
2EX!*,'R'LLEL*O1! 75
,'R'LLEL*!+,E8(others56808$"
en% i)"
4hen RE'>*B!S 56
i) (CURRENT_HIGH_BIT " &$ then
i) (C1RRE2!*,'R!+ 5 SER'L*2$ then
2EX!*S!'!E 75 'LLO=*RE'>"
RE'>*E2'BLE 75 8-8"
e0se
2EX!*S!'!E 75 ,'R!+*ERROR*>E!EC!E>"
en% i)"
e0se
NEXT_HIGH_BIT '" CURRENT_PARALLEL_(UT($%;
2EX!*,'R'LLEL*O1! 75
C1RRE2!*,'R'LLEL*O1!(
- to ,'R'LLEL*B!*CO12!-$ N
SER'L*2"
2EX!*,'R!+ 75 C1RRE2!*,'R!+ Aor
SER'L*2"
en% i)"
4hen ,'R!+*ERROR*>E!EC!E> 56
,'R!+*ERROR 75 8-8"
4hen 'LLO=*RE'> 56
2EX!*S!'!E 75 ='!*GOR*S!'R!"
en% case"
en% i)"
en% process"
S+2C&: process
!his process remem3ers the store% 9a0#es
across c0oc? cyc0es
3e/in
4ait #nti0 CLOCK8e9ent an% CLOCK 5 8-8"
C1RRE2!*S!'!E 75 2EX!*S!'!E"
CURRENT_HIGH_BIT '" NEXT_HIGH_BIT;
C1RRE2!*,'R!+ 75 2EX!*,'R!+"
C1RRE2!*,'R'LLEL*O1! 75 2EX!*,'R'LLEL*O1!"
en% process"
,'R'LLEL*O1! 75 C1RRE2!*,'R'LLEL*O1!"
en% BE&'(OR"
Gote that the synthesi8ed schematic for the shifter im5le-
mentation is much sim5ler than the first (#=am5le "(*). Bt is
sim5ler ecause the shifter algorithm is inherently easier to
im5lement.
Example A1+ (continued) $erial-to-1arallel 7on*erter9$#ifting 4its
Mith the count algorithm0 each of the fli5-flo5s holding the
,'R'LLEL*O1! its needed logic that decoded the value
stored in the B!*,OS!O2 fli5-flo5s to see <hen to route in
the value of SER'L*2. "lso0 the B!*,OS!O2 fli5-flo5s
need- ed an incrementer to com5ute their ne=t value.
Bn contrast0 the shifter algorithm re-uires no incrementer0 and
no fli5-flo5s to hold B!*,OS!O2. "dditionally0 the logic in
front of most ,'R'LLEL*O1! its needs to read only the value
of the 5revious fli5-flo50 or 808. /he value de5ends on <hether
its are currently eing read. Bn the shifter algorithm0 the
SER'L*2 5ort needs to e connected only to the least
significant it (numer J) of the ,'R'LLEL*O1! fli5-flo5s.
/hese t<o im5lementations illustrate the im5ortance of de-
signing efficient algorithms. Both <or> 5ro5erly0 ut the shifter
algorithm 5roduces a faster0 more area-efficient design.
.rogrammable Logic Array ".LA#
/his e=am5le sho<s a <ay to uild P!"s in 234!. /he ,L'
function uses an in5ut loo>u5 vector as an inde= into a
constant P!" tale0 then returns the out5ut vector
s5ecified y the P!".
/he P!" tale is an array of ,L'*RO=s0 <here each ro< is an
array of ,L'*ELEME2!s. #ach element is either a (0 a '0 a minus0
or a s5ace (8-80 8080 880 or 8 8). /he tale is s5lit et<een an
in5ut 5lane and an out5ut 5lane. /he in5ut 5lane is s5ecified
y 's0 (s0 and minuses. /he out5ut 5lane is s5ecified y 's
and (s. /he t<o 5lanesA values are se5arated y a s5ace.
Bn the ,L' function0 the out5ut vector is first initiali8ed to e all
808s. Mhen the in5ut vector matches an in5ut 5lane in a ro<
of the P!" tale0 the 8-8s in the out5ut 5lane are assigned to
the corres5onding its in the out5ut vector. " match is deter-
mined as follo<sL
Bf a 808 or 8-8 is in the in5ut 5lane0 the in5ut vector
must have the same value in the same 5osition.
Bf a 88 is in the in5ut 5lane0 it matches any in5ut
vector value at that 5osition.
/he generic P!" tale ty5es and the ,L' function are
defined in a 5ac>age named LOC'L. "n entity ,L'*(&>L that
uses
LOC'L needs only to s5ecify its P!" tale as a constant0 then
call the ,L' function.
Gote that the ,L' function does not e=5licitly de5end on
the si8e of the P!". /o change the si8e of the P!"0 change
the initiali8ation of the !'BLE constant and the initiali8ation of
the constants 2,1!*CO12!0 O1!,1!*CO12! and RO=*CO12!. Bn
#=am- 5le "(E0 these constants are initiali8ed to a P!"
e-uivalent
to the ROM sho<n 5reviously (#=am5le "*). "ccordingly0 the
synthesi8ed schematic is the same as that of the ROM0 <ith
one differenceL in #=am5le "*0 the >'!' out5ut 5ort range is
- to @; in #=am5le "(E0 the O1!*(EC!OR out5ut 5ort range is D
%o4nto 0.
/his e=am5le is included mainly to sho< the ca5ailities of
234!. Bt is more efficient to define the P!" directly0 y using
the P!" in5ut format. See the <esign 7ompiler Famil" &efer-
ence Manual for more information aout the P!" in5ut for-
mat.
Example A1- 1rogramma5le (ogic Arra"
pac?a/e LOC'L is
constant 2,1!*CO12!: 2!E;ER :5 3"
constant O1!,1!*CO12!: 2!E;ER :5 @"
constant RO=*CO12!: 2!E;ER :5 E"
constant RO=*SZE: 2!E;ER :5 2,1!*CO12! I
O1!,1!*CO12! I -"
type ,L'*ELEME2! is (8-8, 808, 88, 8 8$"
type ,L'*(EC!OR is
array (2!E;ER ran/e 76$ o) ,L'*ELEME2!"
s#3type ,L'*RO= is
,L'*(EC!OR(RO=*SZE - %o4nto 0$"
s#3type ,L'*O1!,1! is
,L'*(EC!OR(O1!,1!*CO12! - %o4nto 0$"
type ,L'*!'BLE is
array(RO=*CO12! - %o4nto 0$ o) ,L'*RO="
)#nction ,L'(2*(EC!OR: B!*(EC!OR"
!'BLE: ,L'*!'BLE$
ret#rn B!*(EC!OR"
en% LOC'L"
pac?a/e 3o%y LOC'L is
)#nction ,L'(2*(EC!OR: B!*(EC!OR"
!'BLE: ,L'*!'BLE$
ret#rn B!*(EC!OR is
s#3type RES1L!*!+,E is
B!*(EC!OR(O1!,1!*CO12! - %o4nto 0$"
9aria30e RES1L!: RES1L!*!+,E"
9aria30e RO=: ,L'*RO="
9aria30e M'!C&: BOOLE'2"
9aria30e 2*,OS: 2!E;ER"
3e/in
RES1L! :5 RES1L!*!+,E8(others 56 B!8( 808 $$"
)or in !'BLE8ran/e 0oop
RO= :5 !'BLE($"
M'!C& :5 !R1E"
2*,OS :5 2*(EC!OR80e)t"
Chec? )or match in inp#t p0ane
)or O in RO=*SZE - %o4nto O1!,1!*CO12! 0oop
i)(RO=(O$ 5 ,L'*ELEME2!8( 8-8 $$ then
M'!C& :5 M'!C& an%
(2*(EC!OR(2*,OS$ 5 B!8( 8-8 $$"
e0si)(RO=(O$ 5 ,L'*ELEME2!8( 808 $$ then
M'!C& :5 M'!C& an%
(2*(EC!OR(2*,OS$ 5 B!8( 808 $$"
e0se
n#00" M#st 3e min#s (C%on8t careC$
en% i)"
2*,OS :5 2*,OS -"
en% 0oop"
Set o#tp#t p0ane
i)(M'!C&$ then
)or O in RES1L!8ran/e 0oop
i)(RO=(O$ 5 ,L'*ELEME2!8( 8-8 $$ then
RES1L!(O$ :5 B!8( 8-8 $"
en% i)"
en% 0oop"
en% i)"
en% 0oop"
ret#rn(RES1L!$"
en%"
en% LOC'L"
#se =ORK:LOC'L:a00"
entity ,L'*(&>L is
port(2*(EC!OR: B!*(EC!OR(. %o4nto 0$"
O1!*(EC!OR: o#t B!*(EC!OR(D %o4nto 0$$"
en%"
architect#re BE&'(OR o) ,L'*(&>L is
constant !'BLE: ,L'*!'BLE :5 ,L'*!'BLE8(
,L'*RO=8(C -0000C$,
,L'*RO=8(C- 0-000C$,
,L'*RO=8(C00 00-0-C$,
,L'*RO=8(C- 00-0-C$,
,L'*RO=8(C-- 00-0-C$,
,L'*RO=8(C- 000-0C$$"
3e/in
O1!*(EC!OR 75 ,L'(2*(EC!OR, !'BLE$"
en% BE&'(OR"