UNIT III MICROPROCESSOR PERIPHERAL INTERFACING

Syllabus:
UNIT III MICROPROCESSOR PERIPHERAL INTERFACING
Introduction, Generation of I/O Ports, Programmable Peripheral Interface (PPI)-Intel
8255, Sample-and-Hold Circuit and Multiplexer, Keyboard and Display Interface,
Keyboard and Display Controller (8279), Programmable Interval timers (Intel 8253,
8254), D-to-A converter, A-to-D converter, CRT Terminal Interface, Printer
Interface.
INDEX
1. The 8255 PPI Programmable Peripheral Interface
1.1 Features:
1.2 Block Diagram of 8255 (Architecture)
1.3 Pin description:
1.4 Modes of operation
1.4.1 I/O mode
1.4.2 BSR mode
1.5 control word register
1.6 8255 programming
1.7 Keyboard interfacing using 8255
2. 8279 Programmable Keyboard/Display Interface
2.1 Features
2.2 Block Diagram of 8279 (Architecture)
2.3 Pin description:
2.4 Modes of operation
2.5 control word register
3. 8253/8254 timer/ counter
3.1 Features
3.2 Block Diagram of 8253 (Architecture)
3.3 Pin description:
3.4 Modes of operation
.5 control word register
4. D-to-A converter and A-to-D converter, S & H circuit
4.1 A-to-D converter

4.1.1 ADC introduction

4.1.2 Features of ADC 803/804
4.1.3 ADC interfacing with 8086 microprocessor
4.2 D-to-A converter
4.2.1 DAC introduction
4.2.2 Features of DAC 1408
4.2.3 DAC1408 interfacing with 8086 microprocessor
4.3 Sample-and-Hold Circuit and Multiplexer
5. CRT Terminal Interface and Printer Interface
5.1 CRT Terminal Interface
5.1.1 About CRT
5.1.2 RS 232C PIN details
5.1.3 CRT interface with microprocessor
5.2 Printer interface
5.2.1 Centronics protocol pin description
5.2.2 Printer interface with microprocessor
5.2.3 Printer algorithm

INTERFACING CONCEPTS
Introduction
The microprocessor achieves its aim or applies its potential only when it is
used for data processing or problem solving. The microprocessor has to accept the
data through input devices process them using the Arithmetic and Logic Unit and
displays the result in a human readable form. In other words we can say the
microprocessor is to be interfaced with input and output devices to provide a
computing environment. Frequently used input devices are Analog to Digital (A/D)
converters and keyboard and the output devices are Light Emitting Diodes (LEDs),
printers and monitors.
These input and output devices are called peripherals. Since the speed at which
the processor and the peripherals operate is different, suitable logic circuits
(hardware) and writing instructions (software) should be used to enable the
microprocessor to communicate with these peripherals. This is called interfacing.
The logic circuits are called I/O ports or interfacing devices. In this unit you will
study about the various programmable interfacing devices. This unit also discusses
about the coprocessors that are used to enhance the performance of the
microprocessors.
1. The 8255 PPI Programmable Peripheral Interface:
1.1 Features:
The parallel input-output port chip 8255 is also called as programmable
peripheral input-output port
It has 24 input/output lines which may be individually programmed in two
groups of twelve lines each, or three groups of eight lines.
The two groups of I/O pins are named as Group A and Group B.
Group A contains an 8-bit port A (PA0-PA7) along with a 4-bit port. C (PC4PC7)upper.
Group B contains an 8-bit port B, containing lines PB0-PB7 and a 4-bit port C
with lower bits PC0- PC3.

The port C upper and port C lower can be used in combination as an 8-bit port
C. All of these ports can function independently either as input or as output
ports.
This can be achieved by programming the bits of an internal register of 8255
called as control word register ( CWR ).
1.2 Block Diagram of 8255 (Architecture)
It has a 40 pins of 4 groups.
1. Data bus buffer
2. Read Write control logic
3. Group A and Group B controls
4. Port A, B and C

Data bus buffer:

This is a tristate bidirectional buffer used to interface the 8255 to system data
bus. The 8-bit data bus buffer is controlled by the read/write control logic This buffer
receives or transmits data upon the execution of input or output instructions by the

microprocessor Control word and status information are also transferred through this
unit.
Read/Write control logic:
The read/write control logic manages all of the internal and external transfers
of both data and control words This unit accepts control signals ( RD, WR ) and also
inputs from address bus and issues commands to individual group of control blocks (
Group A, Group B). RD, WR, A1, A0 and RESET are the inputs provided by the
microprocessor to the READ/ WRITE control logic of 8255. The 8-bit, 3-state
bidirectional buffer is used to interface the 8255 internal data bus with the external
system data bus.
It has the following pins.
a) CS Chip select : A low on this PIN enables the communication between CPU
and 8255.
b) RD (Read) A low on this pin enables the CPU to read the data in the ports or the
status word through data bus buffer.
c) WR ( Write ) : A low on this pin, the CPU can write data on to the ports or on to
the control register through the data bus buffer.
d) RESET: A high on this pin clears the control register and all ports are set to the
input mode
e) A0 and A1 ( Address pins ): These pins in conjunction with RD and WR pins
control the selection of one of the 3 ports.
Group A and Group B controls :
These block receive control from the CPU and issues commands to their
respective ports.
Group A - PA and PCU ( PC7 PC4)
Group B PB and PCL ( PC3 PC0)
Control word register can only be written into, no read operation of the CW register
is allowed.
a) Port A: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in 3 modes mode 0,mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in mode 0, mode1.
c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.
This port can be divided into two 4 bit ports (PCU ( PC7 PC4), PCL ( PC3 PC0)
and can be used as control signals for port A and port B. it can be programmed in
mode 0.
Group A and Group B controls :

These block receive control from the CPU and issues commands to their respective
ports.
Group A - PA and PCU ( PC7 PC4)
Group B PB and PCL ( PC3 PC0)
Control word register can only be written into, no read operation of the CW register
is allowed.
a) Port A: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in 3 modes mode 0,mode 1, mode 2.
b) Port B: This has an 8 bit latched / buffered O/P and 8 bit input latch. It can be
programmed in mode 0, mode1.
c) Port C : This has an 8 bit latched input buffer and 8 bit out put latched/buffer.
This port can be divided into two 4 bit ports (PCU ( PC7 PC4), PCL ( PC3 PC0)
and can be used as control signals for port A and port B. it can be programmed in
mode 0.
1.3 Pin description:

PA7-PA0: eight port A lines that acts as either latched output or buffered input lines
depending upon the control word loaded into the control word register.
PC7-PC4 : Upper nibble of port C lines. It may act as either output latches or input
buffers lines. It used for generation of handshake lines in mode 1 or mode 2.
PC3-PC0 : These are the lower port C lines, other details are the same as PC7-PC4
lines.
PB0-PB7 : These are the eight port B lines which are used as latched output lines
or buffered input lines in the same way as port A.
RD : This is the input line driven by the microprocessor and should be low to
indicate read operation to 8255.
WR : This is an input line driven by the microprocessor. A low on this line
indicates write operation.
CS : This is a chip
hip select line. If this line goes low, it enables the 8255 to respond
to RD and WR signals, otherwise RD and WR signal are neglected.
A1-A0 : These are the address input lines and are driven by the microprocessor.
These address lines are used for addres
addressing any one of the four registers ,i.e. three
ports and a control word register
In case of 8086 systems, if the 8255 is to be interfaced with lower order data bus,
the A0 and A7
D0-D7 : These are the data bus lines those carry data or control word to/from the
microprocessor.

 RESET : A logic high on this line clears the control word register of 8255. All
ports are set as input ports by default after reset.
1.5 Control Word Register:
The Address lines A1-A0 with RD, WR and CS form the following operations for
8255 These address lines are used for addressing any one of the four registers ,
i.e. three ports and a control word register as given in table below
Control Word Format of 8255

BSR Mode:
In this mode any of the 8-bits of port C can be set or reset depending on D0 of the
control word.
The bit to be set or reset is selected by bit select flags D3, D2 and D1 of the CWR
BSR Mode Control Word Register Format

1.4 Modes of Operation of 8255:

2 modes of operation
1. i/o mode
2. BSR mode

1. I/O mode - work as programmable I/O ports,

1. mode 0
2. mode 1
3. mode 2.
2.Bit Set-Reset mode (BSR).Only port C (PC0-PC7) can be used to set or reset its individual port bits
I/O mode:
Mode 0: Simple Input or Output:
In this mode, ports A, B are used as two simple 8-bit I/O ports port C as two 4bit ports.
Each port can be programmed to function as simply an input port or an output
port. The input/output features in Mode 0 are as follows.
1. Outputs are latched.
2. Inputs are not latched.
3. Ports dont have handshake or interrupt capability.
Mode 1: Input or Output with Handshake :
In this mode, handshake signals are exchanged between the MPU and peripherals
prior to data transfer.
The features of the mode include the following:
1. Two ports (A and B) function as 8-bit I/O ports.
They can be configured as either as input or output ports.
2. Each port uses three lines from port C as handshake signals.
The remaining two lines of Port C can be used for simple I/O operations.

3. Input and Output data are latched.

4. Interrupt logic is supported.
82C55: Mode 1 Strobed Input

~STB : The strobe input loads data into the port latch on a 0-to transition.
IBF : Input buffer full is an output indicating that the input latch contain
information.
INTR : Interrupt request is an output that requests an interrupts.
INTE : The interrupt enable signal is neither aann input nor an output; it is an internal
bit programmed via the PC4 (port A) or PC2 (port B) bits.
PC7,PC6 : The port C pins 7 and 6 are general purpose I/O pings that are available
for any purpose.
82C55 : Mode 1 Output Exam.

 ~OBF : Output buffer full is an output that goes low when data is latched in
either port A or port B. Goes low on ~ACK.
~ACK : The acknowledge signal causes the ~OBF pin return to 0. This is a
response from an external device.
INTR : Interrupt request is an output that requests an interrupt.
INTE : The interrupt enable signal is neither an input nor an output; it is an
internal bit programmed via the PC6(Port A) or PC2(port B) bits.
PC5,PC4 : The port C pins 5 and 4 are general
general-purpos
purpose I/O pins that are
available for any purpose.
Mode 2: Bidirectional Data Transfer :
This mode is used primarily in applications such as data transfer between two
computers.
In this mode, Port A can be configured as the bidirectional port
Port B either in Mode 0 or Mode 1.
Port A uses five signals from Port C as handshake signals for data transfer.
The remaining three signals from port C can be used either as simple I/O or as
handshake for port B.
MODE 2 Basic Functional Definitions:

Used in Group A only.

One 8-bit, bi-directional
directional bus port (Port A) and a 55-bit
bit control port (Port C).
Both inputs and outputs are latched.
The 5-bit
bit control port (Port C) is used for control and status for the 8-bit,
8
bidirectional bus port (Port A).

 Timing diagram is a combination of the Mode 1 Strobed Input and Mode 1

Strobed Output Timing diagrams.
INTR : Interrupt request is an output that requests an interrupt.
~OBF : Output Buffer Full is an output indicating that that output buffer
contains dataa for the bi
bi-directional bus.
~ACK : Acknowledge is an input that enables tri
tri-state
state buffers which are
otherwise in their high-impedance
high
state.
~STB : The strobe input loads data into the port A latch.
IBF : Input buffer full is an output indicating that the
the input latch contains
information for the external bi
bi-directional bus.
INTE : Interrupt enable are internal bits that enable the INTR pin. BIT
PC6(INTE1) and PC4(INTE2).
PC2,PC1,PC0 : These port C pins are general-purpose
general purpose I/O pins that are
available for any
ny purpose.
1.7 keyboard interfacing using 8255 ppi

In a matrix keyboard, the major task is to identify a key that is pressed and
decode the key in terms of its binary value. This task can be accomplished through
either software or hardware Columns and rows make contact only when a key is
pressed, otherwise they remain high.
The major function required here is to identify the row and column of the
pressed keyThe interfacing arrangement checks the columns by reading the input
port. If any key is pressed then a change is identified and the key press is decoded.
decode
The steps involved in this process are
1.
2.
3.
4.

Check whether all keys are open

Check a key closure
Identify the key
Find the binary key code for the key

1. 8279 Programmable Keyboard/Display Interface

2.1 Features-8279
Intel 8279 is the keyboard/display controller that is used to interface the
keyboard and the display of a system to the microprocessor
The advantage of 8279 is that it is able to drive the signals for both the
keyboard and display and hence it is possible for the microprocessor to
concentrate
te in its routine tasks
The 8279 has two sections: keyboard and display
The 8279 chip provides a set of four scan lines and eight return lines for
interfacing keyboards and a set of eight output lines for interfacing display

 The keyboard portion can provide a scanned interface to a 64-contact key

matrix
The keyboard portion interfaces an array of sensors or a strobed interface
keyboard
Scans and encodes up to a 64-key keyboard. And Controls up to a 16 digit
numerical display.
Keyboard section has a built-in FIFO 8 character buffer.
The display is controlled from an internal 16x8 RAM that stores the coded
display information.

8279 has 8 control words to be considered before It is programmed

2.2 8279 pin description:

Basic Description of the 8279

A0: Selects data (0) or control/status (1) for reads and writes between 8085
and 8279.

Output that blanks the displays.

CLK: Used internally for timing. Max is 3 MHz.
CN/ST: Control/strobe, connected to the control key on the keyboard.
cs :Chip select that enables programming, reading the keyboard, etc.

DB7-DB0: Consists of bi-directional pins that connect to data bus from 8085.

IRQ: Interrupt request, becomes 1 when a key is pressed, data is available.

OUT A3-A0/B3-B0: Outputs that sends data to the most significant/least

significant of display
:Connects to 8086 WR or RD signal, reads data/status registers.

RESET: Connects to system RESET.

RL7-RL0: Return lines are inputs used to sense key depression in the
keyboard matrix.

Shift: Shift connects to Shift key on keyboard.

SL3-SL0: Scan line outputs scan both the keyboard and displays.
2.3 8279 INTERNAL ARCTHITECTURE:

Intel 8279 Keyboard Section:

Keyboard depressions can be 2-key lockout or N-key rollover
Keyboard entries are debounced and strobed in an 8-charcter FIFO
If more than 8 characters are entered, overrun status is set
Key entries set the interrupt output line to the CPU
Intel 8279 Display Section
The display portion provides a scanned display interface for LED,
incandescent and other popular display technologies
Both numeric and alphanumeric segment displays may be used as well as
simple indicators
The 8279 has 16*8 display RAM which can be organized into dual 16*4
The RAM can be loaded or interrogated by the CPU
Both right entry, calculator and left entry typewriter display formats are
possible
Both read and write of the display RAM can be done with auto-increment of
the display RAM address
The keyboard display controller chip 8279 provides:
a) a set of four scan lines and eight return lines for interfacing keyboards

b) A set of eight output lines for interfacing display. Fig shows the functional
block diagram of 8279 followed by its brief description.
I/O Control and Data Buffers :
The I/O control section controls the flow of data to/from the 8279. The data buffers
interface the external bus of the system with internal bus of 8279.The I/O section is
enabled only if CS is low. The pins A0, RD and WR select the command, status or
data read/writ operations carried out by the CPU with 8279.
Control and Timing Register and Timing Control :
These registers store the keyboard and display modes and other
operating conditions programmed by CPU. The registers are written with A0=1 and
WR=0. The Timing and control unit controls the basic timings for the operation of
the circuit. Scan counter divide down the operating frequency of 8279 to derive scan
keyboard and scan display frequencies.
Scan Counter :
The scan counter has two modes to scan the key matrix and refresh the
display. In the encoded mode, the counter provides binary count that is to be
externally decoded to provide the scan lines for keyboard and display (Four
externally decoded scan lines may drive upto 16 displays). In the decode scan mode,
the counter internally decodes the least significant 2 bits and provides a decoded 1
out of 4 scan on SL0-SL3( Four internally decoded scan lines may drive upto 4
displays). The keyboard and display both are in the same mode at a time.
Return Buffers and Keyboard Debounce and Control:
This section for a key closure row wise. If a key closer is detected, the
keyboard debounce unit debounces the key entry (i.e. wait for 10 ms). After the
debounce period, if the key continues to be detected. The code of key is directly
transferred to the sensor RAM along with SHIFT and CONTROL key status.
FIFO/Sensor RAM and Status Logic:
In keyboard or strobed input mode, this block acts as 8-byte first-in-first-out
(FIFO) RAM. Each key code of the pressed key is entered in the order of the entry
and in the mean time read by the CPU, till the RAM become empty. The status logic
generates an interrupt after each FIFO read operation till the FIFO is empty. In
scanned sensor matrix mode, this unit acts as sensor RAM. Each row of the sensor
RAM is loaded with the status of the corresponding row of sensors in the matrix. If a
sensor changes its state, the IRQ line goes high to interrupt the CPU.
Display Address Registers and Display RAM :

The display address register holds the address of the word currently being
written or read by the CPU to or from the display RAM. The contents of the registers
are automatically updated by 8279 to accept the next data entry by CPU.
2.4 Modes of operation:
2 modes
1.input (keyboard) modes
2.output (display) modes
1.input (keyboard) modes:
a)scanned keyboard mode
i)scanned keyboard mode with 2 key lockout
ii)scanned keyboard with Nkey rollover
b)scanned sensor mode
c)strobed mode
2.output (display) modes
a)display scan or typewritter mode
b) display entry or calculater mode
i)scanned keyboard mode with 2 key lockout:
when a key is pressed, a debounce logic comes into operation
During the next two scans, the other keys are checked for closure and if no
other is pressed the first pressed key is identified
The key code of the identified key is entered into the FIFO with SHIFT and
CNTL status, provided that FIFO is not full, that is it has at least one byte free
If the FIFO does not have any free byte, naturally the key data will not be
entered and the error flag is set
ii)scanned keyboard with Nkey rollover:
each key depression is treated independently

 When a key is pressed the debounce circuit waits for two keyboard scans and
then checks whether the key is still depressed
If it is still depressed, the code is entered in FIFO RAM
Any number of keys can be pressed simultaneously and recognized in the
order, the keyboard scan recorded them
All the codes of such keys are entered into FIFO
iii) Sensor Matrix Mode :
In the sensor matrix mode, the debounce logic is inhibited. The 8-byte FIFO
RAM now acts as 8 * 8 bit memory matrix. The status of the sensor switch matrix is
fed directly to sensor RAM matrix. Thus the sensor RAM bits contains the row-wise
and column wise status of the sensors in the sensor matrix.
The IRQ line goes high, if any change in sensor value is detected at the end of
a sensor matrix scan or the sensor RAM has a previous entry to be read by the CPU.
The IRQ line is reset by the first data read operation, if AI = 0, otherwise, by issuing
the end interrupt command. AI is a bit in read sensor RAM word.
Display Modes:
There are various options of data display. For example, the command number of
characters can be 8 or 16, with each character organised as single 8-bit or dual 4bit codes. Similarly there are two display formats.
The first one is known as left entry mode or type writer mode, since in a type
writer the first character typed appears at the left-most position, while the
subsequent characters appear successively to the right of the first one. The other
display format is known as right entry mode, or calculator mode, since in a
calculator the first character entered appears at the rightmost position and this
character is shifted one position left when the next characters is entered.
Thus all the previously entered characters are shifted left by one position when a
new characters is entered.
i.

Left Entry Mode :

In the left entry mode, the data is entered from left side of the display unit.
Address 0 of the display RAM contains the leftmost display characters and
address 15 of the RAM contains the right most display characters. It is just
like writing in our address is automatically updated with successive reads
or writes. The first entry is displayed on the leftmost display and the

sixteenth entry on the rightmost display. The seventeenth entry is again

displayed at the leftmost display position.
ii.

Right Entry Mode :

In this right entry mode, the first entry to be displayed is entered on the
rightmost display. The next entry is also placed in the right most display
but after the previous display is shifted left by one display position. The
leftmost characters is shifted out of that display at the seventeenth entry
and is lost, i.e. it is pushed out of the display RAM.
2.5 Command word register:

All the command words or status words are written or read with A0 = 1 and CS = 0
to or from 8279. This section describes the various command available in 8279.
1. Keyboard/Display Mode Set
DD is the display mode and KKK is the keyboard mode

2. Programmable Clock:

 PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal

constant ranging from 3 to 31, decided by the bits of an internal prescalar
PPPPP

3. Read FIFO/Sensor RAM:

The format of this command is given below. This word is written to set up
8279 for reading FIFO/ sensor RAM. In scanned keyboard mode, AI and
AAA bits are of no use. The 8279 will automatically drive data bus for
each subsequent read, in the same sequence, in which the data was entered.
In sensor matrix mode, the bits AAA select one of the 8 rows of RAM. If
AI flag is set, each successive read will be from the subsequent RAM
location.

X Dont Care
AI Auto Increment flag
AAA Address pointer to 8-bit FIFO RAM
4. Read Display RAM:
AI is auto increment flag and AAAA, the 4-bit address, points to the 16-byte
display RAM that is to be read. If AI=1, the address will be automatically,
incremented after each read or write to the display RAM.

5. Write Display RAM

AI Auto increment Flag.

AAAA 4 bit address for 16-bit display RAM to be written.
6. Clear Display RAM:

0
1

X
1

All zeros (X dont care) AB = 00

0

A1-A2 = 2 (0010) and B3-B0 = 00 (0000)

All ones (AB=FF), i.e. clear RAM

7. End Interrupt/Error Mode Set:

For N-key rollover mode, if the E bit is programmed to be 1,

the 8279 operates in special error mode
Interfacing Keyboard/Display to the Microprocessor Using Intel 8279:

Intel 8279 Keyboard Section:

Keyboard depressions can be 2-key lockout or N-key rollover
Keyboard entries are debounced and strobed in an 8-charcter FIFO
If more than 8 characters are entered, overrun status is set
Key entries set the interrupt output line to the CPU
Intel 8279 Display Section
The display portion provides a scanned display interface for LED,
incandescent and other popular display technologies
Both numeric and alphanumeric segment displays may be used as well as
simple indicators
The 8279 has 16*8 display RAM which can be organized into dual 16*4
The RAM can be loaded or interrogated by the CPU
Both right entry, calculator and left entry typewriter display formats are
possible
Both read and write of the display RAM can be done with auto-increment of
the display RAM address
The keyboard display controller chip 8279 provides:
a) a set of four scan lines and eight return lines for interfacing keyboards
b) A set of eight output lines for interfacing display. Fig shows the functional
block diagram of 8279 followed by its brief description.
2. Programmable Interval Timer 8253/8254
The 8253/54 solves one of most common problem in any microcomputer
system, the generation of accurate time delays under software control. Instead of
setting up timing loops in system software, the programmer configures the 8253/54
to match his requirements, initializes one of the counters of the 8253/54 with the
desired quantity, then upon command the 8253/54 will count out the delay and
interrupt the CPU when it has completed its tasks.
It is easy to see that the software overhead is minimum and that multiple
delays can be easily be maintained by assignment of priority levels.

In addition, a count can be read by the CPU while the counter is decrementing.
In this chapter, we are going to study two timer ICs 8253 and 8254. The 8254 is a
superset of 8253.
8253

8254

1. Operating frequency 0 - 2.6 MHz.

1. Operating frequency 0 - 10 MHz.

2. Uses N-MOS technology

2. Uses H-MOS technology.

3. Read-Back command not available.

3. Read-Back command available.

4. Reads and writes of the same counter 4. Reads and writes of the same counter
can not be interleaved.
can be interleaved.

3.1 8253/8254 ARCHITECTURE:

Features:
The 8253/54 includes three identical 16 bit counters that can operate
independently
The CLK, GATE and OUT pins are available for each of the three timer
channels.
To operate a counter, a 16-bit count is loaded in its register and, on command,
it begins to decrement the count until it reaches 0. At the end of the count, it
generates a pulse that can be used to interrupt the CPU.
The counter can count either in binary or BCD.
8254 has additional feature of Read Back Command
It has six operating modes

Data Bus Buffer :

This tri-state, bi-directional,
directional, 88-bit
bit buffer is used to interface the 8253/54 to the
system data bus. The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.
Read/Write Logic :
The Read/Write logic has five signals : RD, WR, CS and the address lines A0
and A1. In the peripheral I/O mode, the RD, and WR signals are connected to IOR
and IOW, respectively. In memory-mapped
memory mapped I/O, these are connected to MEMR and
MEMW. Address lines A0 and A1 of the CPU are usually connected to lines A0 and
A1 of the 8253/54, and CS is tied to a decoded address. The control wor
word register
and counters are selected according to the signals on lines A0 and A1.

Control Word Register :

This register is accessed when lines A0 and A1 are at logic 1. It is used to

write a command word which specifies the counter to be used (binary or BCD), its
mode, and either a read or write operation.
Counters :
These three functional blocks are identical in operation. Each counter consists
of a single, 16 bit, pre-settable, down counter. The counter can operate in either
binary or BCD and its input, gate and output are configured by the selection of
modes stored in the control word register. The counters are fully independent. The
programmer can read the contents of any of the three counters without disturbing the
actual count in process.
3.3 PIN DETAILS:

Pulses applied to the CLOCK input are used to decrement the certain counter
The GATE input is used to enable or disable the certain counter.
The counter produces either a clock or a pulse at the OUT pin depending on
the mode of operation selected.
The 82C54 is rated for a maximum clock frequency of 10 MHz

3.4 Operating Modes of 8253

Each of the three counters of 8253 can be operated in one of the following
six modes of operation.
1. Mode0 (Interrupt on terminal count)
2. Model (Programmable monoshot)
3. Mode2 (Rate generator)
4. Mode3 (Square wave generator)
5.Mode4 (Software Triggered robe)
6.Mode5 (Hardware triggerred strobe)
Mode 0 : Interrupt on terminal count
Normal Operation :
1) The output will be initially low after the mode set operation.
2) After the count is loaded into the selected count Register the output will remain
low and the counter will count.
3) When the terminal count is reached the output will go high and remain high until
the selected count is reloaded.
4) if Gate = 1 enables counting. Gate = 0 disables counting.

MODE 1 : Hardware Retriggerable One-shot

Normal operation
1) The output will be initially high

2) The output will go low on the CLK pulse following the rising edge at the gate
input.
3) The output will go high on the terminal count and remain high until the next rising
edge at the gate input.
4) The one shot is retriggerable, hence the output will remain low for the full count
after any rising edge of the gate input.
5) If the counter is loaded during one shot pulse, the current one shot is not affected
unless the counter is retriggered. If retriggered, the counter is loaded with the new
count and the one-shot pulse continues until the new count expires.

MODE 2 : Rate generator

This mode functions like a divide by-N counter.
1) The output will be initially high.
2) The output will go low for one clock pulse before the terminal count.
3) The output then goes high, the counter reloads the initial count and the process is
repeated.
4) The period from one output pulse to the next equals the number of input counts in
the count register.
5) If Gate = 1 it enables a counting otherwise it disables counting (Gate = 0 ).
6) If Gate goes low during an low output pulse, output is set immediately high. A
trigger reloads the count and the normal sequence is repeated.

MODE 3 : Square Wave Rate Generator

\1) Initially output is high.
2) For even count, counter is decremented by 2 on the falling edge of each clock
pulse.
3) When the counter reaches terminal count, the state of the output is changed and
the counter is reloaded with the full count and the whole process is repeated.
4) If the count is odd and the output is high the first clock pulse (after the count is
loaded) decrements the count by 1. Subsequent clock pulses decrement the clock by
2. After timeout, the output goes low and the full count is reloaded. The first clock
pulse (following the reload) decrements the count by 3 and subsequent clock pulse
decrement the count by two. Then the whole process is repeated. In this way, if the
count is odd, the output will be high for (n+1)/2 counts and low for (n-1)/2 counts.
5) If Gate is 1 counting is enabled otherwise it is disabled. If Gate goes low while
output is low, output is set high immediately. After this, When Gate goes high, the
counter is loaded with the initial count on the next clock pulse and the sequence is
repeated.

MODE 4 : Software Triggered Strobe.

1) The output will be initially high
2) The output will go low for one CLK pulse after the terminal count (TC).

3) If Gate is one the counting is enabled otherwise it is disabled. The Gate has no
effect on the output.

MODE 5 : Hardware triggered strobe (Retriggerable).

1) The output will be initially high.
2) The counting is triggered by the rising edge of the Gate.
3) The output will go low for one CLK pulse after the terminal count (TC).
4) If the triggering occurs on the Gate input during the counting, the initial count is
loaded on the next CLK pulse and the counting will be continued until the terminal
count is reached.

Control Word Register

A control word register used to configure the timer in any one of the six
operating mode. It accepts the 8-bit control word written by the microprocessor and
stores it for controlling the complete operation of the specific counter.

The control word register contents are used for (a) initialising the operating modes
(mode0-mode4) (b) selection of counters (counter0-counter2) (c) choosing
binary BCD counters (d) loading of the counter registers

4.ADC Interfacing with 8086 Microprocessor

4.1 Introduction about ADC:

Analog signal:
The real world is analog.
Signals vary continuously with time.
Analog signals take arbitrarily many values.

Examples:
audio signal from microphone or cassette player
video signal from VCR or video camera
Digital:
The microprocessor world is digital.
Limited number of separate (discrete) values at each time ste
step.
Digital signals take only these values, nothing inbetween.
Computers: Two values (0 or 1) corresponding to low/high value of electrical
property (usually voltage).

4.1.2 Signal Conversion:

To interface microprocessors to real
real-world (analog) systems, we need
converters.
Digital to Analog Converters (DAC): Convert a digital input (e.g. binary
word) to analog output (e.g. current or voltage).
Analog to Digital Converters (ADC): Convert an analog input to digital
output.

The basic principle of operation is to use the comparator principle to

determine whether or not to turn on a particular bit of the binary number
output.
It is typical for an ADC to use a digital-to-analog
digital analog converter (DAC) to
determine one of the inputs to the comparator.
3 Basic Types
Digital-Ramp
Ramp ADC
Successive Approximation ADC
Flash ADC
Conversion from analog to digital form inherently involves comparator action
where the value of the analog voltage at some point in time is compared with
some standard.
A common way to do that is to apply the analog voltage to one terminal of a
comparator and trigger a binary counter which drives a DAC.

Binary search to match input voltage.

Conversion time > n times DAC settling time.
Input should stay stable throughout conversion.
3.1.3 Features
The ADC0809// 808/803/804 is an 8-bit successive approxximation
type ADC
DC with inbu
inbuilt 8-channel multiplexer.

 The ADC0804 is suitable for interface with 8086 micropro

oprocessor.
Compatible with 8080 P derivativesno
derivatives no interfacing logic needed - access
time - 135 ns
Easy interface to all microprocessors, or operates stand alone
Differential analog voltage inputs
Logic inputs and outputs meet both MOS and TTL voltage level specifications
Works with 2.5V (LM336
LM336) voltage reference
On-chip clock generator
0V to 5V analog input voltage range with single 5V supply
No zero adjust required

Interfacing of ADC
C 0804
080 with 8086 microprocessor:

B
Block
Diagram of ADC interfacing with 0804

The successive approximation register (SAR) performs eight iterations to

determine the digital code for input value.
The SAR is reset on the positive edge of START pulse and start the conversion
process on the falling edge of START pulse.
A conversion process will be interrupted on receipt of new START pulse. The
End-Of-Conversion (EOC) will go low between 0 and 8 clock pulses after the
positive edge of START pulse.
The ADC can be used in continuous conversion mode by tying the EOC output
to START input. In this mode an external START pulse should be applied
whenever power is switched ON.

The 256R ladder network has been provided instead of conventional R/2R
ladder because of its inherent monotonic, which guarantees no missing digital
codes. Also the
256R resistor network does not cause load variations on the reference voltage.
The comparator in ADC0804/ADC0805 is a chopper- stabilized comparator.
It converts the DC input signal into an AC signal, and amplifies the AC sign
using high gain AC amplifier.

In ADC conversion process

p
the input analog value is quaantized and each
quantized analog valuee will have a unique binary equivalent.
lent.
The quantization step in ADC0804/ADC0805 is given by,

4.2 DAC Interfacing:

4.2.1 Digital-to-Analog
Analog Conversion
When data is in binary form, the 0's and 1's may be of several forms
such as the TTL form where the logic zero may be a value up to 0.8
volts and the 1 may be a voltage from 2 to 5 volts.

The data can be converted to clean digital form using gates which are
designed to be on or off depending on the value of the incoming signal.
Data in clean binary digital form can be converted to an analog form by
using a summing amplifier.
For example, a simple 4-bit D/A converter can be made with a fourinput summing amplifier.
2 Basic Approaches
Weighted Summing Amplifier
R-2R Network Approach
4.2.2 R-2R Ladder DAC
The summing amplifier with the R-2R ladder of resistances shown
produces the output where the D's take the value 0 or 1.
The digital inputs could be TTL voltages which close the switches on a
logical 1 and leave it grounded for a logical 0.
This is illustrated for 4 bits, but can be extended to any number with
just the resistance values R and 2R.
4.2.3 DAC 1408 Features:
To convert the digital signal to analog signal a Digital-to-Analog
Converter (DAC) has to be employed.
The DAC will accept a digital (binary) input and convert to analog
voltage or current.
Every DAC will have "n" input lines and an analog output.
The DAC require a reference analog voltage (Vref) or current (Iref)
source.
The smallest possible analog value that can be represented by the nbit binary code is called resolution.

The resolution of DAC with n-bit binary input is 1/2nof reference analog
value.

The DAC1408 is an 8-bit, high speed, current output DAC with a typical
settling time (conversion time) of 100
It produces complementary current output, which can be converted
to voltage by using simple resistor load.
The DAC0800 require a positive and a negative supply voltage in the
range of 5V to 18V.
It can be directly interfaced with TTL, CMOS, PMOS and other logic
families.
For TTL input, the threshold pin should be tied to ground (VLC = 0V).
The reference voltage and the digital input will decide the analog
output current, which can be converted to a voltage by simply
connecting a resistor to output terminal or by using an op-amp I to V
converter.

4.3 Sample and hold circuit:

Conversion of Signals over Time:
Time

Must hold input signal while converting.

Sample and hold circuit takes in (samples) analog value and holds it
still while A to D conversion is taking place.

What is the minimum rate S at which the analog input should be

sampled?

Minimum sampling rate S determines the minimum acceptable speed

of A to D conversion.

Sampling

Sampling rate must be high enough so that no information is lost

Sampling Theorem:
Signals can be expressed as weighted sums of harmonic functions.
Shannons Theorem (Nyquist Sampling Theorem):
Theorem)
To sample a bandlimited signal x(t) with no loss of information, the sampling
rate must be at least twice the frequency of the highest frequency component.

4 CRT and PRINTER INTERFACE

CRT Fundamentals:
Early computers communicated with the user with either indicator lamps or
hard copy printers, but today, the primary output device is the electronic
display. This is usually the CRT display, although other technologies are
available. The CRT display uses the same technology as the television.

Figure 5.7 Basic Components of the CRT

The vacuum glass tube has at the end of its neck a heated filament. The
electrons emitted are attracted towards the face of the screen by the electric
field created by the high tension (HT) voltage applied between the cathode
and the anode.
The electron beam is aimed at a particular point on the screen by
passing it through an electromagnetic field generated by the set of deflection
coils in the yoke assembly. Two vertical deflection coils generate a field
perpendicular in X direction of the electrons, allowing the electron beam to be
scanned vertically.
It is the oldest and most popular display technology. Advantages of CRT are
as follows.

Low cost because of volume of production.

Speed of updating and the retention of image is good.
Colour display is available.
Text and graphics display modes.

Disadvantages of CRT are as follows.

Large size and weight: Typical CRT displays are at least as deep as
they are wide
High voltage and power consumption.
Also generate a lot of heat.
CRT displays are glass vacuum tubes, and are therefore relatively
fragile.
The microprocessor interface is relatively complex.
RS 232 Serial Communication Standards:
In serial I/O, data can be transmitted as either current or voltage. When data is
transmitted as voltage, the commonly used standard is known as RS-232C.
This standard was developed by Electronic Industries Association (EIA),
USA and adopted by IEEE. RS-232 standard proposes a maximum of 25
signals for the bus used for serial data transfer.

The voltage levels used for all RS-232C signals are :

Logic Low(0) = -3V to -15V under load (-25V on no load)
Logic High(1) = +3V to +15V under load (+25V on no load)
Commonly used TTL voltage levels are,
+12V (Logic high) and -12V (Logic low)

o The RS-232C signal levels are not compatible with TTL logic
levels.
o For interfacing TTL devices, level converters or RS-232C line
drivers are
employed.
The popularly used level converters are :
1. MC 1488 - TTL to RS-232C level converter.
2. MC 1489 RS-232C to TTL level converter.

CRT CONTROLLER 8275:

A CRT controller generates all the signals and coordinates the supporting
activities for interfacing and controlling a CRT display with a microprocessor.
Intels 8275 is a programmable CRT controller designed to interface raster
scan displays with Intel microcomputer systems.
This device refreshes the display besides storing the display data obtained
from the CPU, in a display buffer (RAM). This also keeps a track of the
current display position pointer (cursor) of the screen and offers different
formats and styles to the display.
5.2 Parallel Printer Interface:
A common standard for interface with parallel printers in the CENTRONICS
parallel interface standard, named for the company that developed it.

There are three general types of signals at the printer interface: data,
control, and status.

5.2.1 Pin discrptions:

Centronics type printers usually have a 36-pin interface connected.
This 36- pin connector fall into two categories,
i.
two control Signals sent to the printer to tell it what operation to
do and ii.
ii.
The five status signals form the printer that indicate its status.
For the most common printers, data to be printed is sent to the printer as
ASCII characters on eight parallel lines.

1.

The major control signals to the printer are INIT on pin 31,
which tells the printer to perform its initialization sequence,

2.

The STROBE on pin1 which tells the printer Here is a character

for you. The two addition input pins pin14 and pin16 are usually
taken care of inside the printer.

The major status signals output from the printer are

1. The ACKNLG signal on pin10, which when low indicates that the
character has been accepted and the printer is ready for the next
character.
2. The BUSY signal on pin11, which is high if, for some reason such
as being out of paper, the printer is not ready to receive a character.
3. The PE signal on pin12 which goes high if the out of paper switch in
the printer is activated.
4. The SLCT signal on pin13, which goes high if the printer is selected
for receiving data
5. The ERROR signal on pin32, which goes low for a variety of
problem conditions in the printer.

PRINTER INTERFACE WITH MICROPROCESSOR:

Operation:
i.
ii.
iii.
iv.
v.

vi.

vii.

For the most common printers, data to be printed is sent to the

printer as ASCII characters on eight parallel lines.
The printer receives the characters to be printed and stores them
in an internal RAM buffers.
When the printer detects a carriage return character, it prints out
the first row of characters from the print buffer.
When the printer detects a second carries return, it prints out the
second row of characters etc.
The process continuous until the desired characters have been
printed.
Transfer of the ASCII codes from a microcomputer to a printer
must be done on a handshake basis because the microcomputer
can send characters much faster than a printer can print them.
The printer must in some way let the microcomputer know that
its buffer is full and that is cannot accept any more characters
until it prints some out.

Timing waveform of data transfer to a Centronics compatible parallel printer

Summary
1.

2.

3.

4.

5.

6.

7.

8.

I/O functions can be done with the help of either simple integrated
circuits or programmable devices. Latches and tri-state buffers are
simple integrated circuits whose capabilities are limited.
On the other hand, a programmable interfacing device is capable of
performing various input/output functions according to the way in
which we program the device.
A matrix keyboard is a commonly used input device when more
than eight keys are necessary. A matrix keyboard reduces the
number of connections and hence reduces the number of interfacing
devices.
The rows and columns of a matrix keyboard do not have any
connection and the connection occurs when a key is pressed. In
other words, we can say that pressing a key shorts one row and
column.
In a matrix keyboard, the major task is to identify a key that is
pressed and decode the key in terms of its binary value. This task
can be accomplished through either software or hardware.
Intel 8279 is the keyboard/display controller that is used to interface
the keyboard and the display of a system to the microprocessor. The
advantage of 8279 is that it is able to drive the signals for both the
keyboard and display and hence it is possible for the microprocessor
to concentrate in its routine tasks.
When a keyboard is interfaced through Intel 8279, the keys are
automatically debounced and the keyboard can operate in two
different modes: Two key lockout or N-key rollover.
In the two key lockout mode, if two keys are pressed almost
simultaneously, only the first key is recognized. In the N-key
rollover mode, simultaneous keys are recognized and their codes are
stored in the internal buffer.

REVIEW QUESTIONS:
1.Explain the command register of 8279?
2.Explain the modes of operations 8255?
3.Describe 8255 pin diagram and functional block diagram?
4.How keyboard is interfaced with 8255?explain with algorithm?
5.Draw and explain architecture of 8279 and write the pin description?

6.Explain 8251 with functional diagram?

7.Explain functional block diagram and pin detail of 8237?
8.Explain functional block diagram and pin detail of 8259?
9.Describe the operating modes of 8254?
10.Draw and explain functional diagram and pin diagram of 8254?
2 MARKS
1. What are the operating modes of 8279?
1. Input modes
Scanned keyboard
Scanned sensor matrix
Strobed input
2. Display modes
Left entry (Type writer mode)
Right entry (Calculator mode)
2. What are the different functional units in 8279?
CPU interface section
Keyboard section
Display section
Scan section
3. What are the operating modes of 8255?
1. Bit set/Reset mode
2. I/O modes
a)mode 0 : Simple input/output
b)mode 1 : Input/output with handshake
c)mode 2 : Bi-directional I/O data transfer
4. What is USART?
It is a programmable device. Its function and specification for serial I/O
can be determined by writing instructions in its internal registers. The Intel
8251A USART is a device widely used in serial I/O.
5. What is use of control register?
It is a 16-bit register used to store the control word. The control word consists
of 2 independent bytes: the first byte is called mode instruction and the second
byte is called command instruction.
6. Write the features of 8255A.

The 8255A has 24 I/O pins that can be primarily grouped primarily in two 8bit Parallel ports: A and B, with eight bits as port C. The 8-bits of port C can
be used as two 4-bit ports:CUPPER CU and CLOWER CL.
7. What is BSR mode?
All functions of 8255 are classified according to 2 modes. In the controlword,
if D7 = 0, then it represents bit set reset mode operation. The BSR mode is
used to set or reset the bits in port C.
8. What is mode 0 operation of 8255.
In this mode, ports A and B are used as two simple 8-bit I/O ports and port C
as two 4-bit ports. Each port can be programmed to function as an input port
or an output port. The input/ output features in mode 0 as follows:
i. outputs are latched
ii. inputs are not latched
iii.

ports do not have handshake or interrupt capability.

9.Define Baud.
The rate at which the bits are transmitted, bits per second is called Baud.
3. What are the signals available for serial communication?
SID serial input data
SOD serial output data
10.What is the use of checksum technique?
The checksum technique is used when blocks of data are transferred.
It involves adding all the bytes in a block without carries. Then the 2s
Complement of the sum is transmitted.
11. List some serial I/O standards.
RS-232C, RS-422A, RS-423A.

12. What is key debouching?

Key bouncing may cause multiple entries made for the same key. To
overcome this problem after a key press is sensed the device is made to wait
for few milliseconds. Then the key is checked again to ensure it is still
pressed. If it is still pressed it is taken as a valid key press. This process is
called keyboard debouching
13. What is ADC and DAC?
The electronic circuit that translates an analog signal into a digital
signal is called analog-to-digital converter(ADC).
The electronic circuit translates a digital signal into an analog signal is
called Digital-to-analog converter(DAC).
14. .Define conversion time.
It is defined as the total time required to convert an analog signal into a
digital output. It is determined the conversion technique used and by the
propagation delay in various circuits.
15. Write the features of RS-232.
It operates in single-ended mode.
The maximum cable length can be up to 50 feets.
Ti supports maximum data rate of up to 20 K.
It offers receiver input resistance in the range of 3k to 7k.

16. Write the different types of ADC.

i. Single slope ADC
ii. Dual slope ADC
iii. Successive approximation ADC
iv. Parallel comparator type ADC
v. Counter type ADC

17.What is resolution time in ADC?

It is defined as a ratio of change in value of input voltage Vi, needed to
change the digital output by 1 LSB. If the full scale input voltage required to
cause a digital output of all 1s is ViFS. Then the resolution can be given as
Resolution = ViFS / (2n-1)

EC 2304 MP & MC

R.RAMACHANDRAN

UNIT III

INTERFACING CONCEPTS

Page 53