Datasheet
Design Compiler 2010
Doubles Productivity of Synthesis and Place and Route
Overview
Continuing the trend of delivering
innovative synthesis technology,
Synopsys offers Design Compiler
2010 that provides a twofold
speedup of the synthesis and physical
implementation flow. As geometries
shrink to 65nm and smaller process
technologies, design complexities
increase multifold making it extremely
difficult for designers to complete
designs on schedule. The nanometer
effects such as coupling capacitances
between parallel interconnects have
much higher impact on interconnect
delays and need to be considered
during synthesis for predictable design
implementation. Moreover, floorplan
issues, such as routing congestion
due to macro placement, need to
be fixed early in the design cycle to
avoid iterations. Designers need an
RTL synthesis solution that improves
schedule predictability by producing
a better starting point to physical
implementation and avoids costly
iterations between synthesis and
place-and-route.
Design Compiler 2010 extends topographical technology to produce physical
guidance to IC Compiler, place-and-route solution, tightening timing and area
correlation to 5% while speeding-up IC Compiler placement by 1.5X. It applies
additional physical optimization techniques and considers the effects of smaller
geometries such as coupling capacitances for accurate delay modeling. The
physical guidance passed to IC Compiler streamlines the flow for a faster,
predictable design implementation. Design Compiler 2010 also provides RTL
designers access to IC Compilers design planning capabilities from within the
synthesis environment. With the push of a button, RTL designers can perform
what-if floorplan exploration to identify and fix floorplan issues early and achieve
an optimal floorplan efficiently. Additionally, Design Compiler 2010 includes a new,
scalable infrastructure designed to deliver significant runtime speedup on multicore
compute servers. It employs an optimized scheme of distributed and multithreaded
parallelization techniques, delivering 2X faster runtime on quad-core compute
servers while ensuring zero deviation of the synthesis results. With these new
technology advances, Design Compiler 2010 helps designers reduce iterations and
cut synthesis and placement runtime significantly.
Doublestheproductivity
ofSynthesisandP&R
Design Compiler
2010
Physical
guidance
IC Compiler
Figure 1: Design Compiler 2010
Key Benefits
Timingcorrelation
``
Better starting point for physical
12%
implementation
``
5% Correlation to layout
10%
``
Push-button floorplan exploration
``
2X faster runtime on quad-core
compute servers
Physical Guidance to IC
Compiler
% Correlation
``
1.5X faster placement runtime
8%
Without physical
guidance
With physical
guidance
6%
4%
2%
With designs becoming more
complex along with shrinking
0%
Designs
geometries, designers require even
Figure 2: Timing correlation
tighter correlation between synthesis
and layout results. Additionally, as
geometries become smaller, the
coupling capacitance between adjacent
parallel wires is much higher due to
the fact that spacing between wires is
10%
coupling capacitance is much higher
on design delays and needs to be
accounted for in synthesis.
% Correlation
smaller and the relative heights of the
wires are greater. Hence the impact of
Areacorrelation
12%
8%
Without physical
guidance
With physical
guidance
6%
4%
Topographical technology in Design
2%
Compiler 2010 is extended to create
physical guidance for IC compiler
0%
bringing synthesis timing and area
Designs
results within 5% of layout while
Figure 3: Area correlation
speeding up IC Compiler placement
step by 1.5X. It performs additional
physical optimizations during synthesis
to create a better starting for physical
implementation and accurately models
the effects of smaller geometries such
10%
physical guidance to streamline the
implementation flow and accelerate
placement runtimes.
% Correlation
as coupling capacitance. It further
seeds IC Compiler placement via
Areacorrelation
12%
8%
Without physical
guidance
With physical
guidance
6%
4%
2%
0%
Designs
Figure 4: IC Compiler placement runtime
Design Compiler 2010
Figure 5: Routing congestion identified in Design Compiler
Figure 7: Floorplan editing to address routing congestion
Figure 6: Accessing IC Compiler design planning within synthesis
Figures 2 and 3 illustrate improvements
in timing and area correlation,
respectively, across multiple designs
using physical guidance. On the X-axis
are the designs and the Y-axis is %
delta between synthesis and layout
results. The light purple bars (on the
left) show the delta between synthesis
and layout without passing physical
guidance. The purple bars show the
delta for the same designs with physical
guidance technology. As shown in
these figures, results are consistently
within 5% when physical guidance is
passed from Design Compiler 2010 to
IC Compiler. Figure 4 shows placement
runtime improvements using physical
guidance technology. On the X-axis
are the designs and on the Y-axis are
the runtimes in hours. The light purple
bars represent IC Compiler placement
runtime without physical guidance and
the purple bars represent IC Compiler
placement runtime with physical
guidance. As illustrated by the figure IC
Compiler placement runtime is much
faster when physical guidance is passed
from Design Compiler 2010, averaging
1.5X faster.
Design Compiler 2010
Push-Button Floorplan
Exploration for Faster Design
Convergence
Until now, if changes to design
floorplans were needed, RTL designers
is transparent to users hence no setup or data transfer is required. Once
the designer has created an optimal
floorplan, they can save it to be used for
physical implementation downstream.
had to ask their counterparts on
Figure 5 shows an example of design
physical design teams to adjust the
layout where congestion hot spots
floorplan, resulting in iterations between
occurred due to a very narrow channel
the teams. With immense time-to-
between macros as shown in Design
market pressures, designers need a
Compiler Graphicals layout viewer. A
solution to reduce these iterations.
click on the Start Design Planning
Design Compiler 2010 provides RTL
menu option in Design Compiler (see
designers access to IC Compiler design
Figure 6) opens a new IC Compiler
planning capabilities from within the
design planning window with the design
familiar synthesis environment. After
floorplan loaded for editing. With very
detecting design issues, such as routing
few maneuvers RTL designers can
congestion or timing violations due to
move the macro to eliminate this narrow
floorplan characteristics, RTL designers
channel as shown in figure 7. Once the
can now amend the floorplan and re-
floorplan edits are made, designers can
synthesize the design with an updated
save the floorplan as shown in figure 8
floorplan without ever leaving the
and re-synthesize the design with the
synthesis environment. The IC Compiler
updated floorplan. As shown by the
design planning menus have been
congestion map in figure 9, with the
simplified to give RTL designers ease of
updated floorplan, routing congestion
use for simple floorplan modifications.
has been eliminated and the design is
An option is available for expert users to
ready for physical implementation.
utilize the full, advanced floorplanning
capabilities. The Design Compiler 2010
and IC Compiler design planning link
Figure 8: Saving floorplan updates
Figure 9: Congestion eliminated
2XFasterruntimeon4cores
20
Single core
runtime
16
Multicore
runtime
12
Conclusion
The new technology advances in Design
Compiler 2010 double the productivity
of synthesis and place and route by
0
350k
368k
473k
650k
836k
880k
1.2m
2.7m
Figure 10: Synthesis runtime
Design Compiler 2010 helps RTL
parallelization, Design Compiler 2010
designers perform a what-if analysis of
delivers a 2X improvement in runtimes
floorplan quickly and efficiently so that
on quad core platforms. The new
they can be ensured that the design
infrastructure delivers runtime benefits
will meet its targets during physical
without deviating the quality of results.
implementation without requiring
Figure 10 compares Design compiler
iterations.
2010 runtimes across multiple designs
New Infrastructure for
Multicore
on single core vs. quad core machines.
On the X-axis are designs and on the
Y-axis are the runtimes in hours. The
enabling RTL designers to achieve an
optimal floorplan efficiently, delivering
5% correlation to layout and 1.5X faster
placement runtimes, and 2X faster
synthesis on quad core platforms.
Availability
Technologies of Design Compiler
2010 are available today. The
physical guidance to IC Compiler and
floorplan exploration are available in
Design Compiler Graphical. The new
infrastructure for multicore compute
servers is available in DC ultra and
The advent of multicore processors
light purple bars represent Design
Design Compiler Graphical.
in compute platforms has boosted
Compiler 2010 runtimes using a single
For more information about Synopsys
the processing power available to
core machine and the purple bars
products, support services or
designers. Design Compiler 2010
represent runtimes using quad core
training, visit us on the web at:
introduces a new scalable infrastructure
machines for the same [Link] seen
[Link], contact your
to take advantage of multicore compute
in the figure, Design Compiler 2010 is,
local sales representative or call
servers. Using an optimized scheme
on average, 2X faster on quad core
650.584.5000.
of distributed and multithreaded
compute servers.
Synopsys, Inc. 700 East Middlefield Road Mountain View, CA 94043 [Link]
2010 Synopsys, Inc. All rights reserved. Synopsys is a trademark of Synopsys, Inc. in the United States and other countries. A list of Synopsys trademarks is
available at [Link] All other names mentioned herein are trademarks or registered trademarks of their respective owners.
06/[Link].10-18763.
