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Overview UdS Electronics and Circuits
Overview UdS Electronics and Circuits
Chair of
Electronics and Circuits
Exploring Limits:
Development of Integrated
HighPerformance Circuits
Saarland
Trier
Belgium
Networks
Mainz
Saar
land
Kaisers
lautern
(Sarre)
Innovations
Cluster
Luxem
bourg
University
Education Research
Economy
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Manpower
France
Saarbrcken
(Sarrebruck)
Strasbourg
Infrastructure
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Growth
Saarland University
Universitt des Saarlandes (UdS)
Campus Saarbrcken
1948 founded
15.500 students
290 professors
800 other academics
900 nonacademic
staff members
Cooperative study
France
Luxembourg
Departments
Course of studies
Mathematics
Electronics
Mechatronics
Physics
Microsystem Technology
Mechanics
(Micro/Nano)
Information&
System technology
Obligatory lectures
Solid State Electronics (El. I)
Mechatronics
Microsystem Technology
Micro and Nanostructures
Electronics
Mechanics
(Micro/Nano)
Information&
System technology
*: coming soon
Research Structure
Research Area:
Research Focus:
Research Topics:
Physical Modeling of Circuit Elements and Parasitics
Modeling
Circuit Design
Realization
Measurement Techniques
Characterization
Realization
Characterization
area
Realization
Assembly Techniques
Utilized Parasitics
TML Interfaces
topic
Technology evaluation
Analogue performance
HighSpeed & Low power
Parasitic effects
Characterization
area
metods
Wiring parasitics
TML models
Layer peeling
Similarity & mapping
area
Physical models
Broadband models
Building block moding.
Auto. mod. generation
topic
area
Modelling
topic
Circuit Design
1991
1995
1997
1998
1999
2000
43.5 Gb/s fully integrated SONET/SDH RZ/NRZ CDR & TIA & DEMUX **
2001
43.5 Gb/s SONET/SDH RZ/NRZ 16:1 MUX with 20/40 GHz Clock output **
2002
2004
2006
MUX, CDR & DEMUX modules for experiments at > 100Gbit/s (MultiTeraNet) **
*developed @ Ruhr University Bochum, Prof. Rein
** developed @ MICRAM Microelectronic GmbH
Research Activities
Ongoing
Concepts and techniques for dual mode operation of linear differential circuits.
Automatic measurement of differential Sparameters with ordinary VNA.
Automatic generation of physical models for 2nports from Sparameter measurements.
Realtime circuit simulation by analogue parallel computing.
Planned
Demonstrator circuits for future 100 Gbit/s Ethernet.
Circuit concepts for highspeed driver circuits exeeding VCEO limit.
Circuit concepts for low power highspeed circuits in bipolar technology.
Figures of merit for technology selection by performance criteria.
Measurement Capabilities
Measurement equipment partly located at and shared with industrial partners
HighSpeed Measurement
100 Gb/s pattern generation.
100 Gb/s BER testing.
100 GHz spectrum analysis.
110 GHz S parameter measurements.
50 (80) GHz Sampling scope
On wafer measurements up to 100 Gb/s in clean room.
Even, odd, and conversion mode measurements (freq.&time domain).
All measurements can be carried out for single ended as well as differential devices.
Test/Preselection
Functional & Parametric test on Wafer and Modules at small volumes.
RFmodule technology
Soft Substrates for highspeed, highdensity applications:
PTFE/Polymer based,
bandwidth greater 100 GHz,
dielectric constants of 2.2 ... 10.8,
arbitrarily shaped substrates,
plated through holes,
edge metallization,
fine pitch resolution with 2 mil lines/spaces.
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