A

SEMINAR REPORT
On
Practical Traning
DIGITAL DESIGN USING VHDL
Submitted
In partial fulfillment
For the award of the degree of
Bachelor of Technology
in Department of Electronics and Communication Engineering

RAJASTHAN COLLEGE OF ENGINEERING FOR WOMEN

Submitted to:

Submitted by:

Mr. Roshan Jain

Pinky

H.O.D

(9E1RWECF30P066)

ECE

B.Tech VII Sem

Department of Electronics & Communication Engineering
Rajasthan College of Engineering for Women

Bhankrota, Jaipur
2012-2013
V

RAJASTHAN COLLEGE OF ENGINEERING FOR WOMEN

JAIPUR

Certificate
Certified that this is a bonafide record of the seminar report titled
DIGITAL DESIGN USING VHDL
done by
PINKY
9E1RWECF30P066
of VII semester , B.Tech in the year 2012-2013 in partial fulfillment of
requirement for the Degree of Bachelor of Technology in
ELECTRONICS & COMMUNICATION ENGINEERING OF
RAJASTHAN COLLEGE OF ENGINEERING FOR WOMEN
Mr. Lokesh Sharma

Date: 21-9-2012

Miss. Khushboo Gupta

PTS Supervisor

ACKNOWLEDGEMENT
Writing an acknowledgement for this training report seems bit confusing to me. There are many
hands behind my success. I really thanks to them, I am afraid, I may miss someone to thanks if I
am, then I am sorry.
It is my great pleasure to present Training report on Digital Design Using VHDL for
Department of ECE, RCEW,Jaipur.
I take this opportunity to express my deepest and sincere thanks to Mr. CS Lamba sir for his
constant encouragement.
I do express my special thanks to Mr. Roshan Jain H.O.D Department of ECE.
I also express my special thanks to Mr. Lokesh Sharma sir and Miss Khushboo Gupta mam.
I want to say great thanks to Mr. Ravi Saini to help me out from all the difficulties and problems
which I got in this report.
I owe my thanks not only to those who help me in the training report but also to those friends and
family that have supported and encourage to move forward. I would like to take this opportunity
to acknowledge to my graduate to all the person who have helped and supported in the
completion of this training report.

PINKY
09ERWEC066
B.Tech, IV year, ECE

PREFACE

This report describes a practical training based on digital design using vhdl which was done
under the supervision of Mr. Ravi Saini. The objective of this practical training was to approach
to make VHDL based real time applications working on digital logic. The hardware and software
tools used are those manufactured and developed by Altera and the VHDL circuit has been
designed on a CPLD kit. A basic understanding of electronic devices, digital electronics and
VHDL software and hardware tools is a pre-requisite.

CONTENTS
TOPIC

PAGE NO.

ACKNOWLEDGEMENT

PREFACE

II

CEERI PROFILE

III-IV

LIST OF FIGURES

CHAPTER-1.
VLSI Design Overview

1-4

1.1 Design Overview

1.2 Design Flow Using HDL

1.3 Steps in VLSI Design

CHAPTER-2

5-23

Introduction to VHDL
2.1 Basic Language Elements

2.2 Describing a design

2.3 Architecture Body

15

2.4 Dataflow Modeling

15

2.5 Behavioral Modeling

16

2.6 Structural Modeling

19

CHAPTER-3
Introduction to Synthesis

24-25

CHAPTER-4
Combinational Circuit Design

26-37
V

4.1 Adder
4.2 Decoder

26
31

4.3 Multiplexer

35

CHAPTER-5
Sequential Circuit Design

38-46

CONCLUSION

47

REFERENCES AND BIBILIOGRAPHY

48

ABSTRACT
This report is a study report on VHDL submitted in partial fulfillment of the requirements for the
degree of B.Tech in Electronics and Communication Engineering from Rajasthan college of
engineering for women.
This report gives a detailed idea about VHDL and the various modeling styles used in VHDL.
The first chapter VLSI design overview gives the basic idea about the hardware modeling
using VLSI, the design flow using Hardware Description Languages (HDL) and the steps
involved in VLSI design.
The second chapter Introduction to VHDL goes through the basic language elements, then the
various hardware modeling styles.
The third chapter Introduction to Synthesis gives a brief idea of the synthesis procedure
involved.
The fourth chapter VHDL-A Logical Synthesis Approach describes the various design units
involved and also the schematic flow of simulation cycle.
The fifth chapter Combinational Circuit Design describes the circuit design styles for the
combinational circuits with various diagrams of adders, decoders, and multiplexers.
The sixth chapter Sequential Circuit Design describes the circuit design styles for the
sequential circuits.

CENTRAL ELECTRONICS ENGINEERING RESEARCH INSTITUTE

PILANI (RAJASTHAN)
CEERI PROFILE
Central Electronics Engineering Research Institute, popularly known as CEERI, is a constitute
establishment of the Council of Scientific and Industrial Research (CSIR), New Delhi. The first
Indian Prime Minister Pt. Jawaharlal Nehru laid the foundation stone of the institute on 21st
September 1953. The actual R and D work started towards the end of the 1958. The institute has
since then blossomed into a center for development of technology and for advanced research in
electronics. Over the years the institute has developed a number of products and processes and
has established facilities to meet the emerging needs of electronics industry.
CEERI pilani is a pioneer research institute in the country. Since its inception it has been
working for the growth of electronics in the country and has establish the required infrastructure
and well experienced men power for undertaking R and D in the following three major areas:

Electronics System Area

Semiconductor Devices Area

Microwave Tubes Area

There are over 12 groups working on the various fields, on the frontiers of knowledge in these
thrust areas:
ELECTRONICS SYSTEM AREA for industrial, agriculture and transportation applications.
SEMICONDUCTOR DEVICES AREA for power devices, microelectronics devices, millimeter
devices and hybrid microcircuits.
MICROWAVE TUBES AREA for defense and communication.
V

ELECTRONICS SYSTEM AREA

Industrial Electronics Group (IEG)

Agri Electronics Group (AEG)

Digital System Group (DSG)

Information Technology Group (IFC)

SEMICONDUCTOR DEVICES AREA

Devices group devices processing

Hybrid Microcircuits Group (HMG)

IC Design Group (IDG)

Microwave Devices Group (MDG)

Opto Electronics Group (ODG)

Semiconductor Material Group (SMG)

MICROWAVE TUBES AREA

Communication Tubes group (CTG)

Industrial Tubes Group (ITG)

The main thrust of the R&D efforts traditionally carried out by CEERI has been directed towards
the collaborative or grant-in-aid research projects. These projects are funded by Government
Departments and Government funded user agencies and to a lesser extent, towards in-house
development projects resulting in technological know-how, which can be transferred to Indian
industries. With dwindling support for capital resources needed for state-of-the-art research, it
has now become much more difficult to find the support for developmental activities, which can
lead to competitive products or process of interest to industry.
In this way CEERI has under one roof, an advanced comprehensive program of development for
power semiconductor devices as well as specific integrated circuits and electronics systems for
various applications.
CEERI achievements have contributed significantly towards important substitution and selfreliance. Advanced training programs, seminars, symposia, workshops etc. are being organized
by CEERI, pilani regularly. CEERI has also put a lot of emphasis in the development of and
efficient software packages.

Candidates Declaration
2
I hereby declare that the work, which is being presented in the Dissertation, entitled Digital
Design Using VHDL

in partial fulfillment for the award of Degree of Bachelor of

Technology in Department of Electronic & Communication Engineering, and submitted to the

Department of Electronic & Communication Engineering, Rajasthan College of Engineering for
Women, Rajasthan Technical University, kota is a record of my own investigations carried under
the Guidance of Mr. Lokesh Sharma of ECE. Department, Rajasthan College of Engineering
for Women.

I have not submitted the matter presented in this Dissertation any where for the award of any
other Degree.

Pinky
9E1RWECF30P066
B.Tech. VII sem
(ECE)

Ms. Khushboo Gupta

PTS

LIST OF FIGURES
S. No.

Figures No.

Descriptions

Page No.

1.

Figure 2.1

Structure of an Entity

15

2.

Figure 4.1

Half Adder

27

3.

Figure 4.2

Full Adder

28

4.

Figure 4.3

Full Adder(truth table, logic, logic symbol)

30

5. S Figure 4.4

Ripple Carry Adder

31

6.

Figure 4.5

3-to-8 decoder

33

7.

Figure 4.6

3-to-8 decoder implemented with seven 1-to-2

33

decoder
8.

Figure 4.7

2-to-1 multiplexer

35

9.

Figure 5.1

Block diagram of Sequential circuit

38

10.

Figure 5.2

Simulation trace for the positive edge triggered

43

D-flip flop
11.

Figure 5.3

4-bit serial-to-parallel to shift register

45

12.

Figure 5.4

Sample simulation trace for the 4-bit serial-in-

46

parallel-out shift register