ICSET 2008

SEPIC Converter with Continuous Output Current and Intrinsic

Voltage Doubler Characteristic
Esam H. Ismail, Senior Member, IEEE and Abbas A. Fardoun, Senior Member, IEEE


AbstractA novel single switch two diodes wide conversion

ratio step down/up converter is presented. The proposed
converter is derived from the conventional Single Ended
Primary Inductor Converter (SEPIC) topology and it can
operate into a capacitor-diode voltage multiplier, which offers
simple structure, reduced electromagnetic interference (EMI),
and reduced semiconductors voltage stress. The main
advantages of the proposed converter are the continuous
output current, higher voltage conversion ratio, and near zero
input/output current ripples compared with the conventional
SEPIC converter. The principle of operation and comparison
with the conventional SEPIC converter are presented. The
performance of the proposed converter is verified through
computer-aided simulations and experimental results.

I. INTRODUCTION
WITCHED mode power supplies (SMPS) are used
widely in consumer electronic appliances. They are
designed with the intent to pass the electromagnetic
compatibility (EMC) certification test which is mandatory
and vital for some applications like telecommunication,
automotive, and medical equipments. Designing high
performance power converter with low cost, small size, and
high efficiency make the electromagnetic interference
(EMI) design a more challenging task. The designing task
becomes even more difficult for applications that demand
wide range of voltage gain with reduced input and output
current ripple. For these applications, the Cuk converter
seems to be a potential candidate within the basic converter
topologies [1]. The flyback converter requires and
additional input/output L-C filter to reduce the switching
ripple and noise level at both terminals. Moreover, it was
shown in [1], that the Cuk converter is more efficient than
the flyback converter with the input filter. The boost
converter with an output filter results in a more bulky
converter when compared to the Cuk converter. This is
because the input and output inductor cannot be coupled
into a single magnetic core as in the Cuk converter [2].
The SEPIC converter [3] has similar advantages as the
Cuk converter; both have the same DC voltage gain, low
input noise, and overload protection feature. In addition,
both converters have adequate level of intrinsic immunity

Manuscript received April 29, 2008.

E. H. Ismail is with Electrical Engineering Department, College of
Technological Studies, P.O. Box: 35007, AL-Shaab, Kuwait, 36051
(phone: +96599788776; fax: +9655381284; e-mail: eismail@ieee.org).
A. A. Fardoun is with Electrical Engineering Department, University of
United Arab Emirates, P.O. Box: 17555, Al-Ain, UAE (e-mail:
afardoun@uaeu.ac.ae).

to electromagnetic interference (EMI) when a coupled

inductor techniques is implemented to achieve near zeroripple input current [4]-[5]. Moreover, unlike Cuk
converter, SEPIC converter does not suffer from an output
polarity inversion but it requires an additional output L-C
filter to maintain continuous output current.
The main disadvantage of the single switch topologies
presented above is the need for the high voltage blocking
capability of the active power switch; hence, they require a
MOSFET with a higher RDS-ON leading to higher cost and
conduction losses. Moreover, in conventional pulse-width
modulation (PWM) dc-dc converter topologies operating in
continuous conduction mode (CCM), maximum attainable
dc conversion ratios are limited in practical applications by
the maximum duty cycle (D) of the converter. On the other
hand, extreme duty cycles impose inefficiently small offtimes or low switching frequencies. Small off-times cause
severe diode reverse-recovery current, which will increase
the EMI level. Lower switching frequency causes higher
ripple current and increase magnetic components [6]. Thus,
the net results are increased size and degrading the overall
converter efficiency.
In order to overcome these problems, a modified boost
topology is proposed in [7] with some significant features
of reduced switch voltage stress, wide dc conversion ratio,
and continuous output current as compared with the
conventional boost converter. Detail analysis of this
converter is presented in [8].
This paper presents a new high performance singleswitch DC-DC converter. The proposed converter in Fig.1
is based on the SEPIC configuration, with the output
capacitor replaced by two identical capacitors connected
through two diodes in a way that they can be charged in
parallel and then discharged in series through the load. The
operation of the new converter is similar to the
conventional SEPIC, but it posses several substantial
performance advantages, most notably are: 1) Higher step
up/down voltage conversion ratios. 2) Lower voltage stress
on the semiconductor devices, thus alleviating the
conduction losses. 3) Continuous input and output current.
4) Reduced ripple current in the output capacitor reduces
the output ripple voltage and allows the use of smaller and
less expensive output capacitors.
In the modified converter, the absence of both a
transformer and an extreme duty cycle permits the proposed
converter to operate at high switching frequencies. Hence,
the overall advantages will be: higher efficiency, reduced

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size and weight, simpler structure and control.

The modified converter structure utilizes three inductors
which is often described as a disadvantage. However, the
three inductors can be coupled on the same core [4],
allowing considerable size and cost reduction and
additionally, the 'zero-ripple-current' condition at both the
input and output terminal can be reached without
compromising performance. This condition is very
desirable, because the generated EMI noise is minimized,
dramatically reducing input and output filtering
requirements. Moreover, the 'zero-ripple-current' at both the
input and output terminal can be also obtained in
discontinuous conduction mode (DCM). This is a very
desirable feature for power factor correction (PFC)
applications since it will dramatically reduce the high
switching ripple current.

C1

L1

D1
C

Vg

L2

+
Co

Vo

RL

D2

Fig. 1. Proposed modified SEPIC converter.

+ VC1 -

+ VL1 iL1

L1

C1
VL2
+

Vg

+
VC
-

iL1

C1

+
VS
-

Vg

VL2
+

+ L3 iL3
VC
-

Co

Vo

iC

Io

RL

+ VD -

+ VC1 -

L1

C C

L2

a) Switch on topology

+ VL1 -

+ VL3 -

- VD +

iL2

iS

II. BASIC OPERATION OF THE PROPOSED CONVERTER

Fig. 1 shows the proposed SEPIC converter with
continuous
output
current
and
voltage-doubler
characteristics. As can be seen from Fig. 1, the proposed
circuit resembles the conventional SEPIC converter except
that its output port has been modified to include two
identical capacitors C connected through two diodes
followed by L3-Co filter. The two capacitors C appear in a
parallel configuration during the switch off-time, hence
they are charged equally by the energy stored in the filter
inductors L1, L2, and L3. During the switch on-time, the two
capacitors C are discharged in series through the load and
the filter inductor L2. Thus, for the same duty-cycle, the
proposed converter is capable of supplying an output
voltage level twice as much than the conventional SEPIC
converter.
When the converter operates in continuous conduction
mode (CCM), then the ac ripples in all inductor currents
can be assumed to be negligible. Based on this, the circuit
operation in one switching cycle (Ts) can be divided into
two stages as shown in Fig. 2(a-b). The operational mode is
described briefly next.
Stage 1 [t0, t1], Fig. 2(a): when the power switch S is
turned-on, diodes D1 and D2 are turned-off by the negative
voltage -(Vg + VC) across them. In this stage, the current
through both the C capacitors are the same, and it is equal
to the negative inductor L3 current. Thus, in this stage, both
capacitors C are effectively in series charging the load. At
the end of this interval, the switch S is turned-off initiating
the next subinterval.
Stage 2 [t1, Ts], Fig. 2(b): At the instant tl, switch S is
turned-off, both D1 and D2 are turned-on simultaneously
providing a path for the input and output inductor currents.
In this stage, the two capacitors C are effectively in
Parallel; hence, they are being charged equally.
The volt-second relationship of inductor L1, L2, and L3
gives the following relations

L3

+
VC
-

D1

+ VL3 -

iD1

+ L3 iL3
VC
-

Co

Vo

C C

L2

iC

iL2

Io

RL

iD2
b) Switch off topology

D2

Fig. 2. Topological stages for the converter of Fig. 1.

Vg

D '  V C 1 V C 

(1)

VC1

Dc
VC
D

(2)

Vo

 2 D  D c V C

 D VC1

(3)

respectively, where D'=1-D is the normalized switch-off

time and D is the switch duty-cycle. The input to output
voltage transfer ratio of the proposed converter can be
determined from (1) - (3),as
Vo
D
(4)
M
2
Vg
D'
It is clear from (4) that the voltage gain is twice the
voltage gain of conventional SEPIC converter.
III. COMPARISON BETWEEN THE PROPOSED AND THE
CONVENTIONAL SEPIC CONVERTER
A. Duty-Cycle D
In comparison with the conventional SEPIC converter,
the proposed converter operates at lower duty ratio for the
same overall conversion ratio. The relation between the
respective duty ratios D and DC is obtained from

2D
1 D

DC
1  DC

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(5)

TABLE I.
A COMPARISON BETWEEN CONVENTIONAL SEPIC AND PROPOSED SEPIC
TOPOLOGY OPERATING IN CCM
Proposed Converter
SEPIC
Item
(Fig. 1)
Converter

where the subscript s C s is used to refer to the

conventional SEPIC. Solving for D in (5) gives,
DC
(6)
D
2  DC
it is clear from (6) that D is always less than DC. This is an
attractive feature for high DC voltage gains, since the
conventional SEPIC converter must operate at extremely
high duty-cycle ratios. This means that the output diode in
the SEPIC must sustain a short pulse width current with
high amplitude. Thus, resulting in severe reverse-recovery
as well as high EMI problems.

C. Active Switch Utilization

Active switch utilization factor U, which is defined as
the converter output power divided by the total product of
the peak voltage times the rms current through the given set
of converter active switches, represents how well a circuit
topology uses the capability of its switches to achieve the

Switch rms current

1 M
M

M ( 2M )

1

Diode rms current

Diode average
current

M ( 1 M )

M
2

1 M

output power [9]. Converters having high values of U factor

implies the power that a switching device processes for a
given output is reduced, which can alleviate conduction and
switching loss, hence it operates with relatively higher
efficiency. Thereby, evaluating active switch utilization
factor is a good tool to compare different converter
topologies. The U factor for the proposed topology is given
by

M
(2  M )3

(7)

whereas for the conventional SEPIC converter is given by

UC

1  M

(8)

Graphical representation of (7) and (8) are shown in Fig.

3. The maximum U factor for both converter is equal to
0.385, whereas both converters have the same value of
U=0.377 when M=0.7. It is clear from Fig. 3 that for values
of M>0.7, the switch is utilized much better in the proposed
topology than the switch in the conventional SEPIC
converter.
0.5

Active switch uitlization, U

B. Semiconductors Stresses
The comparison between the semiconductors normalized
stresses for the proposed SEPIC topology and conventional
SEPIC converter are listed in Table I. Voltages and currents
are normalized with respect to Vo and Io, respectively.
Referring to Table I, it can be seen that the proposed SEPIC
topology has lower switch and diode blocking voltages than
the conventional SEPIC converter. Moreover, the switch
voltage stress in the proposed SEPIC topology decreases as
M increases, approaching half of the output voltage in the
limit. This is unlike the conventional SEPIC converter
where the switch voltage stress approaches the output
voltage for high values of M. Thus, the proposed converters
enable the use of a lower voltage rated with low RDS-ON
MOSFET switch that are smaller and less costly; hence, it
reduces switch conduction and turn-on losses.
Table I also shows that the average diode current in both
the proposed topology and the conventional SEPIC are
equal to the output load current Io. However, the peak diode
current in the proposed topology is lower than its
counterpart in the conventional SEPIC converter.
Consequently, the diode root-mean-square (rms) current is
lower for the proposed topology. On the other hand, the
switch current in the proposed convert is equal to the sum
of the three inductor currents, whereas in the conventional
SEPIC the switch current equals to the sum of two inductor
currents. As a result, the switch rms current in the proposed
converter is slightly higher than its counterpart in the
conventional SEPIC. This is the main disadvantage of the
proposed converter. However, this does not mean that the
switch conduction loss in the proposed converter is much
higher than the switch conduction loss in the conventional
SEPIC, since the power switch in the proposed converter
has lower voltage stress with lower RDS-ON.

2M
2M

Peak switch and

diode voltage

Proposed Topology
Conventional Sepic

0.4
0.3

M=0.7

0.2
0.1
0.0

Voltage conversion ratio, M

Fig. 3. Active switch utilization U as a function of voltage conversion

ratio, M.

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D. Output Capacitor Co
The expression of the normalized output voltage ripple
for the proposed converter of Fig. 1 is given by

'vo / 'vo-C

T s2
8 L3 C o (2  M )

'v o
Vo

0.20

(9)

Ts
M
u
RL Co 1 M

(10)

1
1 M
u
4 K 3 M (2  M )

(11)

where

K3

2 L3
R LT s

(12)

Unlike the conventional SEPIC converter, (9) shows that

the output voltage ripple is independent of load. Moreover,
for CCM operation, the defined ratio in (11) is always less
than one when M>0.13. Another advantage of the proposed
converter over the SEPIC converter is the low peak ripple
current through the output capacitor Co due to the absence
of the output diode. Thus, it is possible to use output
capacitors with higher equivalent-series-resistance (ESR)
than would be allowed for a conventional SEPIC converter.
The ratio between the rms currents for the proposed
topology and the SEPIC converter is given by,

I Co  rms
I Co  rms C

1
K 3 2  M 

3M

(13)

Graphical representation of (11) and (13) are shown in

Fig. 4 for several values of K3. The minimum value of K3
that will insure the converter of Fig. 1 to operate in CCM is
0.75 (assuming that L1=L2=L3). It is clear from Fig. 4 that
the proposed SEPIC topology has an advantage of lower
output voltage ripple and output capacitor rms current over
the conventional SEPIC converter. Moreover, the reduction
in both the voltage ripple and the rms current becomes
more pronounced with increasing M. For example, consider
when K3=1 and M=5, output voltage ripples are 24 times
less, and the rms current through the output capacitor is 27
times less, than the conventional SEPIC converter.
E. Input Current Ripple
The peak-to-peak input inductor current ripple ('iL1) in
both the proposed and the conventional SEPIC converters
are proportional to the operating duty-cycle, hence, their
ratio is given by

0.20

For comparison purpose, the ratio between (9) and (10)

result in

'v o
'v o C

0.05
0.00

ICo-rms / ICo-rms-C

'v o C
Vo

0.10

(a)

In conventional SEPIC converter, the output capacitor

supplies the entire output load current during the switch ontime. Thus, the normalized output voltage ripple for the
conventional SEPIC converter is given by,

K3=1
K3=2
K3=5

0.15

K3=1
K3=2
K3=5

0.15
0.10
0.05
0.00

Voltage conversion ratio, M

(b)

Fig. 4. a) Output voltage ripple ratio, b) Output capacitor rms current ratio,
between the proposed and conventional SEPIC converters as a function of
M.

'i L 1
'i L 1C

D
DC

1 M
2M

(14)

From (14), it clear that the defined ratio value is always

less than one for any operating point of M. This is true
since the proposed topology always operates at lower dutycycle than the conventional SEPIC converter provided M is
the same.
IV. THE PROPOSED CONVERTER WITH COUPLED
INDUCTORS
In the proposed circuit of Fig. 1, the three inductors have
identical voltage waveforms; hence they can be
magnetically coupled into a single magnetic core as shown
in Fig. 5. Note that Fig. 5 shows that the input inductor L1
and the output inductor L3 are both coupled to L2, but that
L1 and L3 are not directly coupled. Moreover, by proper
selection of the coupling coefficients k12 and k23, near zero
current ripples in input and output inductors can be
obtained. This is an attractive feature since zero ripple input
current tends to minimize both the system noise level and
EMI at the input port of the converter. Whereas zero ripple
output input current tends to eliminate or reduce the size of
the output filter capacitor. In reality, the ripple current is
not exactly reduced to zero but is highly reduced. The
reason for this is that the voltages across the inductors are
not exactly identical because of the ripple voltage across
the capacitors.
Referring to Fig. 5, the rate of change of the inductor
currents iL1, iL2, and iL3 during switch on-time is given by,
i L1
d
iL2
dt
i L 3

L 2 L3  M 232
1
M 12 L3
'

M 12 M 23

M 12  M 23  L3 
L1  L3  M 23 
L1 (L 2  M 23 )  M 12

M 12 M 23 V g

M 12 L3 V C 1
2
L1L 2  M 12 2V C V o

(15)

where
'

L1 L 2 L3  L1 M 232  L3 M 122 ! 0

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(16)

and

M 12

k 12

L1 L 2 , M 23

k 23

(18)

The circuit of Fig. 5 can supply free ripple current in the

input and output inductor not only in CCM but in DCM as
well where the high switching ripple are of concern. This is
a very desirable feature for power factor correction (PFC)
applications since it will minimize the EMI effect and the
input filtering stage [10]-[13]. On the other hand, the
proposed converter is suitable for PFC applications when
operating in DCM. In this case, the averaged input current
over one switching period is given by

(19)

i L1

(17)

L 2 L3

are the mutual inductances of the windings. At steady state,

VC1=Vg and Vo=2VC, then from (15) the following two
conditions must be satisfied for zero ripple in the input and
output inductors,
di L 1
dt

Vg

di L 3
dt

Vg

L 2 L3  M 12  M 23  L3   M 232
'
L1 L 2  M 23  M 12  L1   M 122
'

respectively. Solving (18) and (19) gives the following

result,

L2
, L 2  L1
k 12
L1
(20)

M 12 M 23 L 2

L2
, L 2  L3
k 23
L3

with
2

 k 12    k 23 

(21)

1

During switch off-time, the conditions for zero ripple in

the input and output inductor is similar to the one in (20). In
order to verify (20), the circuit of Fig. 1 and Fig. 5 have
been simulated for the following values: Vg = 20 V, Vo =
40 V, RL = 10 :, fs = 50 kHz, C1 = C = 100 PF, Co = 47 PF,
L1 = L3 = 100 PH, and L2 = 46.24 PH. It is clear from the
simulation results shown in Fig. 6 that near zero current
ripples at both input and output is achieved by coupling the
three inductors into a single magnetic structure.
iL3

iL1
M23, k23

M12, k12
iL1 L1

C1

Vg

L2

iL2

L3 iL3
Co

+
Vo RL
-

Fig. 5. Proposed converter with coupled inductors.

10A

iL1

8A
6A
4A

iL2

10A
6A

iL3

2A
0A
0
(a)

iL1

8A
4A

iL2

iL3

2A
20 40 60 80 100
Time [s]

0A
0
(b)

20 40 60 80 100

V g D 2 Ts

(22)

2 Le

where

1
1
1
1
=


Le L1 L 2 L3

(23)

Thus, if Vg is a rectified sinusoid voltage, then the

average or low frequency component of the converter input
current naturally follows the ac line voltage waveform,
provided that the switching frequency and the duty-cycle
are kept roughly constant. Note that (22) is similar to result
obtained for conventional SEPIC and Cuk converters [10],
except for the definition of Le which is defined as a parallel
combination of three inductors instead of two.
In order to demonstrate the effect of coupling the
inductors on the input line current, the circuit of Fig. 5 has
been simulated with ac line input voltage followed by a
bridge rectifier for two cases: a) with three separate
inductors (uncoupled), b) with coupled inductors. No
additional input filtering has been included in the
simulation. The simulated input line voltage and input
current waveforms for uncoupled and coupled case are
shown in Fig. 7(a) and 7(b), respectively. The percent of
the total harmonic distortion (%THD) in the input line
current is about 1.5% for the two cases. However, Fig. 7(b)
shows that the high frequency switching ripple current is
greatly reduced due to the coupling of the three inductors.
Thus, the generated EMI noise level is greatly minimized as
well as the requirement for the input filtering. Another
advantage of coupling the three inductors is a significant
reduction in the rms current through the output filter
capacitor Co. It should be mentioned here that the zero
ripple input and output current feature presented in this
section for the converter of Fig. 5 can be also obtained in
the conventional Cuk converter using coupled inductors [4].
However, the proposed converter has an advantage of wider
voltage conversion ratio, reduced switch and diode voltage
stress, better switch utilization, as well as non-inverted
output polarity.

Time [s]

V. EXPERIMENTAL RESULTS

Fig. 6. Simulated inductors current waveforms in CCM. (a) Un-coupled

inductors, Fig.1. (b) Coupled inductors, Fig. 5.

The circuit in Fig. 1 has been built in the laboratory. The

converter is designed for a nominal voltage conversion ratio
M = Vo/Vg = 48 V/24 V=2, and with fs = 75 kHz. The

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switch duty-cycle is set to 0.5 (according to (4)). Fig. 8

shows the measured input/output voltage waveforms and
the switch blocking voltage VS. It is evident from Fig. 8
that the experimental results show a good agreement with
the predicted results.
20

Volt, Ampere

20
10

vac/10
iac

(a)

[3]

0.99
Time [s]

-20
1.00 0.98
(b)

[2]

vac/10

[4]

iac

10

10
-20
0.98

10

REFERENCES
[1]

[5]
0.99
Time [s]

1.00

Fig. 7. Simulated waveforms for the converter of Fig. 4 with rectified ac

input voltage source: a) Un-coupled inductors. b) Coupled inductors.
Simulation parameters: vac = 100 Vrms, Vo = 220 Vdc, RL = 150 :, fs = 50
kHz, C1 = 4 PF, C = 20 PF, Co = 2 mF, L1 = L3 = 150 PH, and L2 = 54 PH.

[6]
[7]

[8]
[9]
[10]

[11]

[12]
Fig. 8. Measured waveforms for the converter of Fig. 1 in CCM.

VI. CONCLUSION

[13]

New technological advances are requiring converter with

wider conversion ratios. This paper presented a new simple
high performance SEPIC derived converter with wide
voltage conversion ratio, continuous output current and
reduced voltage stress on all the semiconductors. The input
and output current ripple can be greatly reduced to near
zero level due to the utilization of a coupled inductor
techniques. The proposed converter has few extra
components in comparison to a standard SEPIC and it is
regulated by the conventional PWM technique at constant
frequency. However, the additional components is far
outweighed by the remarkable advantages gained, thus
expecting the popularity of this technique to other exiting
topologies. The performance of the converter is verified by
means of simulation and experimental tests. The
experimental substantiate the analyses carried out
throughout the paper.

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