2012 5th International Conference on BioMedical Engineering and Informatics (BMEI 2012)

Phase-Locked Loop of Inverter Based on FPGA

Shuhong Li, Yueqing Zhou
School of Electrical Engineering and Automation, Tianjin University
Tianjin, China

AbstractAn induction heating system with a full bridge LLC

a kind of load formresonant inverter is described in this
paper. Subsequently, the output voltage of inverter and
capacitance voltage are chosen as control variables of phaselocked loop (PLL). With regard to LLC resonant inverter, there
is a phase error of 90 degrees between the two control variables.
First of all, a kind of PLL with XOR Phase Detector (XORPD) is
proposed. This PLL is realized by embedded function module
74HCT297 of FPGA. Then a novel PLL with Phase-Frequency
Detector (PFD) is designed. Compared with the latter, the former
can be more completely implemented by FPGA. However, the
latter is able to adapt to more complex input signals, which is
good for high frequency and high efficiency of induction heating
system.

pair of control variables is chosen to design PLL of LLC

resonant inverter. Then a popular all digital phase-locked loop
(ADPLL) based on FPGA is proposed in Section IV. At last, a
novel PLL based on FPGA is designed in Section V.
II.

FULL-BRIDGE INVERTER

A full bridge inverter with LLC resonant load is proposed

in this section. The designed inverter configuration is shown in
Fig. 1. The inverter configuration is an induction heating
system. Field effect transistor MOSFET with an antiparallel
diode serves as a bridge arm of the full bridge inverter. The
part in dash-dotted frame is LLC resonant load.

io

Keywords-LLC resonant inverter; phase-locked loop (PLL);

XOR Phase Detector (XORPD); Phase-Frequency Detector (PFD);
FPGA

I.

is

Ls

UD

uC

INTRODUCTION

Generally, an inverter is the most important constituent part

of an induction heating system. So the design of inverter is
crucial for performance of induction heating system. The
design of inverter contains two kinds of circuits. They are main
circuit and control circuit, respectively. Control circuit consists
of phase-locked loop (PLL), overcurrent protective circuit and
PWM generating circuit. PLL is used to make the inverter
achieve frequency tracking. The output signal of PLL serves as
the input signal of PWM generating circuit. And the output
signal of PWM generating circuit is used to drive switching
devices in the inverter. In addition, overcurrent protective
circuit prevents the electron device from suffering burnout.
Because the resonant frequency of load is varied in the
process of heating, PLL acts as a very useful control circuit of
induction heating system. For induction heating system,
frequency tracking can bring about two benefits. One of the
benefits is that the biggest inverter output power would be
obtained. The other is that zero voltage switch can be realized.
So PLL plays an important role for an induction heating
system. PLL technique has been studied for a long time, but
there is limited research on PLL of LLC resonant inverter. And
the rest paper is focused on designing PLL for LLC resonant
inverter based on FPGA.

Figure 1. Full-bridge LLC resonant inverter.

In Fig. 1, U D represents DC voltage source. Current io

flows through load resistance R. is stands for the output
current of the inverter. At the same time uo is the output
voltage of the inverter, and uC is the capacitance voltage. At
high frequency, field effect transistor MOSFET generally
produces parasitic capacitance. However, when designing the
control circuit, we usually pay attention to working states of
inverter circuit at low frequency and intermediate frequency[1].
So the influence of parasitic capacitance produced by
MOSFET is neglected in this study.

When being heated, the resonant frequency 0 of LLC load

is varied. And the focus of this study is on designing PLL for
the LLC resonant inverter to achieve frequency tracking. In
order to design PLL for the LLC resonant load, control
variables have to be chosen in advance.
III.

CHOOSING CONTROL VARIABLES FOR PHASE-LOCKED

LOOP
For LLC resonant load, quality factor Q is expressed as (1)

Section II describes a LLC resonant inverter. In Section III,

the characteristic of LLC resonant load is talked about, and a

978-1-4673-1184-7/12/$31.00 2012 IEEE

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Q=

1
R

L Ls
( L + Ls ) C

Z ( ) presents the impedance of LLC resonant load. So the

expression of Z ( ) is obtained:

Z ( ) = j Ls +

u (0 ) = arg(

1
jC + 1 ( j L + R )

(2)

acts as a monotonic function. Obviously, both uo and uC could

be chosen as control variables of PLL.
Hv( )
Magnitude (dB)

(3)

Phase (deg)

The characteristic curve of Z ( ) is illustrated in the Fig. 2.

Magnitude (dB)
Phase (deg)

20

-60
0
-45
-90

-135
6

10

(rad/s) 10

With regard to a voltage-fed inverter, inverter output

voltage uo and gate drive signal have identical phases and
frequencies[2]. At the same time, the phase and frequency of
switch drive signal are decided by output signal of PLL.
Thereby, the output signal of PLL takes the place of uo for
phase detection. So the output signal of PLL is chosen as
feedback signal of phase detector. And capacitor voltage uC is
chosen as the reference signal of phase detector.

0
90
45

Frequency (rad/sec)

10

Figure 2. The impedance characteristic curve of LLC resonant load.

For LC series resonant inverter the output voltage and

current of the inverter are usually used as control variables of
PLL. Nevertheless, the phase-frequency curve of LLC resonant
load shows that the phase angle of Z ( ) is not a monotonic
function when it changes with frequency . Consequently, for
LLC resonant inverter, the output voltage and current of the
inverter cannot be used as control variables.
The relation between the output voltage of the inverter
uo and capacitor voltage uC is illustrated by the following

IV.

u
Z ( ) j Ls
H u ( ) = C =
uo
Z ( )

uref

(4)

u fd

When LLC load working at the series resonance frequency

as (5) and (6), respectively.

(5)

jQ( + 1)
1
Q( + 1)
(6)
)= arg( j
)
2

2
A variable is assumed as = Ls L . If 1 , (6) can be

u (0 ) = arg(

approximated to ( 2 ) . Equation (7) demonstrates the

derivation:

ud

Figure 4. Module diagram of XOR Phase Detector.

o , (4) and its phase-frequency characteristic can be expressed

Z (0 ) j0 Ls jQ ( + 1)
=
Z (0 )
2

PHASE-LOCKED LOOP WHITH XOR PHASE DETECTOR

Because uo and uC serve as the control variables of PLL,

when working in locked state, the phase of feedback signal
outstrips that of reference signal by 90 degrees. For this reason,
XOR Phase Detector (XORPD) fits this pair of control
variables. In order to verify the conclusion, an introduction to
XORPD is given. The structure of XORPD is illustrated by the
module diagram in Fig. 4. The only output of XORPD is ud .

expression:

H u (0 ) =

-40

Figure 3. The characteristic curve of H u ( ) .

40

0
-20

-180
5
10

z( )

-45

(7)

To verify (7), the characteristic curve of H u ( ) is

illustrated in the Fig. 3. In the frequency domain where
induction heating power supply generally works, the phasefrequency curve shows that u ( ) = arg tan ( uC ( ) uo ( ) )

And the series resonant angular frequency o of LLC

resonant load is also obtained through (2).

L + Ls
L Ls C

1
Q( + 1)
Q( + 1)

j
) arg( j
)=
2
2

There are two kinds of conditions in which the averaged ud

is equal to zero.
1) the phase of reference signal outstrips that of feedback
signal by 90 degrees.
2) the phase of feedback signal outstrips that of reference
signal by 90 degrees.
The above property of XORPD makes itself fit the control
variables which are inverter output voltage uo and capacitor
voltage uC . Thus, embedded function module 74HCT297 of
FPGA could be chosen as PLL in this study. And the basic

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structure of this PLL is shown in Fig. 5. In Fig. 5, K counter

serves as low-pass filter. Increment-decrement (ID) counter
acts as voltage control oscillator. Whats more, fractional-N
counter is necessary for this ADPLL. Hence, before the output
signal of ID counter reaches XORPD, its frequency has already
been divided by N.

Mf0

V.

PHASE-LOCKED LOOP WITH PHASE-FREQUENCY

DETECTOR

The above designed ADPLL has been popular and could be

realized completely by FPGA. However, this section will
propose a novel PLL for LLC resonant inverter. When the
control variables of LLC resonant inverter are chosen as
inverter output voltage uo and capacitor voltage uC , another
strategy of PLL can be adopted. In this strategy, PhaseFrequency Detector (PFD) substitutes for XORPD.
UB

"1"

XOROUT

CP FF

u1

uC

Q UP

2Nf 0

CD

Ud

IDOUT
CD

u2

CP FF
"1"

Figure 5. The basic structure of PLL with XORPD.

16

DN

Figure 7. Module diagram of Phase-Frequency Detector.

With regard to this ADPLL, only three parameters need to

be determined. These parameters are K, M and N, which have
to be 2 of integer power respectively. For 74HCT297, the
minimum K is 8. Generally, M is equal to 2N. According to
Ripple Minimum Principle, if K is equal to M 4 , the smallest
ripple wave is obtained[3]. As for this PLL, M is set to 32, N is
set to 16, and K is set to 8. In this condition, the system wave is
obtained in Fig. 6.
( Mf0 )

32

u1

u 2i ( IDout 16 )

First of all, an introduction to PFD is given. Fig. 7 is the

module diagram of PFD. As for this phase detector, there exist
only three states whose identifiers are -1, 0 and 1 respectively.
Identifier -1 represents the condition that UP is equal to 0 and
DN is equal to 1. Identifier 0 represents the condition that both
UP and DN are zero. Identifier 1 represents the condition that
Up is equal to 1 and DN is equal to 0. 1 stands for the phase
of reference signal, and 2 represents the phase of feedback
signal. Only the rising edges of the 1 and 2 can change the
state of PFD[4]. Fig. 8 illustrates its operation.

DN UP

K 2

K 2

Figure 8. States of the Phase-Frequency Detector (PFD).

( 2Nf0 )
16

IDout

32

Assume that and K d are the phase error between two

input signals and the time averaged output of PFD,
respectively. When PFD operates in the region of
( 2 , 2 ) , the relation between K d and is shown in
Fig. 9.

IDout 2

Kd

IDout 4
IDout 8

Kd

2
2

Figure 6. System wave of PLL with XORPD.

K d

Figure 9. The relation between K d and .

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Fig. 9 shows that the phase error range of PFD is 2 . But

the phase error range of XORPD is ( 2 ) . Compared with
the PLL with XORPD, the PLL with PFD can adapt to more
complex signal environments which have different frequencies
and phases. When belongs to ( 2 , 2 ) , K d acts as a
linear function of :
u d = K d
(8)
where K d stands for the gain of PFD. Equation (8)
demonstrates that only when both frequency synchronization
and phase synchronization are realized, ud is equal to zero.
And in locked state, the phase of feedback signal is caused to
be equal to that of reference signal by PFD.

uC

"1"

D1

inc

CP FF

CD

PFD

"1"
u2

f
2

CD

CP FF
Q

DN

dec

2Nf 0

Mf 0

Consequently, if inverter output voltage uo and capacitor

voltage uC are used as control variables of PLL with PFD, a
delay circuit of 90 degrees is necessary. A 90 degrees delay
circuit[5] is shown in Fig. 10. The theory waveform diagram of
delay circuit is shown in Fig. 11.
CP1

Q UP

D1

Q1

Q1

D2 Q2
Q2

Q1

Figure 12. The basic structure of PLL with PFD.

Q1
D2 Q2
CP2

VI.

Q2

Figure 10. 90 degrees delay circuit.

CP1
t
Q1

CP2
t

Q2
t

Figure 11. Waveform of 90 degrees delay circuit.

Fig. 12 illustrates the basic structure of this PLL which

consisits of PFD, delay circuit of 90 degrees, K counter, ID
counter, fractional-N counter and 1/2 frequency divider. For
this PLL, both K counter and ID counter will be realized by
FPGA. And 2N should be set to M 2 . The output of 1/2
frequency divider is used to drive signal Q1 and switching
devices of inverter. The output of fractional-N counter is used
as the clock signal CP1 and CP2 . According to the principle of
PLL, signal Q1 and inverter output voltage uo have identical
phases and frequencies. Fig. 11 demonstrates that the frequency
of signal Q2 is the same with that of signal Q1. But compared
with Q1, the phase of Q2 is delayed for 90 degrees. So when
PLL operating in locked state, Q2 and uC have identical phases
and frequencies. Thus, Q2 is used as feedback signal of PDF.

CONCLUSION

This paper has proposed two kinds of PLLs for LLC

resonant inverter when control variables are chosen as inverter
output voltage and capacitor voltage. The two kinds of PLLs
are PLL with XORPD and PLL with PFD, respectively.
Compared with the latter, the PLL with XORPD is more
popularly used, and there are more perfect theory to analysis its
operating principle. Above all, embedded function module
74HCT297 of FPGA makes the former easier to realize
frequency tracking than the latter. However, the latter has its
own advantages. The PLL with PFD has enhanced the ability to
adapt to different phase or frequency errors between two input
signals, which is significant to make induction heating power
supply realize high frequency and high efficiency.
Consequently, an in-depth study of the latter should be
undertaken in the area of induction heating system.
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[1]
[2]

[3]
[4]
[5]

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Sun Jinqiu, Research on the controller of induction heating power

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Resonant Inverter for Induction-Heating Applications With
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58, pp. 29152925, July 2011.
Roland E. Best, Phase-Locked Loops: Design, Simulation, and
Applications (5th Edition), Tsinghua University Press, 2007.
Dean Banerjee, PLL Performance, Simulation, and Design (4th Edition),
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