ALGORITHMIC STATE MACHINE (ASM)

The binary information stored in a digital system can be classified as either data or
control information. Data are discrete elements of information that are manipulated to
perform arithmetic, logic, shift, and other similar data processing tasks. These operations are
implemented with digital components such as adders, decoders, multiplexers, counter, and
shift registers. Control information provides command signals that supervise the various
operations in the data section in order to accomplish the desired data-processing tasks. The
logic design of a digital system can be divided into two distinct parts. One part is concerned
with the design of the digital circuits that perform the data-processing operations. The other
part is concerned with the design of the control circuit that supervises the operations and their
sequence.
The relationship between the control logic and the data processor in a digital system is
shown in the figure below.
Status conditions

External
Inputs

Control Logic

Commands
Input
Data

Data processor

Output
Data

The control sequence and data-processing tasks of a digital system are specified by a
mean of a hardware algorithm, a finite number of procedural steps that specify how to obtain
a solution to a problem. The most challenging and creative part of a digital design is the
formulation of hardware algorithms for achieving required objectives.
A flowchart is a convenient way to specify the sequence of procedural steps and
decision paths for an algorithm. A special flowchart that has been developed specially to
define digital hardware algorithms is called Algorithmic state machine (ASM) chart.
The chart is composed of three basic elements: the state box, the decision box, and the
conditional box. A state in the control sequence is indicated by state box. The shape of the
state box is rectangle within which are written register operations or output signal names that
the control generates while being in this state. The state is given a symbolic name, which
placed at the upper left corner of the box. The binary code assigned to the state is placed at
the upper right corner. Inside box is written register operations or output signals.
Binary code
Name
Register operations or
output signals

General description
Dr Oday A.L.A Ridha

001

T1

START

Example
76

The decision box describes the effect of an input on the control subsystem. It has a
diamond-shape box with two or more exit paths, as shown below.

Condition

0
Exit path

Exit path

The input condition to be tested is written inside the box. One exit path is taken if the
condition is true and another when the condition is false.
The third element of ASM chart is the conditional box. It has an oval shape. The
rounded corner is to differentiate it from state box. The input path of conditional box must
come from one of the exit paths of the decision box. The register operations or outputs listed
inside the conditional box are generated during a given state provided that the input condition
is satisfied.

Register operations or
output signals

ASM block is a structure consisting of one state box and all the decision and
conditional boxes connecting to its exit path. An ASM block has one entrance and any
number of exit paths represented by the structure of the decision boxes. An ASM chart
consists of one or more of interconnected blocks. Each ASM block describes the state of
logic circuit during one clock pulse interval.
ASM block
T1

0
0

T2

Dr Oday A.L.A Ridha

010

001
A+1
1

T3

011

T4

One clock
cycle

Present state Next state

T2, T3, or
T1
T4

100

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Some ASM figures

T1

001
A+1
1

E
0

T2

T1

001
A+1
1

010

T2

Invalid feedback

T1

010

Valid feedback

T1

001
A+1

1
0
R

I1

1 I
2

001
A+1
0

I2

0
K

K
1
0

Parallel interconnection

I1

Serial interconnection

Some of register operations

Symbolic notation

Dr Oday A.L.A Ridha

Description

AB

Transfer the content of reg. B to A

R0

Clear reg. R

AA+1

Increment the content of reg. A by one

AA-1

Decrement the content of reg. A by one

AA+B

Add reg. A and B then store the result in A

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 The ASM chart is very similar to a state diagram. Each state block is equivalent to a
state in sequential circuit. The decision box is equivalent to the binary information
written along the directed lines that connect two states in a state diagram. As
consequence, it is sometimes convenient to convert the chart to a state diagram and
then use sequential circuit procedures to design the control logic.

T1

001
A+1
001

0
0

EF=00

E=1
EF=01

010

T2

010

T3

011

T4

100

100
011

The ASM chart gives all the information necessary to design digital system. The
requirements for the design of data-processor subsystem are specified inside the state
and conditional boxes. The control logic (circuit) is determined from decision boxes
and required state transitions.
The control section of a digital system is essentially a sequential circuit that can be
designed by the procedure used for previous lectures. However, in most cases this
method is impractical because of the large number of state and inputs that a typical
control circuit may have, except for small controllers. There are special methods for
control logic design. These methods may be considered as an extension of the
sequential method. One of these methods is design with multiplexers.

Dr Oday A.L.A Ridha

79

Example: design a digital system with two flip-flops (E and F) and one 4-bit binary counter
(A). A start signal (S) initiates the system by clearing the counter (A) and the flip-flop (F).
The counter is then incremented by one starting from the next clock pulse, and continues
Counter bits A3 and A4 determine the sequence of

counting until the operations stop.

operations as follows:

If A3=0, E is cleared to 0 and the counting continues.

If A3=1, E is set to 1; then if A4=0, the counting continues. But if A4=1, F is set to 1 on
the next clock pulse and the system stops counting.

Control
Circuit

T0
T1
Tn

Combinational
circuit

CLK

Dr Oday A.L.A Ridha

A4 A3

A2

4-bit
Counter

A1

Clear
Count

80

Solution:
P.S
symbol
T0
T0
T1
T1
T1
T2

P.S.
Code
G1G2
00
00
01
01
01
11

I/Ps
S
0
1
X
X
X
X

A3
X
X
0
1
1
X

A4
X
X
X
0
1
X

N.S.
Code
G1G2
00
01
01
01
11
00

O/Ps
T0
1
1
0
0
0
0

T1
0
0
1
1
1
0

T2
0
0
0
0
0
1

00

T0

S
1
A0, F0

State table for control

T1

By using G1 & G2 (JK-type F.F) for representing

states and using k-map for simplification, we
obtain the following logic equations for the control
circuit:

01
AA+1

A3

1
E1

E0

J1=QG2A3A4 , K1=1,
J2=S, K2=QG1,
T0=QG2, T1=QG1.QG2, T2=QG1.

1 A
4
11

T2

F1

Combinational circuit equations

Control circuit

Clear=S.T0, Count=T1,
JE=T1.A3, KE=T1.A3,
JF=T2, KF=S.T0.

J
K

G2

Q
Q

T0
T1

A4
A3

CLK

G1

T2

For more examples see Morris Mano page 305.

Dr Oday A.L.A Ridha

81

Design with multiplexers

One major goal of control-logic design is the development of a circuit that implements
the desired control sequence in a logical and straightforward manner. The attempt to
minimize the number of gates tends to produce an irregular network making it difficult for
anyone but designer to identify the sequence of events the control undergoes. As
consequence, it is difficult to alter, service, or maintain the equipment after initial design. The
sequence of states in the control should be clearly evident from the circuit configuration even
if this requires additional components and results in a nonminimal circuit. The multiplexer
method is such an implementation.
The control circuit consists of three levels: the first level consists of multiplexers that
determine the next state. Second level contains a register that holds the present binary state.
The third level has a decoder that provides separate output for each control state.
For example we redraw the control logic circuit using multiplexer method.
P.S.
N.S.
G1 G2 G1 G2
0 0 0 0
0 0 0 1
0 1 0 1
0 1 0 1
0 1 1 1
1 1 0 0
0

A3
A4

0
1 MUX
2
3
S0 S1

Input
conditions
S
S
A3
A3.A4
A3.A4

Multiplexer inputs
MUX1
MUX2
0

A3.A4

F.F.

G1
T0
Decoder

S
1
0

S0 S1
0
1 MUX
2
3

G2

T1

T2

F.F.
Control circuit

CLK
Dr Oday A.L.A Ridha

82

Exercises

1. A digital system consists of two registers (R1 and R2) and a flip-flop E (as shown in the
figure below). Draw the ASM chart of the control circuit that makes the digital system count
the number of 1s in the number loaded into register R1 and store the result in R2.
Input data
SI=0
Shift right
Load R1

Inputs= All 1s

Load E

Shift register R1

Count
Load R2

Counter R2
Output count

Z=1 if R1=0

Data processor subsystem of 1s counter

Solution
T0

00
0

S
1
R1input,
R2All 1s

01

T1

R2R2+1

1
T2

Z
0

10

P.S.
G1 G2
0
0
0
0

N.S.
Input
Multiplexer inputs
G1 G2 conditions MUX1
MUX2
0
0
S
0
S
0
1
S

1
1

1
1

1
0

0
1

0
Z
1
E

Shift R1 to E

0
1 MUX
2
3 S S
0
1

none

E
E

F.F.

G1
T0

11

T3

Decoder

T1
T2

S
0
1
E

S0 S1
0
1 MUX
2
3

G2

T3

F.F.
Control circuit

CLK

Count=R2R2+1=T1, Load R2=S.T0

Shift R1=load E=T2, Load R1=S.T0

Dr Oday A.L.A Ridha

83

2. Design a logic circuit that multiplies two numbers

Z
Register B

Load B

Cout

B - Multiplicand
Q - Multiplier
P - down counter,
initially hold the
length of Q (n)

Z=1 if P=0
Count
Load P

Parallel Adder

Counter P
Q1

Load E
Clear E

Register A

E
Clear A
Load A
Shift right

Register Q
Load Q
Shift right

Data processor subsystem of multiplier

Solution
P.S.
G1 G2

00

T0

S
T1 1

0
01

A0
E0
Pn

T2

none

none

10
PP-1

Q1
0

0
1
1
Z

F.F.

G1
T0
T1

Decoder

T2

Shift right AQ

0
1 MUX
2
3 S S
0
1

AA+B, ECout

11

T3
1

N.S.
Input
Multiplexer inputs
conditions
G1 G2
MUX1 MUX2

S
0
1
0

S0 S1
0
1 MUX
2
3

G2

T3

F.F.
Control circuit

CLK

Clear E=Clear A=Load P=T1, Count=PP-1=T2, Load A=Load E=T2.Q1

Shift A=Shift Q=T3

Dr Oday A.L.A Ridha

84

3. Design a circuit that controls the process of mixing and heating two liquids (A and B).
The ratio between A and B in produced liquid must be and at temperature of 100 C.
Design the control circuit in such away that the production is maximum.

M5

Size= 1 volume

M1

Full A

Sensor
Motor

M2

Empty
A

Size= 2 volume

Pump

M3

Full B

100 C

M4

M6

Empty C

Empty B

Heater
Start

Control and Driving circuit

Stop

Dr Oday A.L.A Ridha

85

000

T0

T1

Start

001

100 C

Heater

Full A

T4

Full B 1

Full B

M5

1 Stop

M3

T2

010
M5

0
Empty
C

M6

1 Stop

100

M3

100 C

0
M3

Empty
A

T1
Full A

M1

Heater
0

M1

M5

1 Stop

1 Stop
0

011

T3

Full B

Full B

0
M3

M2

Empty
B

Empty
B

0
M4

M4

T3

Dr Oday A.L.A Ridha

86

Calling Machine A

Calling Machine B

Idle state

Some states
ZA
ZA

ZB

Some states

ZB
Other states

Dr Oday A.L.A Ridha

87