Pragyan

Baidya
Lab Report Waveform generators (VCO)
Objective
The main objective of the experiment is to learn about the basic mechanism and
operations of electronic waveform generation. This lab deals with utilizing the
standard IC chips to produce various electronic waveforms. In this lab the standard
IC chips also be utilized to design a frequency modulation circuit to produce various
desired waveforms.
Procedure:
The first part of the lab deals with Oscillation. In part 1 a circuit that produce 900 Hz
symmetrical square using a triangle generator should be designed and built as
shown in the schematic in figure 1 below. The circuit consists of a resistor RB = 10
k and a Vcc of 24 V DC. The capacitors must be combined in either parallel or
series in order to achieve a desired value for the Capacitance to be sued in the
circuit. The desired value for the Capacitor and the Resistor (RA) is computed using
the equations 1 and 2 given below. The RA of the pot must be adjusted to produce
50% duty-cycle which can be measured using the time display on the scope. After
setting the circuit to produce to 50% duty cycle the output frequency of the circuit
must be measured and computed. The output waveforms along with peak to peak
frequency (Vpp), frequency and the duty cycle of the waveform must be captured.
The frequency measurements must be computed with the theoretical or the
designed frequency of the circuit.
The pot resistance (RA) value must be adjusted to produce a resistance of 25%. The
resistance value of the pot must be measured and recorded. The square wave
output should be captured with variables such as frequency, Vpp value and duty
cycle. The same produce should be repeated to gather necessary data for 66% and
75% duty-cycle. The values collected must be tabulated and a graph to show the
impact of resistance on the duty cycle must be plotted. The RA value must be reset
to produce 50% duty-cycle and then capacitors in the circuit must be replaced by
capacitance box provided. The capacitance value must be varied with the intervals
of 10 starting from 0.1 nF and a total of 5 readings must be collected.

Figure 1: The schematic of the basic Oscillator circuit

Equation 1: Equation that demonstrates the relationship between period, Resistance and Capacitance
of the circuit.

Equation 2: Equation to compute the period and the resistance for symmetric output
signal .

To = 3 RA CT or, fo = 1 / To = 1/3 RT CT
Part 2 of the lab deals with DC Sweep input. The circuit shown in figure 2 below
must be built with the RA = 10 k and the capacitor value from part 1. In this circuit
a second DC voltage must be supplied between pins 8 and +Vcc. The input Voltage
VDC through +Vcc must be varied starting from 0 V in intervals of 1 volt step until
the output signal shuts down. The sweep voltage and the frequency must be
measured and recorded. The results gathered must be plotted and the modulation
rate, k must be computed.

Figure 2 The schematic for the DC Sweep circuit.

Part 3 of the lab deals with AC modulation of the circuit. The circuit shown in figure
3 must be designed and built with R C value of 10 k and CC = 10 F. The HP

function generator must be used to apply a sine wave of 100 HZ to the AC

input to the ground. The input should then be adjusted to produce a 500 m
Vpp which is measured at pin 8. The amplitude of the input must be
increased as the frequency is lowered since the capacitor value drops at
lower frequencies. The frequency change from the change in the period of
the output (f = 1/T) must be measured and recorded using the output
wave generated on the scope. The same procedure must be repeated for 2.0
Vpp and 4.0 Vpp inputs and the frequency change like the previous part
must also be computed. The input frequency should then be reduced to 1.0
Hz and the input must be set to 0.5 Vpp. After setting the values the
frequency change must be measured from the output waveform. With the
input frequency set to 1.0 Hz the same procedure must be followed to
measure the frequency change for 2.0 Vpp input and 4.0 Vpp inputs.

Figure 3: The Schematic for the frequency Modulation circuit

Conclusion:
For the first part of experiment the impact of the pot resistance on the % duty cycle
was tested. The data collected are displayed in Table 1 of the results section. It was
observed that increasing the pot resistance value for RA also increases the % duty
cycle of the output. The graph of RA Vs %Duty cycle in figure 1 demonstrates a
exponential relation between pot resistance and the % Duty cycle. It was observed
that increasing the value of pot resistance causes a decrease in frequency for most
of the data collected. From figures 2-5 it can be observed that spacing between the
two peaks decreases as the %duty cycle in increased. For example in Figure 2 for
50% duty cycle the graph is perfectly distributed with rise and the fall having equal
distribution between them however, it can be seen from other graphs that
increasing the % duty cycle causes this distribution to change and the spacing
between the peaks decreases. In the second part of the experiment the impact of
the capacitance was tested on the circuit by varying the capacitance and keeping
the resistance constant. From the data displayed in Table 2 it can be seen that the
increasing the capacitance decreases the frequency of the output waveform. On the
other hand it can be also observed that increasing the capacitance of the circuit
also increases the % duty cycle. From the graph of Capacitance vs. Frequency
shown in figure 6 it can be observed that capacitance and the Frequency have an
decreasing linear relationship with slope equal to 0.05.
The prelab value comparison