ARM

(Advanced RISC Machines )

SUSHMA RAWAL

Introduction

ARM core uses a RISC Architecture

SUSHMA RAWAL

RISC Architecture
Simple but powerful instructions that execute
within a single cycle at a high clock speed.
Reduced complexity of instruction performed by
hardware.
Provides greater flexibility and intelligence in
software, therefore places greater demand on the
compiler.

SUSHMA RAWAL

ARM design philosophy

High code density (The amount of space that an
executable program takes up in memory )
Reduced area of ARM core-required for
embedded systems.
Incorporates hardware debug technology within
processor.

SUSHMA RAWAL

ARM design philosophy

The Thumb instruction set features a subset of the
most commonly used 32-bit ARM instructions
which have been compressed into 16-bit wide
operation codes. On execution, these 16-bit
instructions are decoded to enable the same
functions as their full 32-bit ARM instruction
equivalents.
provides enhanced code density.

SUSHMA RAWAL

ARM PROCESSOR
It incorporates these typical RISC architecture
features:
Large uniform register file
Load/store architecture, where data-processing
operations only operate on register contents, not
directly on memory contents
Simple addressing modes, with all load/store
addresses being determined from register contents
and instruction fields only.

SUSHMA RAWAL

ARM PROCESSOR

In addition, the ARM architecture provides:

Instructions that combine a shift with an
arithmetic or logical operation
Auto-increment and auto-decrement addressing
modes to optimize program loops
Load and Store Multiple instructions to maximize
data throughput
Conditional execution of almost all instructions to
maximize execution throughput.
SUSHMA RAWAL

ARM PROCESSOR
These enhancements to a basic RISC architecture
enable ARM processors to achieve a good balance
of high performance, small code size, low power
consumption, and small silicon area.
ARM processor is small to reduce power
consumption and extend battery operation. Eg
mobile phones and PDAs.

SUSHMA RAWAL

ARM PROCESSOR
ARM core is a 32-bit processor.
ARM processor uses load-store architecture.
There are no data processing instructions that
directly manipulate data in memory.
Data processing is carried out solely in registers.
Register file is made up of 32-bit registers.

SUSHMA RAWAL

REGISTERS
General purpose registers hold either data or
address
All registers are 32-bit in size.
16 data registers ( R0 to R15) and 2 PSR
ARM processor has assigned special functions to
3 registers.
R13- Stack Pointer (SP)
R14- Link Register (LR)
R15- Program Counter (PC)
SUSHMA RAWAL

Registers
Stack Pointer- stores the head of the stack
in the current processor mode
Link register- core puts the return address
when it calls a subroutine
Program counter- contains the address of
the next instruction to be fetched by the
processor.
SUSHMA RAWAL

Registers
In ARM state the registers R0 R13 are
orthogonal.
Any instruction that you can apply to R0
can equally well apply to other registers.

SUSHMA RAWAL

Program Status Register

CPSR-Current Program Status Register
- 32-bit register
- contains the present status of an internal
operation
SPSR-Saved Program Status Register
- 32-bit register
- contains the status of an internal operation
in the previous mode
SUSHMA RAWAL

CPSR
ARM uses CPSR to monitor and control
internal operations.
CPSR is a dedicated 32-bit register and
resides in the register file.

SUSHMA RAWAL

Generic program Status Register

Flags

Status

Extensions

Control

31 30 29 28

F T

Interrupt
Masks

Condition flags

SUSHMA RAWAL

0
Mode

Processor
mode

Generic program Status Register

Modes
Abort

10111

Fast interrupt request

10001

Interrupt request

10010

Supervisor

10011

System

11111

Undefined

11011

User

10000
SUSHMA RAWAL

Processor Modes
Processor Modes determine - which
registers are active and have access rights to
the CPSR.
Priviledged mode
- allows full read write access to CPSR
Non Priviledged mode
- read access to control field of CRSP
- read-write access to conditional flags
SUSHMA RAWAL

Processor Modes
Priviledged Modes
Abort
Fast interrupt request
Interrupt request
Supervisor
System
Undefined
Nonpriviledged mode
User
SUSHMA RAWAL

Processor Modes
The ARM has seven operating modes:
User (unprivileged mode under which most user tasks
run)
FIQ (entered when a high priority (fast) interrupt is
raised)
IRQ (entered when a low priority (normal) interrupt is
raised)
Supervisor (entered on reset or when a Software
Interrupt instruction is executed). OS kernel executes.
Abort (used to handle memory access violations)
Undefined (used to handle undefined instructions)
System (privileged mode using the same registers as
user mode). OS routines can be configured to run in this
mode.
SUSHMA RAWAL

Banked Registers
ARM has 37 registers in total, all of which
are 32-bits long.

1 dedicated program counter

1 dedicated current program status register
5 dedicated saved program status registers
30 general purpose registers

SUSHMA RAWAL

Banked Registers
20 registers are hidden from a program at
different times.
These registers are called banked registers
They are available only when the processor
is in a particular mode.

SUSHMA RAWAL

Banked Registers
Banked registers are arranged into several banks,
with the accessible bank being governed by the
processor mode. Each mode can access
a particular set of r0-r12 registers
a particular r13 (the stack pointer) and r14 (link
register)
r15 (the program counter)
cpsr (the current program status register)

and privileged modes can also access

a particular spsr (saved program status register)

SUSHMA RAWAL

Register Organisation
General registers and Program Counter
User32 / System

FIQ32

Supervisor32

Abort32

IRQ32

Undefined32

r0

r0

r0

r0

r0

r0

r1

r1

r1

r1

r1

r1

r2

r2

r2

r2

r2

r2

r3

r3

r3

r3

r3

r3

r4

r4

r4

r4

r4

r4

r5

r5

r5

r5

r5

r5

r6

r6

r6

r6

r6

r6

r7

r7

r7

r7

r7

r7

r8

r8_fiq

r8

r8

r8

r8

r9

r9_fiq

r9

r9

r9

r9

r10

r10_fiq

r10

r10

r10

r10

r11

r11_fiq

r11

r11

r11

r11

r12

r12_fiq

r12

r12

r12

r12

r13 (sp)

r13_fiq

r13_svc

r13_abt

r13_irq

r13_undef

r14 (lr)

r14_fiq

r14_svc

r14_abt

r14_irq

r14_undef

r15 (pc)

r15 (pc)

r15 (pc)

r15 (pc)

r15 (pc)

r15 (pc)

cpsr

cpsr

Program Status Registers

cpsr

cpsr
sprsr_fiq
spsr_fiq

cpsr
SUSHMA RAWAL

cpsr

spsr_svc

spsr_abt

sprsr_fiq
spsr_irq

spsr_undef
sprsr_fiq

Banked registers
Every mode except the user mode, can change
mode by writing directly to the mode bits of the
cpsr.
All processor modes except system mode have a
set of associated banked registers that are a subset
of the main 16 registers.
A banked register maps one-on-one onto a user
mode register.
With change of mode, a banked register from the
new mode will replace an existing register.
SUSHMA RAWAL

Register Example: User to FIQ Mode

SUSHMA RAWAL

State and instruction sets

The state of the core determines which
instruction set is being executed.
Three instruction sets
ARM-Arm state
Thumb-Thumb state
Jazelle- Jazelle state

SUSHMA RAWAL

ARM and Thumb instruction set features

ARM (cpsr T=0) Thumb (cpsr T =1)

Instruction size

32-bit

16-bit

Core instructions

58

30

Conditional
execution
Data processing
instructions

Most

Only branch
instructions
Separate barrel
shifter and ALU
instructions

Access to barrel
shifter and ALU

SUSHMA RAWAL

ARM and Thumb instruction set features

ARM (cpsr T=0) Thumb (cpsr T =1)
Program status
register

Read-write in
privileged mode

No direct access

Register usage

15 general
purpose registers
+ pc

8 general purpose
registers+7 high
registers + pc

SUSHMA RAWAL

Interrupt masks
Interrupt masks are used to stop specific interrupt
requests from interrupting the processor.
Two interrupt request levels- IRQ, FIQ
CPSR has two interrupt mask bits
- 7 (I bit )-IRQ
- 8 (F bit )-FIQ
These interrupt requests are masked when set

SUSHMA RAWAL

Conditional Flags
Updated by
- comparisons
- results of ALU operations that specify S
instruction suffix.
Eg: SUBS

SUSHMA RAWAL

Conditional execution
Conditional execution controls whether or not the
core will execute an instruction.
Condition attribute is postfixed to the instruction
mnemonic, which is encoded into the instruction.
Prior to execution, the processor compares the
condition attribute with the conditional flags in the
CPSR.
If they match then the condition is executed.
When a condition mnemonic is not present, it is
always AL
SUSHMA RAWAL

Conditional execution

SUSHMA RAWAL

Using and updating the Condition Field

To execute an instruction conditionally, simply
postfix it with the appropriate condition:
For example an add instruction takes the form:
ADD r0,r1,r2
; r0 = r1 + r2
(ADDAL)
To execute this only if the zero flag is set:
ADDEQ r0,r1,r2 ; If zero flag
set then
; r0 = r1 + r2

SUSHMA RAWAL

Using and updating the Condition Field

By default, data processing operations do not affect the
condition flags (apart from the comparisons where this is
the only effect).
To cause the condition flags to be updated, the S bit of the
instruction needs to be set by postfixing the instruction
(and any condition code) with an S.
For example to add two numbers and set the condition
flags:
ADDS r0,r1,r2 ; r0 = r1 + r2
; ... and set flags

SUSHMA RAWAL

Exception, Interrupts and the Vector Table

The following exceptions can halt the normal
sequential execution of instructions

Data abort
Prefetch abort
Fast interrupt request
Interrupt request
Software interrupt
Reset
Undefined instructions
SUSHMA RAWAL

Exception, Interrupts and the Vector Table

ARM processor exceptions and associated modes:

Fast interrupt request FIQ mode

Interrupt request IRQ mode
SWI and Reset supervisor mode
Data abort & prefetch abort abort mode
Undefined instruction undefined mode
SUSHMA RAWAL

Exception, Interrupts and the Vector Table

When an exception occurs the ARM
processor always switches to ARM state.

SUSHMA RAWAL

Exception, Interrupts and the Vector Table

Reset: this is the first instruction executed by the processor
when the power is applied.
Initializes the system, sets up stack pointer, memory,
external interrupt sources before enabling FIQ and IRQ.
ISR code should be designed to avoid further triggering of
exceptions.
Data Abort: occurs when memory controller indicates that
an invalid memory address has been accessed.
FIQ exception can be raised within data abort handler.

SUSHMA RAWAL

Exception, Interrupts and the Vector Table

FIQ
Occurs when an external peripheral generates the FIQ
input signal.
Core disables both FIQ and IRQ interrupts.
IRQ
Occurs when an external peripheral generates the IRQ
input signal.
IRQ handler will be entered if neither FIQ or abort
exceptions occur.
On entry IRQ interrupt is disabled.

SUSHMA RAWAL

Exception, Interrupts and the Vector Table

Prefetch Abort
Occurs when an attempt to fetch an instruction results in
memory fault.
FIQ interrupt can be serviced.
Undefined instruction
Occurs when the instruction is not an ARM or THUMB
instruction.

SUSHMA RAWAL

Exception, Interrupts and the Vector Table

SWI interrupt
SWI vector is called when you execute a SWI instruction.
The SWI instruction is frequently used as the mechanism
to invoke an operating system routine.

SUSHMA RAWAL

Exception, Interrupts and the Vector Table

0x00

Reset

0x04

Undefined instruction

0x08

Software interrupt

0x0C

Prefetch abort

0x10

Data abort

0x14

Reserved

0x18

Interrupt request

0x1C

Fast interrupt request

SUSHMA RAWAL

Exception, Interrupts and the Vector Table

Each exception causes the core to enter a specific
mode.
When the exception causes mode change, core
automaticallySaves the cpsr to the spsr of the exception mode
Saves the pc to the lr of the exception mode
Sets the cpsr to the exception mode
Sets pc to the address of the exception handler.
SUSHMA RAWAL

Exception, Interrupts and the Vector Table

To return, exception handler needs to:
Restore CPSR from SPSR of exception mode
Restore PC from LR of the exception mode

SUSHMA RAWAL

Pipeline
The ARM uses a pipeline in order to increase the
speed of the flow of instructions to the processor.
Allows several operations to be undertaken
simultaneously, rather than serially.
Rather than pointing to the instruction being
executed, the PC points to the instruction being
fetched.
Pipeline allows the core to execute an instruction
every cycle.

SUSHMA RAWAL

Pipeline
As the pipeline length increases, the amount of
work done at each stage is reduced.
This allows the processor to attain a higher
operating frequency.
This increases the throughput.
The system latency also increases because it takes
more cycles to fill the pipeline before the core can
execute an instruction.

SUSHMA RAWAL

Pipeline
The execution of a branch instruction or branching
by the direct modification of the pc causes the
ARM core to flush its pipeline.
An instruction in the execute stage will complete
even though an interrupt has been raised.
Other instructions in the pipeline will be
abandoned, and the processor will start filling the
pipeline from the appropriate entry in the vector
table.

SUSHMA RAWAL

ARM nomenclature

T- thumb 16 bit decoder

D JTAG debug
M fast multiplier
I embedded ICE
J - Jazelle
E Enhanced instructions

ARM7TDMI, ARM9T, ARM9E, ARM10E, etc.

SUSHMA RAWAL