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Set No. 1

R10

Code No: P41051

IV B.Tech I Semester Supplementary Examinations, May/June - 2014

COMPUTER ARCHITECTURE
(Computer Science and Engineering)
Time : 3 hours

Max. Marks: 75

Answer any Five Questions

All Questions carry equal marks
*****
1 a) Explain the Flynns classification of parallel Computers.
b) Differentiate the Explicit and Implicit parallelism.
2

[8]
[7]

Describe various techniques for optimization of cache in detail.

[15]

3 a) Define inclusion property? Explain it with neat diagram.

b) Draw and explain the architecture of RISC representative model.

[8]
[7]

4 a) Consider the nonlinear pipeline reservation table:

S1
S2
S3

1
X

4
X

6
X

i) List the set of forbidden latency and initial collision vector.

ii) Draw the state diagram
iii) List all simple cycles and greedy cycles
iv) Determine MAL
b) Differentiate Synchronous and Asynchronous pipeline models.

[8]
[7]

5 a) What is Hot Spot Problem? Explain the methods used to eliminate this
problem.
b) Draw and discuss Multistage Crossbar Network in the Cray Y-MP.

[8]
[7]

What is cache coherence problem in shared memory systems? Explain the

methods used to resolve this problem.

7 a) Explain about processing nodes array processor system

b) Describe the vector super computers architecture.
8

[15]
[8]
[7]

What is instruction level parallelism? Describe the basic compiler techniques

for exploiting instruction level parallelism.

[15]

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JNTUK FAST UPDATES

Code No: P41051

R10

Set No. 2

IV B.Tech I Semester Supplementary Examinations, May/June - 2014

COMPUTER ARCHITECTURE
(Computer Science and Engineering)
Time : 3 hours

Max. Marks: 75

Answer any Five Questions

All Questions carry equal marks
*****
1 a) Explain about the system attributes that affect the systems performance.
b) Explain three types of multiprocessor systems with neat diagrams

[8]
[7]

2 a) What is virtual machine? Explain how memory can be protected via virtual
machines
b) What is Cache memory? Why do systems need cache optimization techniques.
3 a) Discuss about three properties of memory hierarchy in the Computer system.
b) Distinguish the RISC and CISC processors.
4

Explain about Collision free scheduling in detail.

[7]
[8]
[7]
[15]

5 a) Discuss about multi vector computers. Describe the vector processing

principles.
b) Draw the 8X8 omega network using 2X 2 switches. Show the simultaneous
connections between inputs and out puts.
Input
0
4
3
6
7
5
2
1
Output
6
7
0
4
3
1
2
5
Is the network blocked or not?
6 a) What is a dead lock? Explain about deadlock virtual channels.
b) Discuss about multicast routing algorithms.

[8]

[8]

[7]
[8]
[7]

Draw and explain the architecture of CM-2 array processor system.

[15]

Explain about Structural parallelism versus instruction level parallelism

[15]

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