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Report : area
Design : viterbiimpdetbtest
Version: I-2013.12-SP5-4
Date : Tue Apr 12 18:14:55 2016
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Information: Updating design information... (UID-85)
Library(s) Used:
tsl18fs120_scl_ff (File: /mtech/nishant_iit/scl_digital/scl_pdk/stdlib/fs120
/liberty/lib_flow_ff/tsl18fs120_scl_ff.db)
Number
Number
Number
Number
Number
Number
Number
Number

of
of
of
of
of
of
of
of

ports:
nets:
cells:
combinational cells:
sequential cells:
macros/black boxes:
buf/inv:
references:

79
640
626
337
289
0
65
23

Combinational area:
Buf/Inv area:
Noncombinational area:
Macro/Black Box area:
Net Interconnect area:

12577.760328
658.429996
25336.319321
0.000000
1066.690856

Total cell area:

Total area:

37914.079648
38980.770504