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Datasheet 7493 PDF
Datasheet 7493 PDF
described in the appropriate truth table. A symmetrical divide-by-ten count can be obtained from the 90A counters by
connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output QA.
Features
Y
Connection Diagrams
Dual-In-Line Package
TL/F/6533 1
TL/F/6533 2
TL/F/6533
RRD-B30M105/Printed in U. S. A.
DM5490/DM7490A, DM7493A
Decade and Binary Counters
July 1992
b 65 C to a 150 C
DM5490
Parameter
VCC
Supply Voltage
VIH
VIL
IOH
IOL
fCLK
Clock Frequency
(Note 5)
tW
Pulse Width
(Note 5)
DM7490A
Units
Min
Nom
Max
Min
Nom
Max
4.5
5.5
4.75
5.25
0.8
0.8
b 0.8
b 0.8
mA
16
0
32
16
15
16
0
32
16
30
30
15
15
TA
mA
MHz
15
Reset
tREL
25
ns
25
b 55
125
ns
70
Parameter
Conditions
Min
VI
VOH
VOL
II
IIH
VCC e Max
VI e 2.7V
IIL
IOS
ICC
VCC e Max
VI e 0.4V
Short Circuit
Output Current
VCC e Max
(Note 2)
Supply Current
2.4
Typ
(Note 1)
Max
Units
b 1.5
3.4
0.2
V
0.4
mA
80
Reset
40
120
b 3.2
Reset
b 1.6
b 4.8
DM54
b 20
b 57
DM74
b 18
b 57
29
42
mA
mA
mA
mA
Parameter
RL e 400X
CL e 15 pF
From (Input)
To (Output)
Min
fMAX
Maximum Clock
Frequency
A to QA
32
B to QB
16
Units
Max
MHz
tPLH
A to QA
16
ns
tPHL
A to QA
18
ns
tPLH
A to QD
48
ns
tPHL
A to QD
50
ns
tPLH
B to QB
16
ns
tPHL
B to QB
21
ns
tPLH
B to QC
32
ns
tPHL
B to QC
35
ns
tPLH
B to QD
32
ns
tPHL
B to QD
35
ns
tPLH
SET-9 to
QA, QD
30
ns
tPHL
SET-9 to
QB, QC
40
ns
tPHL
SET-0
Any Q
40
ns
DM7493A
Parameter
Units
Min
Nom
Max
4.75
5.25
0.8
VCC
Supply Voltage
VIH
VIL
IOH
b 0.8
mA
IOL
16
mA
fCLK
Clock Frequency
(Note 5)
32
16
Pulse Width
(Note 5)
15
30
Reset
15
tW
tREL
25
TA
MHz
ns
ns
70
Parameter
Conditions
Min
VI
VOH
VOL
II
IIH
VCC e Max
VI e 2.4V
IIL
VCC e Max
VI e 0.4V
IOS
Short Circuit
Output Current
VCC e Max
(Note 2)
ICC
Supply Current
2.4
Typ
(Note 1)
Max
Units
b 1.5
3.4
0.2
V
0.4
mA
Reset
40
80
80
Reset
b 1.6
b 3.2
b 3.2
b 18
26
mA
mA
b 57
mA
39
mA
Parameter
RL e 400X
CL e 15 pF
From (Input)
To (Output)
Min
fMAX
Maximum Clock
Frequency
A to QA
32
B to QB
16
Units
Max
MHz
tPLH
A to
QA
16
ns
tPHL
A to
QA
18
ns
tPLH
A to
QD
70
ns
tPHL
A to
QD
70
ns
tPLH
B to
QB
16
ns
tPHL
B to
QB
21
ns
tPLH
B to
QC
32
ns
tPHL
B to
QC
35
ns
tPLH
B to
QD
51
ns
tPHL
B to
QD
51
ns
tPHL
SET-0
to
Any Q
40
ns
90A
BCD Count Sequence
(See Note A)
Outputs
Count
0
1
2
3
4
5
6
7
8
9
Outputs
Count
QD
QC
QB
QA
L
L
L
L
L
L
L
L
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
8
9
Reset Inputs
QD
QC
QB
L
L
L
L
L
H
H
H
H
H
L
L
L
L
H
L
L
L
L
H
L
L
H
H
L
L
L
H
H
L
L
H
L
H
L
L
H
L
H
L
R9(1)
R9(2)
QD
H
H
X
X
L
L
X
H
H
X
L
X
X
L
L
X
H
X
L
X
L
X
L
H
L
X
L
X
L
L
H
QC
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
QD
QC
QB
QA
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
93A
Reset/Count Function Table
Outputs
R0(2)
Outputs
Count
QA
90A
Reset/Count Function Table
R0(1)
93A
Count Sequence
(See Note C)
QB
L
L
L
L
L
L
COUNT
COUNT
COUNT
COUNT
Reset Inputs
Outputs
QA
R0(1)
R0(2)
QD
QC
QB
QA
L
L
H
H
L
X
H
X
L
COUNT
COUNT
Logic Diagrams
90A
93A
TL/F/6533 4
TL/F/6533 3
The J and K inputs shown without connection are for reference only and are functionally at a high level.
DM5490/DM7490A, DM7493A
Decade and Binary Counters
National Semiconductor
Europe
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