Tutorial of Tanner Tool

Tanner EDA
Circuit Analysis Tutorial
#Introduction
16
#Example 1: DC Operating Point Analysis
18
#Example 2: DC Transfer Analysis
24
#Example 3: Transient Analysis
29
#Example 4: AC Analysis
34
#Example 5: Subcircuits
39
#Example 6: Transient Analysis
45
#Example 7: Transient Analysis, Powerup Mode
51
#Example 8: Transient Analysis, Preview Mode
56
#Example 9: Noise Analysis
61
(continued)
T-Spice Pro User Guide
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#Example 10: Direct Model Evaluation
64
#Example 11: Transistor Subthreshold Behavior
68
#Example 12: MOS Transconductance Amplifier
72
#Design Examples
76
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15
Introduction
Introduction
This tutorial provides a hands-on introduction to the integrated components of
the T-Spice Pro circuit analysis suite.
The tutorial examples follow a standard format, involving sample files (included
upon installation) of various types:
Schematic data files (.sdb) describing the circuits to be analyzed in

graphical form, for display and editing by S-Edit Schematic Editor.
Simulation input files (.sp) describing the circuits to be analyzed in textual

form, for editing and simulation by T-Spice Circuit Simulator. (The
listings of input files in this chapter exclude comments.)
Simulation output files (.out) containing the numerical results of the circuit
analyses, for manipulation and display by W-Edit Waveform Viewer.
T-Spice Pros waveform probing feature integrates S-Edit, T-Spice, and W-Edit
to allow individual points in a circuit to be specified and analyzed (see
Waveform Probing on page 84).
Running the Examples

;
Launch T-Spice.
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Introduction
Use File > Open to open the specified SPICE (.sp) file.
Use Simulation > Run Simulation to start the simulation.
In the Run Simulation dialog, under Waveform options choose Show during.
Click Start Simulation. W-Edit will automatically display the results.
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Example 1: DC Operating Point Analysis

DC operating point analysis finds a circuits steady-state condition, obtained (in
principle) after the input voltages have been applied for an infinite amount of
time.
Schematic
invert1.sdb
Input
invert1.sp
Output
invert1.out
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Schematic
This CMOS inverter is also used in Example 2: DC Transfer Analysis on page 24

and Example 3: Transient Analysis on page 29.
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Most of the module instances visible in the main schematic Page0 of

module invert1 have SPICE OUTPUT properties associated with them. For
example, module Operating point consists of a labeled rectangular (box) symbol
and the property
[SPICE OUTPUT=.op]
When the schematic is exported as a SPICE netlist (T-Spice input file), this
module becomes the .op command.
Similarly, module MOSFET_P has the property
[SPICE OUTPUT=M# %{D} %{G} %{S} %{B} ${model} L=${L} W=${W}
AD=${AD} PD=${PD} AS=${AS} PS=${PS}]
The variables prefixed by % are replaced by the appropriate node names, and the
variables prefixed by $ are replaced by the appropriate (numerical or string)
values (also specified as properties), in the exported netlist. Property values
specified when the module is instanced take precedence over default values: in
this case, the default values for the transistors width and length are 22u and 2u,
respectively, but these are overridden by the specifications W=12u and L=5u at
the level of this modules instancing in module invert1.
Input
c2 out Gnd 800ff
.include ml2_125.md
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m1p out in Vdd Vdd pmos L=5u W=12u

m1n out in Gnd Gnd nmos L=5u W=8u
.op
Vdd Vdd Gnd 3.0
vin in Gnd 1.0
.END
A capacitor c2 (signified by the key letter c), connecting nodes out and GND, is
defined, with a capacitance of 800 femtofarads. (Strictly speaking, the capacitor
could be omitted from the circuit for this example, since it does not affect the DC
operation of the inverter.)
The .include command causes T-Spice to read in the contents of the model file
ml2_125.md for the evaluation of transistors m1n and m1p. This file (which
must be in the same directory as invert1.sp) consists of two .model commands,
describing two MOSFET models called nmos and pmos:
.model nmos nmos
+ Level=2
+ Nsub=1.066E+16
+ Gamma=.639243
+ Uexp=4.612355E-2
+ Vmax=177269
+ Nfs=4.55168E+12
+ Tpg=1.000
+ Cgdo=2.89E-10
+ Cjsw=1.74E-10
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Ld=0.0u
Vto=0.622490
Phi=0.31
Ucrit=174667
Xj=.9u
Neff=4.68830
Rsh=60
Cj=3.27E-04
Mjsw=0.195
Help
Tox=225.00E-10
Kp=6.326640E-05
Uo=1215.74
Delta=0.0
Lambda=0.0
Nss=3.00E+10
Cgso=2.89E-10
Mj=1.067
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.model pmos pmos

+ Level=2
+ Nsub=6.575441E+16
+ Gamma=0.618101
+ Uexp=8.886957E-02
+ Vmax=63253.3
+ Nfs=1.668437E+11
+ Tpg=-1.000
+ Cgdo=3.35E-10
+ Cjsw=2.23E-10
Ld=.03000u
Vto=-0.63025
Phi=.541111
Ucrit=637449
Xj=0.112799u
Neff=0.64354
Rsh=150
Cj=4.75E-04
Mjsw=.307
Tox=225.000E-10
Kp=2.635440E-05
Uo=361.941
Delta=0.0
Lambda=0.0
Nss=3.00E+10
Cgso=3.35E-10
Mj=.341
ml2_125.md assigns values to various Level 2 MOSFET model parameters for

both n- and p-type devices. When read by the input file, these parameters are
used to evaluate Level 2 MOSFET model equations, and the results are used to
construct internal tables of current and charge values. Values read or interpolated
from these tables are used in the computations called for by the simulation.
Two transistors, m1n and m1p, are defined in invert1.sp. These are MOSFETs,
as indicated by the key letter m which begins their names. Following each
transistor name are the names of its terminals. The required order of terminal
names is: draingatesourcebulk. Then the model name ( nmos or pmos in this
example), and physical characteristics such as length and width, are specified.
The .op command performs a DC operating point calculation and writes the
results to the file specified in the Simulate > Start Simulation dialog.
Two voltage sources are defined: Vdd, which sets node Vdd to 3.0 volts relative
to system ground, and vin, which sets node in to 1.0 volt relative to ground.
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Output
The output file lists the DC operating point information for the circuit described
by the input file (in addition to comments of various kinds, not shown here).
DC ANALYSIS
v(out) =
v(in)
=
v(Vdd) =
i(Vdd) =
i(vin) =
2.9309e+00
1.0000e+00
3.0000e+000
-5.8215e-006
0.0000e+000
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Example 2: DC Transfer Analysis

DC transfer analysis is used to study the voltage or current at one set of points in
a circuit as a function of the voltage or current at another set of points. This is
done by sweeping the source variables over specified ranges, and recording the
output.
Schematic
invert2.sdb
Input
invert2.sp
Output
invert2.out
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Schematic
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Input
.include ml2_125.md
m1n out in GND GND nmos l=5u w=8u
m1p out in vdd vdd pmos l=5u w=12u
c2 out GND 800ff
vdd vdd GND 3.0
vin in GND 1.0
.dc vin 0 3 0.02 vdd 2 4 0.5
.print dc in out
This circuit is identical to that of Example 1: DC Operating Point Analysis on

page 18.
The .dc command, indicating transfer analysis, is followed by a list of sources to
be swept, and the voltage ranges across which the sweeps are to take place.
In this example, vin will be swept from 0 to 3 volts in 0.02 volt increments, and
vdd will be swept from 2 to 4 volts in 0.5 volt increments.
The transfer analysis will be performed as follows: vdd will be set at 2 volts and
vin will be swept over its specified range; vdd will then be incremented to 2.5
volts and vin will be reswept over its range; and so on, until vdd reaches the
upper limit of its range.
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The .dc command ignores the values assigned to the voltage sources vdd and vin
in the voltage source statements, but they must still be declared in those
statements.
The results for nodes in and out are reported by the .print dc command to the
specified destination.
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Output
c:\tspro\tutorial\invert2.out
4.0
v(in),0
v(in),1
v(in),2
v(in),3
v(in),4
3.5
Volt (V)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
00
05
10
15
20
25
30
4.0
v(out),0
v(out),1
v(out),2
v(out),3
v(out),4
3.5
Volt (V)
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
vin (V)
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Example 3: Transient Analysis

Transient analysis provides information on how circuit elements vary with time.
The basic T-Spice command for transient analysis has three modes. In the default
mode, the DC operating point is computed, and T-Spice uses this as the starting
point for the transient simulation. Example 3 illustrates this option. (The other
modes, powerup and preview, are treated in Example 7: Transient Analysis,
Powerup Mode on page 51 and Example 8: Transient Analysis, Preview Mode on
page 56.)
Schematic
invert3.sdb
Input
invert3.sp
Output
invert3.out
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Schematic
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Input
.include ml2_125.md
c2 out GND 800ff
vdd vdd GND 3.0
vin in GND PWL(0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V
300ns
+ 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V)
.tran 2n 600n
.print tran in out
This circuit is identical to that of Example 1, except that voltage source vin,
instead of setting the voltage between nodes in and GND at a constant value, here
generates a piecewise linear waveform input (indicated by the keyword PWL) to
in.
The successive legs of the waveform are delimited by the corners, whose times
and voltages are specified in the arguments to PWL. Between 0 and 100
nanoseconds, the voltage at in is zero; between 100 and 105 nanoseconds, the
voltage is linearly interpolated (ramps up) between 0 and 3; between 105 and 200
nanoseconds, the voltage stays at 3; and so on.
The parameters of the device statement that defines vin are continued to the next
line with the + character in the first column.
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The .tran command specifies the characteristics of the transient analysis to be

performed: it will last for 600 nanoseconds, with time steps no larger than 2
nanoseconds.
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Output
v(in)
3.0
Volt (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
50
100
150
200
250
300
350
400
450
500
550
v(out)
3.0
Volt (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
50
100
150
200
250
300
350
400
450
500
550
Time (ns)
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Example 4: AC Analysis
AC analysis characterizes the circuits behavior dependence on small-signal
input frequency. It involves three steps: (1) calculating the DC operating point;
(2) linearizing the circuit; and (3) solving the linearized circuit for each
frequency.
Example 4 involves a standard operational amplifier, consisting of seven
MOSFETs (four n-channel and three p-channel) and two capacitors.
Schematic
opamp.sdb
Input
opamp.sp
Output
opamp.out
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Schematic
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Input
.include ml2_125.md
mn1 vn1 vbias GND GND nmos l=10u w=6u
mn2 vm1 in1 vn1 GND nmos l=6u w=6u
mn3 vf1 in2 vn1 GND nmos l=6u w=6u
mp1 vm1 vm1 Vdd Vdd pmos l=6u w=6u
mp2 vf1 vm1 Vdd Vdd pmos l=6u w=6u
mn4 out vbias GND GND nmos l=10u w=6u
mp3 out vf1 Vdd Vdd pmos l=6u w=20u
cout out GND 2pf
ccomp vf1 out 2pf
vin1 in1 GND 2
Vdd Vdd GND 5.0
vbias vbias GND 0.8
vdiff in2 in1 -0.0007 AC 1 90
.ac DEC 5 1 100MEG
.print ac vdb(out)
.print ac vp(out)
.acmodel opamp1m.out {*}
Three voltage sources (besides Vdd) are defined.
vdiff sets the DC voltage difference between nodes in2 and in1 to 0.0007
volts; its AC magnitude is 1 volt and its AC phase is 90 degrees.
vin1 sets node in1 to 2 volts, relative to GND.
vbias sets node vbias to 0.8 volts, relative to GND.
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The .ac command performs an AC analysis. Following the .ac keyword is

information concerning the frequencies to be swept during the analysis. In this
case, the frequency is swept logarithmically, by decades (DEC); 5 data points are
to be included per decade; the starting frequency is 1 Hz and the ending
frequency is 100 MHz.
The two .print commands write the voltage magnitude (in decibels) and phase (in
degrees), respectively, for the node out to the specified file.
The .acmodel command writes the small-signal model parameters and operating
point voltages and currents for all circuit devices (indicated by the wildcard
symbol *) to the file opamp1m.out.
This example will generate two output files: opamp1.out, specified by the
Simulate > Start Simulation command, and opamp1m.out, specified by the
.acmodel command.
Output
The output file opamp1m.out lists small-signal data for all relevant devices.
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c:\tspro\tutorial\opamp.out
vdb(out)
150
100
(dB)
50
0
-50
-100
-150
10
100
1E3
1E4
1E5
1E6
1E7
vp(out)
150
100
(deg)
50
0
-50
-100
-150
10
100
1E3
1E4
1E5
1E6
1E7
Frequency (Hz)
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Example 5: Subcircuits
Subcircuit definitions allow arbitrarily complex arrangments of nodes and
devices to be easily reused multiple times in a circuit.
Example 5 uses a NAND gate to illustrate the use of subcircuit definitions and
subcircuit parameters.
Schematic
nandgate.sdb
Input
nandgate.sp
Output
nandgate.out
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Schematic
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Input
.include ml2_125.md
.subckt NAND in1 in2 out Vdd length=5u nwidth=10u pwidth=10u
mt1 out in1 n1 GND nmos l='length' w='nwidth'
mt2 n1 in2 GND GND nmos l='length' w='nwidth'
mt3 out in1 Vdd Vdd pmos l='length' w='pwidth'
mt4 out in2 Vdd Vdd pmos l='length' w='pwidth'
.ends
xnand1 a b outab Vdd NAND nwidth=8u pwidth=12u
vvdd Vdd GND 5.0
.ic nand1.n1=2V
va a GND PWL(0ns 0V 100ns 0V 105ns 5V 200ns 5V 205ns 0V
+ 300ns 0V 305ns 5V 400ns 5V 405ns 0V 500ns 0V 505ns 5V
+ 600ns 5V)
vb b GND 5
.print tran a outab nand1/n1
.op
.tran 1n 600n
Subcircuits are defined by blocks of device statements bracketed with the

.subckt and .ends commands, and instanced by statements beginning with the
key letter x.
The .subckt command includes the name of the subcircuit being defined
(NAND), a list of terminals, and three subcircuit parameters. The terminals do not
have a predefined order, but whatever order is used in the definition must be used
in instances. Parameters can be written in any order in both definition and
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instances. Parameter values specified in the definition are used as defaults when
not specified in instances.
Within the subcircuit definition, four MOSFETs are defined in the usual manner
(and in these statements the order of terminals is important: draingatesource
bulk). Node n1 is the source of transistor mt1 and the drain of transistor mt2.
Subcircuit parameters, enclosed by single quotes, are used in place of numerical
values.
The subcircuit definition must be terminated by the .ends command. It is a
common mistake to omit this line accidentally.
After the subcircuit is defined, an instance of the subcircuit is created. The
instance statement begins with the key letter x, but the name of the instance (by
which it is to be identified in the rest of the input file) is nand1, not xnand1.
The list of terminals on the instance statement must have the same order as on the
first line of the subcircuit definition: a b outab Vdd (instance) corresponds to in1
in2 out Vdd (definition). The next argument of the instance statement is the
original subcircuit name (NAND).
Two of the default subcircuit parameter values, as originally specified by the
definition, are overriden by instance-specific assignments. These assignments
may appear in any order. The parameter omitted from the instance statement
(length) retains its default value.
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Initial conditions on node voltages and currents can be set for the purposes of
computing the DC operating point. The .ic command sets node nand1/n1 (that is,
node n1 of instance nand1) to 2 volts for the duration of the DC operating point
calculation. When the transient analysis begins, the node will return to a floating
voltage state.
Voltage source va supplies a PWL (piecewise linear) input waveform to node a.
Two analyses are carried out on this circuit: a DC operating point calculation
(.op) and a transient simulation (.tran) with a duration of 600 nanoseconds and a
maximum timestep of 1 nanosecond.
The .print command reports the results of the simulation for the voltages at nodes
a, outab, and nand1/n1.
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Output
c:\tspro\tutorial\nandgate.out
v(a)
Volt (V)
4
3
2
1
0
0
50
100
150
200
250
300
350
400
450
500
550
v(outab)
Volt (V)
4
3
2
1
0
0
50
100
150
200
250
300
350
400
450
500
550
v(nand1/nn1)
Volt (V)
4
3
2
1
0
0
50
100
150
200
250
300
350
400
450
500
550
Time (ns)
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Transient analysis on a CMOS static D-latch demonstrates the analog D-latch
characteristics of a digital circuit. The circuit has four inverters and four
transmission gates.
Schematic
dlatch.sdb
Input
dlatch.sp
Output
dlatch.out
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Schematic
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Input
.include ml2_125.md
*** Inverter Subcircuits
.subckt invmod1 in out vdd GND
mn out in GND GND nmos l=5u w=8u
mp out in vdd vdd pmos l=5u w=12u
.ends invmod1
.subckt invmod2 in out vdd GND
mp vdd in out vdd pmos l=5u w=12u
mn GND in out GND nmos l=5u w=8u
.ends invmod2
*** D Latch Circuit
mtg1p n1 phi1 data vdd pmos l=5u w=12u
mtg1n n1 phi2 data GND nmos l=5u w=8u
mtg2p n2 phi2 n1 vdd pmos l=5u w=12u
mtg2n n2 phi1 n1 GND nmos l=5u w=8u
xinv1 n1 n3 vdd GND invmod1
xinv2 n3 n2 vdd GND invmod2
xinv3 n5 Q vdd GND invmod1
xinv4 Q n4 vdd GND invmod2
cQ Q GND 64ff
cdata data GND 32ff
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cphi2 phi2 GND 204ff

cphi1 phi1 GND 212ff
cn4 n4 GND 24ff
cn1 n1 GND 96ff
cn3 n3 GND 64ff
cn2 n2 GND 24ff
cn5 n5 GND 96ff
* All time specs x5
vphi1 phi1 GND bit ({0011}
ft=1.25n)
vphi2 phi2 GND bit ({1100}
ft=1.25n)
vdata data GND bit ({1000}
ft=1.25n)
vvdd vdd GND 3
.print tran phi1 phi2 data
.tran 0.2n 200n
pw=10n off=0.0 on=3.0 rt=1.25n

pw=10n off=0.0 on=3.0 rt=1.25n
pw=20n off=0.0 on=3.0 rt=1.25n
n1 n3 n5 Q
The first three statements beginning with v define voltage sources for custom
input waveforms. Following each voltage source name are the names of the input
nodes and the type of waveform. Here, however, not piecewise linear but rather
bit waveforms are used. Following the keyword bit in parentheses are the
parameters specifying the waveform characteristics. The four-digit sequence in
curly brackets { } specifies the sequence of the waves states (either 1, on, or 0,
off). This sequence will be repeated until the simulation is complete. The pulse
width (pw) is 2 nanoseconds. The off voltage is zero, the on voltage is 3 volts,
and the rise (rt) and fall (ft) times are each one-quarter of a nanosecond.
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Voltage source vdd sets the voltage between power and ground to 3 volts.
The .print command writes the results of the simulation for the voltages at six
nodes to the specified file.
The .tran command instructs T-Spice to perform a 200-nanosecond simulation
while printing node voltages at least every 0.2 nanoseconds.
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Output
Volt (V)
c:\tspro\tutorial\dlatch.out
v(phi1)
3
2
1
0
Volt (V)
50
100
150
v(phi2)
3
2
1
0
Volt (V)
50
100
150
v(data)
3
2
1
0
Volt (V)
50
100
150
v(a1)
3
2
1
0
Volt (V)
50
100
150
v(a3)
3
2
1
0
Volt (V)
50
100
150
v(a5)
3
2
1
0
Volt (V)
50
100
150
v(Q)
3
1
0
50
100
150
Time (ns)
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Example 7: Transient Analysis, Powerup Mode

Some circuits do not have a DC steady state or quiescent point. Because such
circuits are constantly fluctuating with time, finding the starting point for their
simulation is a problem. More precisely, the question is how to define the initial
state of a circuit which has no definite DC steady-state condition. This is done in
T-Spice with the powerup option of the .tran command. The powerup option
essentially sets the entire circuit to zero for time equal to zero. As the simulation
proceeds, the voltage sources are allowed to ramp up to their specified values.
The ring oscillator is an example of such a time-dependent circuit.
Schematic
ring.sdb
Input
ring.sp
Output
ring.out
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Schematic
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Input
.include ml2_125.md
.subckt inv in out Vdd
mt1 out in GND GND nmos l=5u w=8u
mt2 out in Vdd Vdd pmos l=5u w=12u
c2 out GND 800ff
.ends inv
xinv1 a1 a2 Vdd inv
xinv2 a2 a3 Vdd inv
xinv3 a3 a4 Vdd inv
xinv4 a4 a5 Vdd inv
xinv5 a5 a6 Vdd inv
xinv6 a6 a7 Vdd inv
xinv7 a7 a1 Vdd inv
cinv1 a7 GND 400ff
vdd Vdd GND 3.0
.print tran a1 a2 a7
.tran/powerup 1n 800n
A subcircuit named inv is defined with three terminals. (This inverter is

structurally identical to the one used in Example 1 and Example 4.)
Seven instances of the subcircuit, with names inv1 through inv7, are defined
next. The output of each inverter is connected to the input of the next in the ring.
The powerup option of the .tran command eliminates the DC convergence
problem for unstable circuits. If the powerup option were not specified, then
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T-Spice would try to calculate a DC operating point, which would lead to

problems for this oscillator.
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Output
c:\tspro\tutorial\ring.out
v(a1)
3.0
Volt (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
100
200
300
400
500
600
700
v(a2)
3.0
2.5
Volt (V)
2.0
1.5
1.0
0.5
0.0
0
100
200
300
400
500
600
700
v(a7)
3.0
Volt (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
100
200
300
400
500
600
700
Time (ns)
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Example 8: Transient Analysis, Preview Mode

Before a lengthy transient simulation is run on a large circuit, the input
waveforms can be examined using the preview option of the .tran command.
This option causes T-Spice to report specified input stimuli only, and to forego
simulation of the remainder of the circuit.
Input
wave.sp
Output
wave.out
Schematic
In addition to illustrating the preview mode, this simple wave circuit
showcases the variety and flexibility of input patterns available to current and
voltage sources in T-Spice.
For a description of this circuit, see Input, below.
Input
r1 n1 GND 2k
r2 n2 GND 2k
r3 n3 GND 2k
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r4
r5
r6
r7
r8
r9
v1
+
v2
n4
n5
n6
n7
n8
n9
n1
GND
GND
GND
GND
GND
GND
GND
2k
2k
2k
2k
2k
2k
pwl (0n 0 100n 0 101n 5 300n 5 301n 0
500n 0 680n 5 700n 0 880n 5 900n 0)
n2 GND pwl (0n 0 100n 0 101n 1 200n 1 201n 2 300n 2 301n
3
+
400n 3 401n 4 500n 4 501n 5 600n 5 601n 4
+
700n 4 701n 3 800n 3 801n 2 900n 2 901n 1)
v3 n3 GND sin (2.5 2.5 30MEG 100n)
v4 n4 GND bit ({01010 11011} on=5.0 off=0.0 pw=50n rt=10n
ft=30n)
v5 n5 GND bit ({5(01010 5(1))} pw=10n on=5.0 off=0.0)
.vector bb {n6 n7 n8 n9}
vb bb GND bus ({50(Ah) 30(7d4) 20(1000)} pw=5n on=5.0
off=0.0)
.print tran n1 n2 n3 n4 n5 n6 n7 n8 n9
.tran/preview 1n 1u
Nine resistor/node/voltage source combinations, numbered 1 through 9, are

defined. Each resistor has a resistance of 2 kilohms; each voltage source,
connected across the corresponding resistor to ground, supplies its characteristic
waveform to the corresponding node.
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57
Two voltage sources, v1 and v2, generate pwl (piecewise linear) inputs. v1
produces a single pulse followed by a pair of sawtooth cycles, and v2 produces a
staircase waveform which takes 1-volt steps from zero up to 5 volts and back
down to 1 volt.
Voltage source v3 generates a sin (sinusoidal) input. It has an amplitude of 2.5
volts, a frequency of 30 MHz, an offset of 2.5 volts from system ground, and a
time delay of 100 nanoseconds after the start of the simulation before the wave
begins.
Voltage source v4 generates a bit input. Enclosed in curly brackets { } are two
binary-valued five-bit patterns specifying the waveform. The two patterns
alternate in time. The on voltage value is 5.0 volts; the off voltage value is zero.
The pulse width (pw), 50 nanoseconds, is the time the wave is either (ramping up
and) on, or (dropping down and) off. The rise time (rt), 10 nanoseconds, is the
time given for the wave to ramp from off to on; and the fall time (ft), 30
nanoseconds, the time given for the wave to drop from on to off.
Voltage source v5 generates a repeating bit input. Two distinct patterns are given
again, but now multiplier factors are included. The wave consists of two
alternating patterns: the first pattern contains five bits, the second is a single bit.
The five-bit pattern is followed by five successive repetitions of the single-bit
pattern, and this sequence is repeated five times. (The same pattern could be
described by {5(3(01) 4(1))}.) The pulse width and on and off voltages are again
specified, but the rise and fall times take default values.
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58
The .vector command defines the bus waveform generated by voltage source vb.
The command assigns the bus a name (bb) and specifies by name the number of
bits the bus waveform will have (four: n6 through n9). The voltage source
statement, which contains the bus keyword, specifies waveforms with one or
more patterns, along with pulse width and level information. The patterns can be
in binary, hexadecimal, octal, or decimal notation. (For decimal patterns the
number of lower-order bits to be collected is also given.)
The first pattern is Ah (hex) = 1010 (binary). Thus, using the names given on
the .vector command, n6=1, n7=0, n8=1, and n9=0. The pattern is repeated
50 times (that is, maintained for a time period equal to the pulse width
multiplied by 50).
The next pattern is 7d4 that is, 7 (decimal) = 111 (binary), or, to four
lower-order bits, 0111. So n6=0, n7=1, n8=1, and n9=1. The pattern is
repeated 30 times.
The last pattern is 1000 (binary), so n6=1, n7=0, n8=0, and n9=0. The
pattern is repeated 20 times.
The .print command writes the results at the output nodes of all nine voltage
sources.
The .tran preview command reports the input waveforms in place of running the
simulation.
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59
Volt (V
Volt (V)
Volt (V)
Volt (V)
Volt (V)
Volt (V)
Volt (V)
Volt (V)
Volt (V)
Output
c:\tspro\tutorial\wave.out
5.0
v(n1)
2.5
0.0
00
5.0
01
02
03
04
05
06
07
08
09
v(n2)
2.5
0.0
00
5.0
01
02
03
04
05
06
07
08
09
v(n3)
2.5
0.0
00
5.0
01
02
03
04
05
06
07
08
09
v(n4)
2.5
0.0
00
5.0
01
02
03
04
05
06
07
08
09
v(n5)
2.5
0.0
00
5.0
01
02
03
04
05
06
07
08
09
v(n6)
2.5
0.0
00
5.0
01
02
03
04
05
06
07
08
09
v(n7)
2.5
0.0
00
5.0
01
02
03
04
05
06
07
08
09
v(n8)
2.5
0.0
00
5.0
2.5
0.0
0.0
01
02
03
04
05
06
07
08
09
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
v(n9)
Time (us)
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60
Example 9: Noise Analysis

Real circuits, of course, are never immune from small, random fluctuations in
voltage and current levels. In T-Spice, the influence of noise in a circuit can be
simulated and reported in conjunction with AC analysis. The purpose of noise
analysis is to compute the effect of the noise associated with various circuit
devices on an output voltage or voltages as a function of frequency.
Schematic
opamp2.sdb
Input
opamp2.sp
Output
opamp2.out
Schematic
For a description of this circuit, see Example 4.
Input
.include ml2_125.md
mn3 vf1 in2 vn1 GND nmos l=6u w=6u
Contents
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61

mp2 vf1 vm1 Vdd Vdd pmos l=6u w=6u
mn4 out vbias GND GND nmos l=10u w=6u
mp3 out vf1 Vdd Vdd pmos l=6u w=20u
cout out GND 2pf
ccomp vf1 out 2pf
vin1 in1 GND 2
Vdd Vdd GND 5.0
vbias vbias GND 0.8
vdiff in2 in1 -0.0007 AC 1 90
.ac DEC 5 1 100MEG
.noise v(out) vbias
.print noise inoise onoise transfer dn(mn1) inoise(tot)
onoise(tot)
Noise analysis is performed in conjunction with AC analysis; if the .ac command

is missing, then the .noise command is ignored. With the .ac command present,
the .noise command causes noise analysis to be performed at the same
frequencies: starting at 1 Hz, ending at 100 MHz, 5 data points per decade.
The .noise command takes two arguments: the output at which the effects of
noise are to be computed, and the input at which the noise can be considered to
be concentrated for the purposes of estimating the equivalent noise spectral
density.
The .print noise command, with six arguments, writes to the output file 11
numbers for each frequency analyzed. Many other options are available.
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62
Volt (V/V)
Volt (uV/Rt(Hz))
Output
c:\tspro\tutorial\opamp2.out
inoise(mag)
onoise(mag)
30
20
10
0
1
10
100
1E3
1E4
1E5
1E6
1E7
1E8
v(out)/vbias
1.5
1.0
0.5
0.0
10
100
1E3
1E4
1E5
1E6
1E7
1E8
dn(mn1,RD)
dn(mn1,RS)
dn(mn1,FN)
Volt (nV/Rt(Hz)
Volt (nV/Rt(Hz)
1
80
80
Volt (kV/A)
Volt (mV/Rt(Hz)
1
400
200
0
-200
-400
300
10
100
1E3
1E4
1E5
1E6
1E7
1E8
dn(mn1,ID)
60
40
20
0
1
10
100
1E3
1E4
1E5
1E6
1E7
1E8
dn(mn1,TOT)
60
40
20
0
1
10
100
1E3
1E4
1E5
1E6
1E7
1E8
dn(mn1,RX)
200
100
0
Volt (mV)
10
100
1E3
1E4
1E5
1E6
1E7
1E8
inoise(total)
onoise(total)
1.0
0.5
0.0
1
10
100
1E3
1E4
1E5
1E6
1E7
1E8
Frequency (Hz)
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63
Example 10: Direct Model Evaluation

T-Spice employs two fundamental techniques of simulation: direct model
evaluation and table-based evaluation.
In direct model evaluation, values are computed as needed from analytical

equations, returning results as accurate as the models used allow.
In table-based evaluation, tables of values are precomputed from analytical

equations at finite resolution, and needed values are linearly interpolated
from stored values. This technique is slightly less accurate, but is
significantly faster.
Table-based evaluation is T-Spices default simulation technique. Direct model

evaluation can be explicitly called for, as in Example 10, which repeats the
transient analysis of the inverter of Example 1.
Schematic
invert4.sdb
Input
invert4.sp
Output
invert4.out
Contents
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64
Schematic
Contents
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65
Input
.options deftables=0
.include ml2_125.md
c2 out GND 800ff
vdd vdd GND 3.0
vin in GND PWL(0ns 0V 100ns 0V 105ns 3V 200ns 3V 205ns 0V
300ns
+ 0V 305ns 3V 400ns 3V 405ns 0V 500ns 0V 505ns 3V 600ns 3V)
.tran 2n 600n
.print tran in out
This input file is identical to that of Example 1, with one addition: the command
.options deftables=0, which turns off default table generation and causes the
circuit to be simulated by direct evaluation of device models.
Output
Compare invert4.out, obtained using direct model evaluation, to invert1.out,
obtained using internal table-based evaluation. For the inverter or other digital
circuits there will be only slight differences in the results. For analog circuits,
however, there can be greater discrepancies between results from the two
evaluation techniques.
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66
v(in)
3.0
Volt (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
50
100
150
200
250
300
350
400
450
500
550
v(out)
3.0
Volt (V)
2.5
2.0
1.5
1.0
0.5
0.0
0
50
100
150
200
250
300
350
400
450
500
550
Time (ns)
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67
Example 11: Transistor Subthreshold Behavior

Modern analog designs are required to meet strict specifications with tight
tolerances. Designers therefore need models that can accurately simulate
semiconductor device behavior over all regions of operation.
It has been traditionally difficult to model the operation of MOSFETs in the
subthreshold region, particularly through the transition from subthreshold to
above threshold. This region is of special interest to designers of low-power and
advanced analog designs, in which MOSFETs are sometimes intentionally biased
to operate in this transition region.
In subthreshold, the saturation drain current of a MOSFET is an exponential
function of the gate voltage, and the drain current saturates at a drain voltage that
is independent of gate voltage. Well above threshold, the transistor drain current
is a quadratic function of the gate voltage, and the drain current saturates at a
drain voltage which is a function of the gate voltage.
T-Spice supports the simulation of MOSFETs in the subthreshold region in the
following ways.
The BSIM3 models (revisions 2 and 3) in the Advanced Model Package

include subthreshold characteristics.
The Maher-Mead model simulates MOSFETs over all regions of operation

with continuous functions for superior accuracy and convergence.
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68
The T-Spice simulation engine can accurately simulate low-current

operation without convergence problems even when internal tables are used
for improved speed.
Example 11 simulates the gate characteristics of a transistor in subthreshold by

sweeping its gate voltage while holding its drain voltage fixed.
Input
trangm.sp
Output
trangm.out
Input
.include ml5_20.md
mn5 drain gate GND GND nmos l=10u w=6u
vdrain drain GND 5
vgate gate GND 0.85
.dc vgate .5 1.5 0.01
.print dc id(mn5)
.options abstol=1E-14
Voltage source vgate is attached to the gate terminal of the MOSFET mn5 and is
swept from 0.5 to 1.5 volts with the .dc command. Voltage source vdrain is
attached to the drain terminal with a fixed value of 5 volts, which keeps the
transistor well in saturation. The source and bulk terminals are grounded.
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69
The .print dc command reports the current through the drain terminal of mn5.
The .options abstol command changes the absolute value of the current
tolerance that T-Spice uses, so that low-current and subthreshold behavior can be
simulated accurately. The results are quite accurate when T-Spice uses internal
tables (its default simulation technique) to represent the model. More accuracy
can be achieved by defining a larger gridsize (finer resolution for example,
.gridsize mos 500 500 500), or by using direct model evaluation (with the
.options deftables=0 command), but this is not necessary in most cases.
Output
The output is a logarithmic plot of the drain current against the gate voltage. The
logarithm of the current is a straight line for low gate voltages and shows a
smooth transition between low-current exponential behavior and high-current
quadratic behavior.
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c:\tspro\tutorial\trangm.out
id(mn5),0
1.0E-6
Current (A)
1.0E-7
1.0E-8
1.0E-9
1.0E-10
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
vgate (V)
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71
Example 12: MOS Transconductance Amplifier

The basic transconductance amplifier produces an output current proportional in
magnitude to the difference between the input voltages. Proper modeling of the
transconductance amplifiers output current behavior, over a broad range of
differential voltages, requires accurate subthreshold modeling of its transistors.
Otherwise, the predicted trasnconductance characteristics will be inaccurate. This
circuit can be simulated correctly in subthreshold by T-Spice.
Schematic
transamp.sdb
Input
transamp.sp
Output
transamp.out
Contents
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72
Schematic
Contents
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73
Input
.include ml5_20.md
mn3 out in2 vn1 GND nmos l=6u w=6u
mp2 out vm1 Vdd Vdd pmos l=6u w=6u
vin1 in1 GND 2
Vdd Vdd GND 5.0
vbias vbias GND 0.7
vdiff in2 in1 0.0
vout out GND 2.5
.options abstol=1E-14
.dc vdiff -1 1 0.01
.print dc i1(vout)
This circuit is identical to the one described in Example 4, except that the output
stage (inverter) has been removed, and a voltage source has been connected to
the output so that the transconductance characteristics of the amplifier can be
measured.
The .options abstol command changes the absolute value of the current
tolerance that T-Spice uses, so that low-current and subthreshold behavior can be
simulated accurately.
Contents
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74
Output
c:\tspro\tutorial\transamp.out
i1(vout),0
Current (nA)
2
1
0
-1
-2
-1 0
-0 5
00
05
10
id(mn3),0
Current (nA)
2
1
0
-1
-2
-1 0
-0 5
00
05
10
id(mn2),0
Current (nA)
2
1
0
-1
-2
-1.0
-0.5
0.0
0.5
1.0
vdiff (V)
Contents
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75
Design Examples
Design Examples
Following are design examples created and simulated by T-Spice Pro. Use S-Edit
to run all of the examples.
Wide-Band GaAs IC Amplifier

This example describes the design and performance of a wide-band GaAs IC
amplifier. The amplifier consists of two cascaded stages. It features a
high-voltage gain (>20 dB), wide bandwidth, and very low input VSWR. This
amplifier is useful for many signal processing and instrument/measurement
applications.
The example consists of four sub-examples for characterizing the AC, DC and
transient performance and measuring S-parameters of the circuit. The example
files are in the ~\example\gaasamp directory. The contents of the directory are:
gaas.mdGaAs
MESFET and diode model parameters for the

example.
amp_ac.sdb
The amplifier schematic, containing commands for

AC, noise, and small-signal parameter analysis.
amp_dc.sdb

DC transfer analysis.
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76
Design Examples
amp_spar.sdb

analyzing the scattering parameters of the circuit.
amp_tran.sdb

transient analysis.
AC Analysis Example
;
Use File > Open to open amp_ac.sdb.
Use Module > Open to open module amp_ac (the top module) if it is not already
open.
Follow the procedures described in the Waveform Probing Tutorial on page 95 to

export, simulate and probe the design.
To probe into a subcircuit, select the subcircuit and use the Probe toolbar buttons
to move through different levels. Click the Probe Push button to get into the
next lower level of the circuit, the Probe Pop button to go back to the next higher
level, and the Probe Top Level button to go to the top level.
Use the analysis buttons on the Probe toolbar to view the results of different
types of analyses.
Select the AC/Noise button and click on nodes to view AC analysis results. Click
on devices to view noise analysis results.
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77
Design Examples
Select the Operating Point/Small Signal button and click on nodes to view DC
operating point values. Click on devices for small signal parameters.
The measurement results are listed in the output file amp_ac.out.
DC Analysis Example
;
Use File > Open to open amp_dc.sdb.
Use Module > Open to open module amp_dc (the top module) if it is not already
open.

export, simulate, and probe the design.
Select the DC Transfer button in the Probe toolbar. Click on nodes to view DC
transfer analysis results.
Select the Operating Point/Small Signal button and click on nodes to view DC
Transient Analysis Example

This example contains a polynomial voltage controlled voltage source. This
provides a ramp-up sinusoidal wave as an input source.
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78
Design Examples
Use File > Open to open amp_tran.sdb.
Use Module > Open to open module amp_tran (the top module) if it is not
already open.

Use the analysis buttons on the Probe toolbar to view the results of different
types of analyses.
Select the Transient button and click on nodes to view transient analysis results.
Click on devices to view noise analysis results.
Select the Operating Point/Small Signal button. Click on nodes to view DC

S-parameter measurement example

;
Use File > Open to open amp_spar.sdb.
Use Module > Open to open module amp_spar (the top module) if it is not
already open.
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79
Design Examples
The circuit is wired in the same way that s-parameters are measured. The module
amp in the circuit is the amplifier that was studied in the previous three
examples.
;

Click on ports S11, S21, S12, and S22 to find the s-parameters S11, S21, S12, and
S22 of the amplifier.
Voltage Controlled Ring Oscillator

This example describes the design and performance of a voltage-controlled ring
oscillator. The ring VCO consists of a control stage that provides bias and tuning
voltage and seven differential cells that form a ring oscillator. The tuning voltage
from the control stage controls the frequency of the ring oscillator. The
applications of VCO include frequency modulators, tone generators, A/D
converters, and digital voltmeters.
The example files are in the ~\example\ringvco directory. The contents of the
directory are:
mosis2u.md
MOSIS MOSFET 2um model parameters. This is

the model that is used in simulating the design.
Contents
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80
Design Examples
ringvco.sdb
The ring oscillator schematic, containing

commands for transient analysis.
tech.sdb
A small library of technology setup modules which

can be included in S-Edit schematics. Some of
these modules are used in the above design.
vco.c
An external T-Spice macromodel of a voltagecontrolled oscillator.
vco.dll
A DLL which contains the VCO macromodel

described above. This DLL is used by T-Spice
during simulation.
vcomacro.sp
A Spice file showing the performance of the VCO

macro-model. This file has macromodel parameters
that were tuned to match the performance of the
actual circuit in ringvco.sdb.
Use File > Open to open ringvco.sdb.
Use Module > Open to open module ringvco (the top module) if it is not already
open.

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81
Design Examples
This example will be modeled using the user-defined external model feature in
T-Spice. The file vco.c is the ring VCO model written in the C programming
language. You can compile and build the file into a dynamically linked library,
vco.dll, before you simulate the circuit. You can then include vco.dll in the
SPICE file for simulation in T-Spice.
;
Use File > Open to open vcomacro.sp. This file includes the file vco.dll.
Select Simulation > Run Simulation to simulate the file.
Note:
For more information on the external model feature in T-Spice, see User-Defined
External Models on page 634 of the T-Spice User Guide and Reference.
8-Bit Analog-to-Digital Converter

The design used in this example is an 8-bit analog-to-digital converter (ADC).
The converter digitizes music signals with a frequency range of 20Hz20kHz.
Due to the limitations of practical anti-aliasing filters, the sampling rate is set to
be 83 kHz, about twice the Nyquist rate. The A/D conversion time is 12ms. In
order to archive 8-bit accuracy, the quantization error should be less than 0.01V.
The example file is in the ~\example\adc directory.
;
Use File > Open to open adc8.sdb.
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82
Design Examples
Use Module > Open to open module adc_sp (the top module) if it is not already
open.

Contents
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83

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Circuit Analysis Tutorial

#Example 1: DC Operating Point Analysis

#Example 2: DC Transfer Analysis

#Example 3: Transient Analysis

#Example 6: Transient Analysis

#Example 7: Transient Analysis, Powerup Mode

#Example 8: Transient Analysis, Preview Mode

#Example 9: Noise Analysis

T-Spice Pro User Guide

Circuit Analysis Tutorial

#Example 10: Direct Model Evaluation

#Example 11: Transistor Subthreshold Behavior

#Example 12: MOS Transconductance Amplifier

T-Spice Pro User Guide

Circuit Analysis Tutorial

Schematic data files (.sdb) describing the circuits to be analyzed in

Simulation input files (.sp) describing the circuits to be analyzed in textual

Running the Examples

T-Spice Pro User Guide

Circuit Analysis Tutorial

Use Simulation > Run Simulation to start the simulation.

Click Start Simulation. W-Edit will automatically display the results.

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 1: DC Operating Point Analysis

Example 1: DC Operating Point Analysis

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 1: DC Operating Point Analysis

This CMOS inverter is also used in Example 2: DC Transfer Analysis on page 24

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 1: DC Operating Point Analysis

Most of the module instances visible in the main schematic Page0 of

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 1: DC Operating Point Analysis

m1p out in Vdd Vdd pmos L=5u W=12u

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 1: DC Operating Point Analysis

.model pmos pmos

ml2_125.md assigns values to various Level 2 MOSFET model parameters for

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 1: DC Operating Point Analysis

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 2: DC Transfer Analysis

Example 2: DC Transfer Analysis

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 2: DC Transfer Analysis

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 2: DC Transfer Analysis

This circuit is identical to that of Example 1: DC Operating Point Analysis on

T-Spice Pro User Guide

Circuit Analysis Tutorial

Example 2: DC Transfer Analysis

T-Spice Pro User Guide

Circuit Analysis Tutorial