Single cycle CPU: Datapath & Control

:-

-:
-

.
.
.
-

Single cycle CPU: Datapath & Control

:-

:MIPS
lw, sw :
add, sub, and, or, slt :
beq, j :

:
(program counter ) PC ) (fetch ) (.
) (decode . ) (executeFetch
) ( j ALU .PC = PC+4
Decode

Exec


) = FETCH (1  " .PC
) = DECODE (2   )
( .
   ,   
 .
 = EXECUTE  ALU , .
 = MEMORY :#  )(Store
 ).(Load
 = WRITE BACK # .

 : ) ( instruction memory and data memory

PC
)(Register file
)(ALU

5. Write
Back

4. Memory

3. Execute

2. Decode/
Register
Read

) (.. ALU

1. Instruction
Fetch



PC

Add
4

Instruction
Memory
Instruction

Read
Address

PC

PC )( .

(Decoding)
. function opcode 

Control
Unit

Instruction

Read Addr 1
Register Read
Data 1
Read Addr 2
File
Write Addr
Read
Data 2
Write Data

Instruction Formats Handled by the Datapath

field
bit positions

0
31-26

rs

rt

rd

shift n

function

25-21

20-16

15-11

10-6

5-0

rs

rt

25-21

20-16

R-type instruction

field
bit positions

35 or 43
31-26

address
15-0

Load Word (LW)/Store Word (SW) instruction

field
bit positions

4
31-26

Branch Equal (BEQ) instruction

rs

rt

address

25-21

20-16

15-0

(add, sub, slt, and, or) R

0
31-26

rs

rt

rd

shift n

function

25-21

20-16

15-11

10-6

5-0

RegWrite

Instruction

Read Addr 1
Register Read
Data 1
Read Addr 2
File
Write Addr
Read
Data 2
Write Data

ALU control

ALU

overflow
zero

(RegWrite)

 LW SW
-

" ) (rs ) 0-15

(.
SW )(rt
.
LW ).(rt
address
15-0
MemWrite

ALU control

Read Addr 1
Register Read
Data 1
Read Addr 2
File
Write Addr
Read
Data 2
Write Data

Address

ALU

Write Data

MemRead

LW
SW

20-16

25-21

31-26

RegWrite

overflow
zero
Data
Memory Read Data

rt

rs

35 or 43

32

Sign
Extend

16

Instruction

Branch
)ALU
( Z
PC ( " branch target )
.4
Add
Add

Shift
left 2

rs

rt

Branch
target
address

address
ALU control

PC

Instruction

Read Addr 1
Register Read
Data 1
Read Addr 2
File
Write Addr
Read
Data 2
Write Data

16

Sign
Extend

32

zero (to branch

control logic)
ALU

 JUMP
28 PC 26
.

Add
4
4

Jump
address
28

Instruction
Memory

Shift
left 2

Instruction
26

Read
Address

PC

 -
 "
 :

,
) , (

) (mux
.

)
(

Principle Datapath with Control (R type & LW SW)

Add

RegDst

RegWrite

ALUSrc

4
Rs
Instruction
Memory
PC

Read
Address

Rt

Instruction
Rd

16

MemWrite

ovf
zero

Read Addr 1
Register Read
Data 1
Read Addr 2
File
Write Addr
Read
Data 2
Write Data

Sign
Extend

ALU control

Address

ALU

Data
Memory Read Data
Write Data

MemRead
32

MemtoReg

)(Register File, ALU, Memory read/write

) " (

:
opcode 26-31 ) rs ( ) rt ( ) rd (R .(lw) rt ) (beq,lw,sw .0-15function

shift n

rd

rt

rs

5-0

10-6

15-11

20-16

25-21

address
15-0

rt
20-16

0
31-26

rs
25-21

R-type instruction

I-type instruction
31-26

Some of the Control Line Functions

Signal Name

Effect when 0

Effect when 1

MemRead

None.

Data Memory contents at the read address

are put on read data output.

MemWrite

None.

Data memory contents at address given by

write address are replaced by value on write
data input

ALUSrc

The second ALU operand comes from

the second register file output.

The second ALU operand is the signextended lower 16 bits of the instruction.

RegDst

The register destination for the

register write comes from the rt
field.

The register destination number for the

register write comes from the rd field.

RegWrite

None.

The register given by write register number

input is written into with the value on the
write data input.

PCSrc
(== Branch &
cond)

The PC is replaced by the output of

adder that computes the value of
PC+4.

The PC is replaced by the output of the

adder that computes the branch target.

MemtoReg

The value fed to the register write

data input comes from the ALU.

The value fed to the register write data input

comes from the data memory.

Single Cycle Datapath with Control Unit

0
Add
Add
Shift
left 2

4
ALUOp
Instr[31-26]

1
PCSrc

Branch

MemRead
MemtoReg
MemWrite

Control
Unit
ALUSrc
RegWrite

RegDst
Instruction
Memory
PC

Read
Address

Instr[31-0]

ovf

Instr[25-21] Read Addr 1

Register Read
Instr[20-16] Read Addr 2
Data 1
File
0
Write Addr
Read
1
Data 2
Instr[15
Write Data
-11]
Instr[15-0]
16

Sign
Extend

Address

zero
0

ALU

32

Instr[5-0]

ALU
control

Data
Memory Read Data

Write Data

R-type Instruction Data/Control Flow

0
Add
Add
Shift
left 2

4
ALUOp
Instr[31-26]

1
PCSrc

Branch

MemRead
MemtoReg
MemWrite

Control
Unit
ALUSrc
RegWrite

RegDst
Instruction
Memory
PC

Read
Address

Instr[31-0]

ovf

Instr[25-21] Read Addr 1

Register Read
Instr[20-16] Read Addr 2
Data 1
File
0
Write Addr
Read
1
Data 2
Instr[15
Write Data
-11]
Instr[15-0]
16

Sign
Extend

Address

zero
0

ALU

32

Instr[5-0]

ALU
control
10

Data
Memory Read Data

Write Data

Load Word Instruction Data/Control Flow

0
Add
Add
Shift
left 2

4
ALUOp
Instr[31-26]

1
PCSrc

Branch

MemRead
MemtoReg
MemWrite

Control
Unit
ALUSrc
RegWrite

RegDst
Instruction
Memory
PC

Read
Address

Instr[31-0]

ovf

Instr[25-21] Read Addr 1

Register Read
Instr[20-16] Read Addr 2
Data 1
File
0
Write Addr
Read
1
Data 2
Instr[15
Write Data
-11]
Instr[15-0]
16

Sign
Extend

Address

zero
0

ALU

32

Instr[5-0]

ALU
control

Data
Memory Read Data

Write Data

Load Word Instruction Data/Control Flow

0
Add
Add
Shift
left 2

4
ALUOp
Instr[31-26]

1
PCSrc

Branch

MemRead
MemtoReg
MemWrite

Control
Unit
ALUSrc
RegWrite

RegDst
Instruction
Memory
PC

Read
Address

Instr[31-0]

ovf

Instr[25-21] Read Addr 1

Register Read
Instr[20-16] Read Addr 2
Data 1
File
0
Write Addr
Read
1
Data 2
Instr[15
Write Data
-11]
Instr[15-0]
16

Sign
Extend

Address

zero
0

ALU

32

Instr[5-0]

ALU
control
00

Data
Memory Read Data

Write Data

Branch Instruction Data/Control Flow

0
Add
Add
Shift
left 2

4
ALUOp
Instr[31-26]

1
PCSrc

Branch

MemRead
MemtoReg
MemWrite

Control
Unit
ALUSrc
RegWrite

RegDst
Instruction
Memory
PC

Read
Address

Instr[31-0]

ovf

Instr[25-21] Read Addr 1

Register Read
Instr[20-16] Read Addr 2
Data 1
File
0
Write Addr
Read
1
Data 2
Instr[15
Write Data
-11]
Instr[15-0]
16

Sign
Extend

Address

zero
0

ALU

32

Instr[5-0]

ALU
control
01

Data
Memory Read Data

Write Data

Branch Instruction Data/Control Flow

0
Add
Add
Shift
left 2

4
ALUOp
Instr[31-26]

1
PCSrc

Branch

MemRead
MemtoReg
MemWrite

Control
Unit
ALUSrc
RegWrite

RegDst
Instruction
Memory
PC

Read
Address

Instr[31-0]

ovf

Instr[25-21] Read Addr 1

Register Read
Instr[20-16] Read Addr 2
Data 1
File
0
Write Addr
Read
1
Data 2
Instr[15
Write Data
-11]
Instr[15-0]
16

Sign
Extend

Address

zero
0

ALU

32

Instr[5-0]

ALU
control
01

Data
Memory Read Data

Write Data

Adding the Jump Operation

Instr[25-0]

Shift
left 2

26

28

32

PC+4[31-28]

Add
Add
Shift
left 2

4
Jump

ALUOp
Instr[31-26]

1
PCSrc

Branch

MemRead
MemtoReg
MemWrite

Control
Unit
ALUSrc
RegWrite

RegDst
Instruction
Memory
PC

Read
Address

Instr[31-0]

ovf

Instr[25-21] Read Addr 1

Register Read
Instr[20-16] Read Addr 2
Data 1
File
0
Write Addr
Read
1
Data 2
Instr[15
Write Data
-11]
Instr[15-0]
16

Sign
Extend

Address

zero
0

ALU

32

Instr[5-0]

ALU
control

Data
Memory Read Data

Write Data

 -

) . ,lw
(
Cycle 2

Cycle 1
Clk

Waste

sw

lw


) ,(
 .


CPU Time = IC X CPI X Clock Cycle Time

CPI = 1.
IC is the same for all implementations of MIPS ISA.
Everything depends on clock cycle Time.

I-type

stage1

stage2

stage3

stage4

R - type

I-fetch

regs

ALU

regs

Load

I-fetch

regs

ALU

mem

Store

I-fetch

regs

ALU

mem

Branch

I-fetch

regs

ALU

Jump

I-fetch

stage5

total (ns)
38

regs

48
39
29
9

table assumes ALU, Adders - 10ns; Memory - 10ns; register file - 9ns

Assume the following dynamic instruction counts for a typical

program (gcc compiler)
I-type

Loads

22

Stores

11

R-type

49

Branch

16

Jump

Using table of instruction delays from the previous slide, calculate actual
average time per instruction for gcc.
(.49 x 38ns) + (.22 x 48ns) + (.11 x 39ns) + (.16 x 29ns) + (.02 x 9ns)
= 38.29ns
For single cycle implementation we must use longest period = 48ns;
slowdown = approx. 48/38.29 = 25.36%. Floating point or other longer instructions
would make the slowdown much worse.

)(multicycle

)(pipeline