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Bi 18
Tn bi : Mch gii m nn tn hiu ting (MPEG - audio Decoder)
M bi : HCO 01 22 18
Gii thiu :
y l bi hc gii thiu v mch gii m nn tn hiu ting (MPEG - AUDIO Decoder)
dng trong cc my CD/VCD. Bao gm: S chc nng, nhim v v nguyn l hot ng
ca mch.. ng thi, hng dn hc sinh thc hnh v cc ni dung: Chn on, kim tra,
sa cha v thay th cc linh kin h hng trong mch gii m nn tn hiu ting (MPEG AUDIO Decoder) ca my CD/VCD.
Do bi hc ch vit cho cp cng nhn, ch yu phc v cho vic vn hnh, bo dng,
bo hnh v sa cha, nn bi hc s cung cp nhng kin thc c bn nht, tm tt nht v
vn gii m nn, nhm gip cho hc vn c mt khi nim cn bn v mch MPEG dng
trong my VCD. Chnh v vy, bi hc ch cp ch yu v c th cc tn hiu vo /ra, cc mi
lin lc quan trng ca mch gii m nn tn hiu ting (MPEG - AUDIO Decoder) vi cc khi
chc nng khc, v cc tn hiu quang trng m bo cho mch hot ng. Cn vn i su
v chi tit x l c th trong khi c vit dnh cho cp cao hn mi cc bn xem cun
Sa cha my DVD dnh cho cp III.

Mc tiu thc hin: Gip cho hc vin c kh nng

1. Trnh by c chc nng, nhim v ca mch gii m nn tn hiu ting ng theo bi
hc.
2. Trnh by c nguyn l hot ng ca mch gii m nn tn hiu ting ng theo bi
hc.
3. Chn on, kim tra v sa cha nhng h hng ca mch gii nn tn hiu ting ng
tiu chun thit k.

Ni dung chnh:
Bao gm cc vn chnh sau:
1. Khi nim chung, S khi, chc nng v nhim v ca cc khi trong mch gii m
nn tn hiu ting
2. Hin tng, nguyn nhn v phng php sa cha nhng h hng ca mch in gii
m nn tn hiu ting
3. Sa cha nhng h hng ca mch gii m nn tn hiu ting
Cc hnh thc hc tp:
I.

Nghe thuyt trnh trn lp C THO LUN

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1. Khi nim chung v d liu nn AUDIO MPEG dng trong my VCD:
Trong my VCD tn hiu m thanh c nn theo chun
MPEG-1 theo hai
loi l Layer I v Layer II .
hiu nguyn l hot ng ca mch giI nn, ta cn nm s lc cc
phn sau:
1.1.

Cu trc ca chui d liu nn m thanh:

Hnh 1.1: Cu trc ca chui d liu nn m thanh

Dng d liu nn m thanh (MPEG AUDIO) c cu trc gm nhiu gi m thanh
(Audio Packets), mi gi c cu trc nh (hnh 1.1). Bao gm:

Audio Packet Header: Cha cc thng tn v m bt u ca gi (Packet

Start Code), chiu di ca gi (Length: ch s lng Byte ca gi ), v phn
Presentation time Stamps th khng bt buc.

Aud io Frame: Trong gi m thanh c nhiu khung lin tc, trong mi khung
cha nhiu Slice v mt s d liu h tr. C th mt khung m thanh c
cc phn t sau:
+

Audio Frame Header:

Cha nhiu thng tin khc nhau nh : T

ng b (Sync Word), ID dng cho b m ho nhn dng d liu c

m ho nn hay khng, Kiu lp (Layer Type) cho bit m ho Layer
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I, II hay III. Tc bit ly mu, s knh Ni chung l cc thng tin
v h thng.
+ Audio Frame Cyclic Redundancy Code (CRC): M kim tra khung,
dng nhn dng li ca khung.
+

Audio Data: D liu ca cc knh m thanh.(Xem hnh 1.2)

+ Ancillary/ User Data: L phn t cui cng ca mt khung m thanh.

Ni chung, c php ca chui d liu nn m thanh c tm tt (nh
hnh 1.2). Mi cc bn tham kho:

Hnh 1.2: Cu trc ca chui d liu nn m thanh

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Cc gi MPEG Audio s c ghp chung vi cc gi Video thnh chui d liu
nn CD-DATA hay Serial Bitstream.
ti to li tn hiu Audio t dng bits chng trnh hay dng bit h thng
(System Bitstream) hay cn gi Serial Bitstream. Thc hin tch to thnh
dng tn hiu MPEG Audio v a vo b phn gii m Audio decoder ti to li
tn hiu Audio di dng s (PCM) cp cho mch DAC phc hi li tn hiu m
thanh dng Analog.
Nu i su v l thuyt cu trc chi tit ca mch gii m nn m thanh th rt
phc tp. Do gii hn ca gio trnh phc v cho vic sa cha nn ta ch quan tm
n mch di dng s khi, cc tn hiu lin quan n khi chc nng gii nn
m thanh (thc s l cc IC) m bo cho mch hot ng.
1.2. S khi chc nng v nhim v ca mch gii m nn tn hiu m
thanh (MPEG - AUDIO Decoder):
1. 2 . 1 . S khi chc nng: (Hnh 1.2-1)

Hnh 2.1-1: S khi chc nng.

My VCD Player hin nay hu ht khi gii nn hnh v ting u tich hp
chung trn 1 IC gii nn m ng vo tn hiu ca n s nhn 3 tn hiu LRCK,
DATA, BKC m ta hay gi l Serial Bitstream . Trong DATA l chui d liu
chung cho c Video v Audio. Nhim v ca cc khi l:

DSP: Cp tn hiu LRCK, DATA, BCK cho mch gii m nn m thanh.

MPEG Audio Decoder: m nhn chc nng gii m nn tn hiu m

thanh. Sau khi gii nn n cho ra 3 tn hiu DATA, WS (Word Select hay
cn gi l LRCK) v BCK cp cho khi DAC.
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Audio DAC: m nhn chc nng chuyn i tn hiu s phn m thanh
gii nn t khi Audio MPEG DOCDER thnh tn hiu m thanh Analog
knh tri L v phi R.

1.3. Cc ng tn hiu giao tip chnh trn khi gii nn m thanh:

c ci nhn bao qut, tng th i vi mch MPEG Audio Decoder ni chung,
cng vi tnh phc tp ca mch v vi cng ngh cao ca mch tch hp, nn vn
nm vng hot ng ca mch phc v cho vic sa cha l ch yu, nn
chng ta cn thit nm r mi quan h, lin lc gia mch gii nn m thanh vi cc
mch chc nng khc trong my.
1.3.1. S khi giao tip:( Hnh 1.3-1).

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Hnh 1.3-1: Cc nhm tn hiu giao tip chnh trn khi gii nn m thanh.
1.3.2. Cc ng tn hiu giao tip chnh trn khi gii nn hnh:
Nhm tn hiu giao tip chung (global interface signals):
y l nhm tn hiu phc v chung cho ton b h thng trong
khi MPEG DECODER. Quyt nh trc tin mch MPEG DECODER c
hot ng hay khng. Bao gm cc tn hiu sau:
+ Tn hiu /RESET: Nhn tn hiu Reset t bn ngoi v c mc tch
cc thp (active LOW) t li trng thI cho cc mch s bn trong IC
khi mi cp ngun.
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+

Tn hiu SYSCLK (System Clock): Nhn xung Clock h thng t bn

ngoi vi tn s thng dng trong cc my VCD l 27Mhz hoc c tn s
khc tu tng hng sn xut.

Tn hiu PIO[10:0] (Programmable I/O): L cc tn hiu vo /ra lp trnh.

+ Cc chn ngun cp v t cho h thng (Power and Ground):

Bao gm cc chn ngun cp cho mch s v mch tng t bn
trong khi MPEG DECODER:
A- VDD v A-Vss: Chn cp ngun v t cho mch Analog. Thng 3.3
V hoc 5V.
D- VDD v D-Vss: Chn cp ngun v t cho mch Digital. Thng 3.3
V hoc 5V.

Nhm tn hiu giao tip vi vi x l ch (Host Interface signals):

y l nhm tn hiu iu khin t vi x l ch v tn hiu hi bo
lin lc v, m bo cho khi MPEG Decoder hot ng ng b, nhp
dng trong qu trnh thc hin giI nn tn hiu Video. Minh ho nh
(Hnh 1.3-2).

Hnh 1.3-2: Nhm tn hiu giao tip vi vi x l ch

+ Tn hiu Chn chip ( /CS): Chn nhn lnh chn chp ca vi x l
ch, khi mch Decode c dng thao tc c hoc ghi. Mc tch
cc l L.
+

Tn hiu HADDR(2:0) : Trng hp ghi c th nh HADDR (2:0)

ngha l c 3 tn hiu a ch do HOST ch nh tng ng Bus 3 bit
a ch ca vi x ch ch nh chn 1 trong 8 thanh ghi trong IC
Decode thuc khi Host interface Controller Logic.

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+

Tn hiu /RD (Read Strobe) : Tn hiu chn Mpeg Decoder cho vic
thc hin c hoc ghi. Trng hp ny, mc tch cc thp thc hin
c.

+ Tn hiu HDATA (7:0):

Trng hp ghi c th nh vy ngha l Bus 8-bit d liu 2 chiu giao
tip vi vi x ch (Host). Host ghi data n mch Mpeg Decoder theo nguyn
tc FIFO qua HDATA[7:0]. Host cng c v ghi vo cc thanh ghi bn trong
IC Decode v SDRAM/ROM ni qua HDATA[7:0].
Khi Mpeg Decoder cng gi cc d liu yu cu n Host thng qua
BUS ny.
+

Tn hiu /WAIT: Tn hiu bo i v HOST khi tn hiu CS tc ng

v tn hiu bo i xc nhn li khi khi Mpeg Decoder sn sng hon
thnh chu k truyn data. Mc tch cc thp L.

Tn hiu /INT (Interrupt request) : Tn hiu yu cu ngt gi n

HOST.

Tn hiu R/W (Read/ Write): Tn hiu cho php Mpeg Decoder c/

ghi Data ra Bus data. Read =H cho php c v Write = L cho php
ghi.

Nhm tn hiu giao tip vi khi CD (CD Interface):

y l ng vo tn hiu chung cho c ca khi MPEG Decoder
(Video & Audio) , c 4 ng tn hiu quan trng nht t khi CD-DSP m
ta phI quan tm. S khi minh ha nh (Hnh 1.3-3) sau:

Hnh 1.3-3: Nhm tn hiu giao tip vi khi CD

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+

Tn hiu CD-DATA: D liu CD thu t khi CD-DSP theo chui ni

tip (Serial).

CD-LRCK (CD Left Right Clock) : Cp t 16 bit ng b (Left

Right) cho khi giI m nn, v c cc tnh ring bit ( hoc mc cao
cho Left channel v ngc li cho Right channel).

CD-BCK (CD-Bit Clock): Xung ng b bit CD.

CD-C2PO: L tn hiu bo li data cho khi MPEG Decoder, khi c li

CD xut hin th CD-C2PO = H , khi MPEG Decoder s gi hnh nh
trc cho n khi c hnh nh k tip khng li.

Nhm tn hiu giao tip vi b nh (DRAM /ROM interface):

Tu theo thit k IC MPEG Decoder v HOST m giao tip vi

DRAM/ROM c cc tn hiu iu khin c phn khc nhau nhng c cu
trc chung nht l phI c cc tn hiu sau:
+

/CAS (Column Address Strobe): a ch ct nh (lu tr).

/RAS (Row Address Strobe): a ch hng nh (lu tr).

MADDR[20:0] (Memory address): a ch nh vi 20 bit a ch, tu

theo my m s bit a ch khc nhau (tu dung lng).

MDATA[15:0] (Memory Data Bus): D liu ca nh vi s bit l 16.

MWE (Memory Write Enable): Cho php ghi vo nh.

/ROM-CS ( Rom Chip Select): Tn hiu chn chip ROM c.

/SD-CAS ( SDRAM- Column Address Strobe): Tn hiu a ch ct

ca SDRAM.

/SD-RAS ( SDRAM- Row Address Strobe): Tn hiu a ch hng ca

SDRAM.

SD-CLK (SDRAM-Clock): Tn hiu xung CLK cp cho SDRAM.

/SD-CS[1 :0] (SDRAM-Chip Select): Tn hiu chn chip SDRAM

thc hin ghi/ c.

LDQM (Datainput/output mask):Tn hiu cho php lc (Mask) d liu vo/

ra.

/UDQM: Tn hiu khng cn lc (Mask) d liu vo/ ra.

1.3.3. Nhm tn hiu giao tip m thanh s (Digital Audio Interface):

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L cc tn hiu vo cp cho khi giI nn ting:
+ DAI_DATA: D liu PCM m thanh vo.
+ DAI_LRCK: Xung ng b PCM m thanh knh tri-phi.
+ DAI_BCK: Xung ng b bit PCM (ng b bit).
1.3.4. Nhm tn hiu giao tip m thanh (Audio Interface Signals):
L cc tn hiu ra cp cho khi DAC thc hin chuyn i m thanh s
sang tng t gm :
+ DA_DATA: D liu m thanh s ni tip ra sau khi giI m cp cho
khi DAC.
+ DA_LRCK: Xung ng b m thanh PCM knh tri-phi. Dng nhn
dng knh trI v knh phI ( tch knh).
+ DA_BCK: Xung ng b bit PCM c chia 8 t DA_XCK
+ DA_XCK: Xung ng h bn ngoi c s dng to ra DA_BCK v
DA_LRCK.
1.4. Khi chuyn i tn hiu m thanh dng s sang tng t (DAC):
1.4.1. S khi chc nng mch DAC trong my CD/VCD: (Hnh 1.4-1)

Hnh 1.4-1: S khi chc nng mch DAC trong my CD/VCD.

1.4.2. Nguyn l hot ng ca mch DAC:
+ Khi Serial Data Input:
Thc hin ng thi cc nhim v: Tch DATA knh L v R thnh 2 knh ring
bit - Chuyn i Data vo ni tip thnh song song.
Qu trnh thc hin tch knh c th hin thng qua dng sng nh (Hnh 1.41).

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Hnh 1.4-1: Biu dng sng thc hin tch knh L-R.
Trong :
BCK - ng vai tr l xung clock dch bit data.
LRCK- ng vai tr phn ng chn data knh tri v phi. Tng ng mc
logic 0/1.
ng vi LRCK= 1 cho qua cc Bit DATA ca knh L.
ng vi LRCK= 0 cho qua cc Bit DATA ca knh R.

Qu trnh chuyn i Data ni tip thnh song song c th dng nhiu cch:
V d :
- Dng b phn knh: Lc ny LRCK l tn hiu chuyn mch cho b phn knh L hoc
R v chuyn mch cho mch DAC ti ng vo v ra cn BCK l tn hiu dch data.
- Dng cc thanh ghi dch ni tip thnh song song: Lc ny BCK l tn hiu dch data.
LRCK l tn hiu iu khin mch cht v chuyn mch vo/ ra khi DAC.

+ Khi lc s (Digital Filter): C nhim v khI phc cc bit DATA mt cch

chnh xc hn.
+ Khi DAC: Sau khi c cc t m (cc bit song song) ca cc knh L, R
tng ng vi mt mc lng t, khi DAC thc hin chuyn i tn hiu
s sang tng t.
+ Cc OPAMP: ng vai tr nh phn t khuch i m. Tn hiu ra ca 2
OPAMP s a n 2 mch lc thng thp (LPF) khi phc li m thanh
tng t ca knh L v R.
II. T NGHIN CU TI LIU LIN QUAN V THO LUN NH

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1. c cc tI liu ca s dn trI my CD\VCD ca D n GD dy ngh trang
b ti xng thc hnh.
2. Tham kho sch Tm hng v sa cha u my CD, LD, DVD, CD_ROM,
VCD ca - K s Nguyn Minh Gip.
3. Tham kho sch My c a hnh v phng php chuyn i my CD sang
VCD ca K s Phm nh Bo.
4. Tho lun v t hc thuc cc thut ng vit tt v mch gii m nn tn hiu
hnh.
5. T nghin cu v tho lun s mch nguyn l mch gii m nn tn hiu
ting ca cc hng sn xut.
6. c v nghin cu cc s mch nguyn l mch gii m nn tn hiu ting
ca cc my thng dng.
7. Tp phn tch, tho lun v tm lc cc ng tn hiu lin quan n mch gii
m nn tn hiu hnh.

2.

III. THC TP TI XNG

Kho st v phn tch mch gii m nn tn hiu ting trn my CD/VCD thc t:
2. 1 . Cung cp ti liu lin quan n mch gii m nn tn hiu ting ca my ang thc
hnh ti xng: Bao gm.
S khi lin lc tng th gia mch gii m nn tn hiu ting vi cc khi chc
nng ca hng sn xut.
S mch in nguyn l ( Schematic Diagram) mch gii m nn tn hiu ting.
Bng tm tt cc thng s k thut quan trng do hng sn xut cung cp, hoc c
th hin ngay trn Schematic Diagram.
Cc ti liu h tr khc (nu c).
2.2. Hng dn thc hnh kho st v phn tch:
Gm cc bc sau:
Hng dn c v Phn tch S khi lin lc tng th gia khi gii m nn tn
hiu ting vi cc khi chc nng.
Hng dn c v Phn tch s mch nguyn l (Schematic Diagram).
Hng dn cch v s lin lc tm tt nh s khi chc nng phn u ca
bi ny. (nu khng c th so dung ngay ti liu s khi lin lc ca hng sn
xut).
Hng dn cch d mch in v cch o cc thng s in p v dng tn hiu
trn my so vi cc thng s chun trn Schematic ca my.

Sau y s gii thiu my VCD ca Hng JVC _MX-J770V minh ho cho cc bc

nu trn:
Cung cp ti liu:
Cho s lin lc tng th nh (Hnh 2.2-1)
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Cho s mch in nguyn l nh ( Hnh 2.2-2a ;2.2- 2b; 2.2-2c v 2.2-2d).
Cc thng s k thut c th hin ngay trn Schematic Diagram.

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Hnh 2.2-1: S lin lc tng th

Hnh 2.2-2a: S mch in nguyn l AUDIO MPEG Decoder

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Hnh 2.2-2b: S mch in nguyn l MPEG Decoder

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Hnh 2.2-2c: S mch in nguyn l MPEG Decoder

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Hnh 2.2-2d: S mch in nguyn l MPEG Decoder

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Hng dn c v Phn tch S khi lin lc tng th gia khi AUDIO MPEG
Decoder vi cc khi chc nng :
Cc Nhm tn hiu lin lc vi AUDIO MPEG Decoder gii thiu tng t nh
phn l thuyt. Sau y l bng tm tc cho IC ny hc sinh lm ti liu t tra
cu tham kho:
2. 2. 1 .

Symbol and
Pin No
Name
Description
I/O
Nhm tn hiu phc v cho h thng (thuc giao tip chung) (System Services)
Nhn tn hiu Reset t bn ngoi v c mc
tch cc thp (active LOW) t li trng
13
RESET
I
thI cho cc mch s bn trong IC khi mi
cp ngun, thi gian thit lp t nht l 20s.
178

190,174,156,153,
147,141,138,
133,129,52,1

SYSCLK

PIO[10:0]

Nhn xung Clock h thng t bn ngoi vi

tn s 27Mhz.

I/O

Cc chn vo/ ra lp trnh (Programmable I/O

pins).

Ngun cp v t (Power and Ground)

176

A- VDD

179

A- VSS

Analog
Ground

VDD

Power

Nhn ngun 3.3V cp cho phn mch logic

v cc cng I/O.

VSS

Ground

Chn Mass cho mch logic v cc cng I/O.

CS

Chn nhn lnh chn chp ca vi x l ch,

khi mch Decode c dng thao tc c
hoc ghi.

5,12,17,27,36,40,
47,55,61,65,
69,75,81,87,91,95
,101,107,113,
117,123,134,144,
149,160,168,
175,181,193,197
7,14,19,29,38,42,
49,57,63,67,
71,77,83,89,93,97
,103,109,115,
119,125,136,146,
151,162,170,
183,195,199

206

Analog
Power

Nhn ngun 3.3V cp cho phn mch analog

bn trong.

Chn Mass cho mch vng kho pha PLL.

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204-202

11-8,6,4-2

16

208

207

15

HADDR[2:0]

HDAT[7:0]

I/O

INT

O,OD

Bus 3 bit a ch ca vi x ch ch nh
chn 1 trong 8 thanh ghi trong IC Decode
thuc khi (Host interface Controller Logic)
Bus 8-bit d liu 2 chiu giao tip vi vi x
ch (Host).
Host ghi data n IC Decoder theo nguyn
tc FIFO qua HDATA[7:0].
Cc bit cao (MSB) ca t 32-bit c ghi
trc. Host cng c v ghi vo cc thanh ghi
bn trong IC Decode v SDRAM/ROM ni
qua HDAT[7:0].
Tn hiu ngt n Host . M lung tn hiu
(OD-Open drain signal), p khi ngt tng n
3.3Vol
Tn hiu chn Mpeg Video Decoder cho vic
thc hin c hoc ghi. Trng hp ny,
mc tch cc thp thc hin c.

/RD

R/W

WAIT

O,OD,PU

Read/write strobe in M mode. Write strobe in I

mode. Host asserts R/W LOW to select write
and LOW to select Read.
Active LOW to indicate host initiated transfer
is not complete.
WAIT is asserted after the falling edge of CS
and reasserted when decoder is ready to
complete transfer cycle. Open drain signal,
must be pulled-up to 3.3 volts. Driven high for
10 ns before tristate.

Giao tip vi khi CD (CD interface)

185

184
182
180

Tn hiu bo li data cho khi MPEG

Decoder, khi c li CD xut hin th CDC2PO = H , khi MPEG Decoder s gi
hnh nh trc cho n khi c hnh
nh k tip khng li.

CD-C2PO

CD-BCK

CD bit clock. Decoder accept multiple BCK

rates.

CD-LRCK

Programmable
polarity
16-bit
synchronization to the decoder
(right channel HIGH).

CD-DATA

word

Serial CD data.
Video Output

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157

HSYNC

I/O
Horizontal sync. The decoder begins
outputting pixel data for a new horizontal line
after the falling (active) edge of HSYNC.
horizontal line after the falling (active) edge of
HSYNC.

177

VCLK

155,154,152,150, VDATA[7:0]
148,145,143,
142

Video clock. Clocks out data on input.

VDATA[7:0]. Clock is typically 27 MHz.

Video data bus. Byte serial CbYCrY data

synchronous with VCLK.
At power-up, the decoder does not drive
VDATA. During boot-up,
the decoder uses configuration parameters to
drive or 3-state
VDATA.
I/O
Vertical sync. Bi-directional, the decoder
outputs the top border of a new field on the
first HSYNC after the falling edge of VSYNC.
VSYNC can accept vertical synchronization or
top/bottom field notification from an external
source. (VSYNC HIGH = bottom field.
VSYNC LOW = Top field)
SDRAM/EDO/ROM interface

158

VSYNC

92

EDO-CAS

Active LOW EDO DRAM column address

strobe.

94

EDO-RAS

Active LOW EDO DRAM Row address strobe.

79

LDQM

SDRAM LDQM.

Memory address.

I/O

Memory data.

SDRAM/EDO write enable. Decoder asserts

active LOW to request a write operation to the
SDRAM array.

127,126,124,122- MADDR[20:0]
120,118,116,
114,112110,108,106104,102,
100-98,96
78,76,74MDATA[15:0]
72,70,68,66,64,62
,6058,56,54,53
82
MWE

128

ROM-CS

O,OD,PU

ROM chip select. Open drain signal, must be

pulled-up to 3.3 volts.

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85

SD-CAS

Active LOW SDRAM column address.

84

SD-CLK

SDRAM system clock.

SD-CS[1 :0]

Active LOW SDRAM bank select.

86

SD-RAS

Active LOW S DRAM row address.

80

UDQM

SDRAM UDQM.

88,90

Audio interface
O
PCM bit clock. Divided by 8 from DA-XCK,
DA-BCK can be either
48 or 32 times the sampling clock.

167

DA-BCK

161

DA-DATA

166

DA-LRCK

169

DA-XCK

I/O

173

DAI-BCK

PCM input bit clock.

171

DAI-DATA

PCM input data, two channels. Serial audio

samples relative to DA-BCK clock, resulting in
downmixed audio output.

172

DAI-LRCK

PCM input left-right clock.

Serial audio samples relative to DA-BCK

clock.
PCM left-right clock. Identifies the channel for
each audio sample.
The polarity is programmable.
Audio external frequency clock. Used to
generate DA-BCK and DALRCK. DA-XCK can be either 384 or 256
times the sampling frequency.

2.2.2. Hng dn c v Phn tch s mch nguyn l (Schematic Diagram):

Trn c s s lin lc tng th gia cc khi chc nng ta bt u c v phn
tch s mch nguyn l ln lt theo tng nhm chc nng nh phn loi S
khi tng qut v s khi ca hng sn xut, t ta nhn bit cc khi chc nng
lin quan nh trnh by c th bng trn. T , ta s lm quen dn vi cu trc
ca mch giI m nn hnh v rn luyn c kh nng c v phn tch bt k mt
mch giI m nn hnh ca nhiu my VCD khc.

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2.2.3. Hng dn cch to s lin lc tm tt nh s khi chc nng phn u
ca bi ny. (nu khng c th s dng ngay ti liu s khi lin lc ca hng
sn xut):
Ban u khi mi lm quen ta nn t mnh v li s lin lc tm sau khi nm chc
cc k hiu chn (thut ng) v chc nng ca cc chn bng cch phin qua ting vit.
Sau khi quen thuc ta nn khai thc trc tip phn s khi lin lc ca hng sn xut
v ch lp li thao tc ny khi ta gp my khng c y ti liu.
V d:
Cho ti liu v my VCD thc t ang thc hnh.
Hc sinh t tm tc mch giI nn ca my mnh ang thc hnh trn c s ti liu v
my thc t. ( Xem nh l bi tp m hc sinh phI lm ).
V tm tc li cc nhm lin lc v c th ho cho cc chn.
So snh vi ti liu l thuyt hc.
2.2.4. Hng dn cch d mch in v cch o cc thng s in p v dng tn hiu
trn my so vi cc thng s chun trn Schematic ca my:
Cch d mch in: bng cch xc nh cc khi chc nng thng qua cc linh
kin d nhn bit, hoc thng qua m vng ca mch, hoc thng qua cc trm
lin lc nh trm dy lin lc vi bn phm, hoc lin lc vi IC nh, hoc
chnh m s ca IC. Sau khi xc nh vng mch, bo ,bo mch, ta ln lt d
mch theo tng nhm lin lc nh s khi tng qut.
Cch o cc thng s in p v dng tn hiu:
Da vo bng thng s ca hng hoc da vo chc nng ca cc chn
m ta bit n thuc loi Data, xung Clock, hay tn hiu logic, hay p DC m chn
dung c o l My hin sng hay VOM hoc DMM.
Khi o cn ch n bin , tn s, v nhiu i vi tn hiu l Data, xung
Clock. ln v nhiu i vi tn hiu logic, hay p DC.
Tu vo chc nng ca cc tn hiu m ta cn phI cho my hot ng cho
ph hp khi cn kim tra, thng thng cc thng s c o ch Play.
Ch nn kim tra cc im Test quan trng theo th t khi ghi vn h hng
do khi giI m nn hng:
Nhm tn hiu chung cho h thng.
Nhm tn hiu vo t khi CD-DSP.
Nhm tn hiu giao tip vi SDRAM/EPROM.
Nhm tn hiu giao tip vi HOST.
Trn c s l thuyt hc ta ln lt o cc thng s ti cc chn v cc
im TP theo Schematic ca my. nh mch trn c tt cc thng s cc
chn quan trng.
2.3. Tho lun cc hin tng h hng c bn c th xy ra ra theo nhm:
Gm cc hin sau:
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My c hnh bnh thng khng c ting ng ra.
My c hnh bnh thng c ting n.
Chn on, kim tra v sa cha mch gii nn tn hiu AUDIO:
Ta bit mch gii nn Video/ Audio thng c tch hp chung trn mt IC, v 2
phn ny c cc tn hiu chi phi chung cho c 2 phn. Ngha l, khi phn chung hng th c
hnh v ting u mt. Nh vy, khi hng thuc phn m thanh ta ch quan tm n phn ring
thuc phn m thanh m thi.
Ni cch khc, khi hng v phn m thanh ta cn quan tm n:
+ Cc ng vo giao tip m thanh (DAI_DATA; DAI_BCK; DAI_LRCK) v ng ra
3.

(DATA; BCK; LRCK; XCK) vi khi gii nn.

Ng iu khin MUTE m thanh.

Mch DAC.

Mch khuch i m thanh a ti ng ra v cc mch trn.

Sau y s l mt s hng dn v gi phn tch theo hin tng trn mt cch

bao qut, tu vo kt cu ca tng my c th m v tr kim tra cng nh mt s chc
nng m trn mi my s khc nhau.
3.1. My c hnh bnh thng khng c ting ng ra:
y l hin tng h hng ch c th lin quan n phn ring ca mch m thanh,
do c hnh nh bnh thng nn kh nng hng khi giI nn t xy ra. Do , ta ln lt
kim tra theo th t u tin bt u t ng ra m thanh tr v khi giI nn, tc l cc khi:
+ Ng iu khin v mch iu khin m thanh (MUTE m thanh, iu khin m
+

lng).
Mch khuch i m thanh a ti ng ra v cc mch trn.

Mch DAC .

Cui cng l mch gii nn m thanh.

Ta cn kim tra nhanh loi tr vng mch h hng trc khi i vo chi tit.
Thng thng hay hng cc mch t DAC cho n ng ra m thanh.
Trng hp nghi vn mch gii nn m thanh hng:
Ta ln lt kim tra cc tn hiu vo/ra khi gii nn m nh cp trn theo
thng s ca nh sn xut (Schematic).
Nu c dao ng XCK cp t bn ngoi vo ta cn phi kim tra mch ny hoc
ng tn hiu ny.
Cui cng ta thay th IC gii nn.
3.2. My c hnh bnh thng c ting n:
C ting n chng t t mch DAC cho n ng ra m thanh thng sut, th
chc hn ta tng m lng. Nu c tc dng chng t thng sut.

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Nu m thanh nh, nhiu th kh nng h hng hon ton thuc mch tng t, tc
t ng ra DAC n ng ra m thanh.
Trng hp ny, thc t gp l hng khi giI nn m thanh. Thay IC giI nn
my hot ng bnh thng.

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