Implementation of Dynamic Branch Prediction using

HDL
Advanced Computer Architecture Project Report
by

Surya Ganesh P (15VL17F)

Mahesh K (15VL14F)
Ankur Agrawal (15VL03F)
(M.Tech VLSI Design)
Under the guidance of

Dr. M S Bhat

Department of Electronics and Communication Engineering

National Institute of Technology Karnataka
16th November 2015

ABSTRACT
In high-performance computer systems, performance losses due to conditional branch
instruction can be minimized by predicting a branch outcome and fetching, decoding
and/or issuing subsequent instructions before the actual outcome is known. Dynamic
Branch prediction has become an area of interest due to its effect on the performance of
pipelined and super scalar processors. Various methods have been proposed to speculate
the path of an instruction stream after a branch. This project presents our evaluation of
the performance of two types of prediction strategies (One-bit, Two-bit) and architectures
with the goal of maximizing prediction accuracy.

Introduction

In this project attempts to cover various branching strategies which have been used by
various microprocessor designs. Various methods of predicting the direction of conditional
branches using Branch Target Buffer (BTB) have been developed. Different predictor
mechanisms take advantage of different observed patterns in branch behaviour. Pipelining is the major technique for improving the performance of machines. Branches cause
performance losses in pipelines by making the pipeline stall till the branch instruction is
evaluated. Branches comprise about 15-30total instructions. Stalling for evaluation of
the branch instruction increases with an increase in pipelining and causes performance
losses. Additionally as processors get wider with deeper pipelines branch prediction becomes critical since the relative cost of incorrect prediction increases. With increasing
pipeline depth, the number of instructions which have to be flushed out of the pipeline
increases and this increases the incorrect prediction cost. An accurate branch predictor
can substantially improve the performance of a machine by scheduling correct instructions in the pipeline after a conditional branch. The strategies are divided into two basic
categories; depending on whether or not past history was used for making a prediction.
Branch prediction strategies are thus divided in to static and dynamic prediction strategies. A static prediction strategy (Strategy 1) makes the same prediction every time a
branch instruction is encountered. A dynamic prediction strategy takes in to account
previous instruction execution history before predicting a branch.

Branch Target Buffer (BTB)

The BTB can be used to reduce the performance penalty of branches by predicting the
path of the branch and caching information about the branch. The BTB can cache up to
four types of information: a tag indentifying the branch the information corresponds to
(usually branch address), prediction information for predicting the path of the branch,
the branch target address and instruction bytes at the branch target address. As each
instruction is fetched from memory, the instruction address is used to index into the BTB.
If a valid BTB address is found for that address, then the instruction is a branch. The

Figure 1: Branch Target Buffer

branch path is then predicted by the branch?s prediction information. If the branch is
predicted as taken, the instructions cached in the BTB are supplied to the processor while
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if the branch is predicted as not taken, sequential execution continues. As the processor
finishes executing the branch, it checks to see if the BTB correctly predicted the branch.
The branch prediction information and branch target address are updated after every
branch.

Dynamic Branch Prediction

Figure 2: Dynamic Branch Prediction Mechanism

Prediction Mechanisms

Hear we are discussing mainly two types of Branch Prediction techniques One-bit and
Two-bit predictors

4.1

One-bit Prediction

A very basic dynamic predictor stores the result of a branch in a table; the next time
that branch is called, the result of the previous branch is used as the prediction. For a
predictor with 2n entries, the lowest n bits of the instruction address are used to address
the prediction table. In order to update the table after the result of the branch is known,
the lowest n bits of the instruction address are also forwarded along the pipeline .

Figure 3: One-bit prediction

4.2

Two-bit Prediction

While a one-bit predictor makes some advances over static prediction, some- times it
changes its prediction too quickly. One instruction might branch three times, then fail
to branch once, and then branch three more times. This is especially the case with
frequently-called loops. To fix this case, we widen the prediction table to two bits,
storing the prediction in the upper bit and the result of the previous branch in the lower
bit. The prediction only changes when the past two predictions are incorrect. This also
requires two additional bits - the state of the table at prediction time - to be forwarded
along the pipeline so that the table can be properly updated

Figure 4: Two-bit prediction

Simulation Results

Figure 5: Simulation results of 1-bit prediction

Figure 6: Simulation results of 2-bit prediction

.

Conclusion

Dynamic branch prediction implemented in Hardware level by using BTB with single-bit
and two-bit predictor mechanisms.