Addressing Modes

Addressing Modes involves

1) Address range and addressing flexibility
2) Number of memory references in the instruction and complexity of address
calculation.

Types of Addressing Modes

Immediate
Memory Reference
Direct
Indirect
Register Reference
Register
Register Indirect
Displacement
Indexed
Base
Relative
Stack

1) Immediate Addressing

Operand is part of instruction

Operand = address field
e.g. ADD 5
Add 5 to contents of accumulator
5 is operand
No memory reference to fetch data
Fast
Limited range

2) Direct Addressing

Address field contains address of operand

Effective address (EA) = address field (A)
e.g. ADD A
Add contents of cell A to accumulator
Look in memory at address A for operand
Single memory reference to access data
No additional calculations to work out effective address
Limited address space

3) Indirect Addressing

Memory cell pointed to by address field contains the address of (pointer to) the
operand
EA = (A)
Look in A, find address (A) and look there for operand
e.g. ADD (A)
Add contents of cell pointed to by contents of A to accumulator
Large address space
2n where n = word length
May be nested, multilevel, cascaded
e.g. EA = (((A)))
Draw the diagram yourself
Multiple memory accesses to find operand
Hence slower

4) Register Addressing

Operand is held in register named in address filed

EA = R
Limited number of registers
Very small address field needed
- Shorter instructions
- Faster instruction fetch
No memory access
Very fast execution
Very limited address space
Multiple registers helps performance
Requires good assembly programming or compiler writing
C programming
register int a;

5)

Register Indirect Addressing

6)

Similar to indirect addressing

EA = (R)
Operand is in memory cell pointed to by contents of register R
Large address space (2n)
One fewer memory access than indirect addressing

Displacement Addressing

EA = A + (R)
Address field hold two values
i. A = base value
ii. R = register that holds displacement
iii. or vice versa

Indexed Addressing

A = base

R = displacement

EA = A + R

Good for accessing arrays

Ex: LDAC 5(X)

Assume that the index registers holds the value 12. Then the instruction reads the
data from the location 5+12=17 and stores it in the Accumulator.

Base Addressing
Same as indexed mode except that indexed register is replaced with base address
register.
Relative Addressing

A version of displacement addressing

R = Program counter, PC

EA = A + (PC)

i.e. get operand from A cells from current location pointed to by PC

Ex: LDAC $5
Assumes that this instruction is locked at memory location 9 and it takes up two
memory locations where the next instruction is at location 12. Then the instruction
reads data from location 5+12=17 and stores it in the Accumulator.

7) Stack Addressing:

The operand is implied as top of the stack.

It uses the CPU register called Stack Pointer which points to the top of the stack i.e.

the memory location where the last value pushed.

Stack provides either indirect addressing or indexed addressing. The specified
operand is found at the top of stack.

Interrupts

Improve the processing efficiency of a processor because when the processor

interacts with most of the external devices.

Interrupts force the operating system to deal with the unexpected activities of
running programs.

An interrupt is assumed as an emergency signal which is serviced by the

microprocessor as soon as possible. When the microprocessor receives the
interrupt signal, it suspends or terminates the currently executing instructions and
jumps to an interrupt service routine (ISR) to respond to the incoming interrupt.
Definition:
An interrupt is a control signal that forces the CPU to suspend the
execution of its present sequence of instructions and transfer to another
sequence of instructions and when the execution of these instructions is
finished, the original sequence of instructions is resumed.
Or

When a Process is executed by the CPU and when a user Request for another
Process then this will create disturbance for the Running Process. This is also called as
the Interrupt.
The sequence of events is usually like this:
1. Hardware signals an interrupt to the processor
2. The processor notices the interrupt and suspends the currently running Program
3. The processor jumps to the matching interrupt handler function in the OS
4. The interrupt handler runs its course and returns from the interrupt
5. The processor resumes where it left off in the previously running software
Types of Interrupt:
1) Internal Interrupt (Exception)
2) Hardware Interrupt.
3) Software Interrupt.

1)

Internal Interrupt (Exception)

The Internal Interrupts are those which are occurred due to Some Problem in the
Execution

For Example When a user performing any Operation which contains any Error and
which contains any type of Error. So that Internal Interrupts are those which are
occurred by the Some Operations or by Some Instructions and the Operations
those are not Possible but a user is trying for that Operation
Two Sources:
1) Processor- Detected Exception
These types of exception are generated when the CPU encounters an error while
attempting to execute an instruction. These errors do not allow the process to be
executed.
Reasons:
1) Faults ( Debugging) Correctable
2) Traps ( Addressing Error) Debugged
3) Aborts ( Arithmetic error, hardware failure , CPU send the appropriate signal to
kill that process)
2) Programmed exception:
These types of exception occur when the programmer makes logic or syntactical
mistakes. It would be illegal to execute the instruction.
Ex:
1) Reading from an unavailable memory unit
2) Detected before incrementing the IP
3) Executing a privileged Instruction
2) Hardware Interrupt (External Interrupt)
The External Interrupt occurs when any Input and Output Device request for any
Operation and the CPU will Execute that instructions first For Example When a
Program is executed and when we move the Mouse on the Screen then the CPU
will handle this External interrupt first and after that he will resume with his
Operation
I/O devices tell the CPU that an I/O request has completed by sending
an interrupt signal to the processor.
I/O errors may also generate an interrupt.
Most computers have a timer which interrupts the CPU every so many interrupts
the CPU every so many milliseconds

Maskable Interrupt: These interrupts are block (does not recognize) able like
Disk, Clock and Network interrupts unless the interrupt enable Flag is Set.
Non-maskable Interrupts: These interrupts are non-block (Recognize) able like
power failure, bus time out etc.
3)

Software Interrupt:

This is generated by executing an instruction.

It is special call instruction that behaves as an interrupt rather than a

subroutine call.

The interrupt calling program must pass information to the operating

system in order to specify the particular task requested.

Instruction Execution Cycle

It is a procedure through which the CPU goes through to execute an instruction.
First of all both the data and the program that acts upon that data are loaded into main
memory. The CPU is now ready to do some work.
1) Fetch : ( Gets Instruction)
The first step the CPU carries out is to fetch some data and instruction (Program)
from main memory then stores them in its own internal memory areas called
Registers. This is called fetch part of the cycle.
Following registers to implement the fetch operation
1) MAR: Specifies the address in the memory for read/write operation.
2) MDR: It contains the value to be stored in the memory
3) PC: Holds the address to the next instruction to be fetched.
4) IR: Holds the last instruction fetched.
Eg:

This is one cycle

1) MARPC
2) MDRMemory
3) PCPC+1
4) IRMDR

2) Decode (Decode the instruction)

The next step is for the CPU to make sense of the instruction it has just
finished.

This process is called Decode

The CPU is designed to understand a specific set of commands. These are

called the Instruction set of the CPU.

The CPU Decodes the instruction and prepares various areas within the chip
in readiness of the next step

3) Execute ( Run the instruction):

This is the part of the cycle when data processing actually takes place.
The instruction is carried out upon the data (executed).
The result of this processing is stored in yet another register (AC)

Start

Fetch
Next
Instructio

Decode
Instructio
n

Execute
Instructio
n

Fig. Instruction Cycle

Stop

Control Unit:

The control unit of CPU is used to supervise the operations of the processor.
It builds connections (Coordinates) between various components of the computer
system.
Coordinates the movement of data to and from IO devices, memory units and
registers.
The CU operates according to the program stored by receiving and executing its
instructions one at a time.
Inputs to CU
1) Clock Signal
2) Instruction Register
3) Flag
4) Control Bus
Outputs of CU
1) It causes data movement and activates some specific functions within the CPU.
2) Sends control signals to memory and IO modules via control bus.
Types of Control Unit
Hardwired Control Unit
It uses flags, decoder, logic gates and

Micro-programmed Control Unit

It uses sequence of micro-instruction in

other digital circuits.

it is a hardware control unit.

micro programming language.

It is mid-way between Hardware and

On the basis of input Signal output is

Software.
It generates a set of control signal on the

generated.
Difficult to design, test and implement
Inflexible to modify.
Faster mode of operation
Expensive and high error
Used in RISC processor

basis of control line.

Easy to design, test and implement.
Flexible to modify.
Slower mode of operation
Cheaper and less error.
Used in CISC processor.

Advantages of hardwired control unit:

1. Faster than micro- programmed control unit.
2. Can be optimized to produce fast mode of operation.
Disadvantages of hardwired control Unit:
1. Instruction set control logic are directly
2. Require change in wiring if designed has to be controlled.

Advantages of micro-programmed control unit:

1. Simplifies design of CU.
2. Cheaper
3. Less error prone to implement.
Disadvantage of micro-programmed control unit:
1. Slower compared to hardwired control unit.

RISC and CISC

RISC and CISC are the two different types of processor architectures. RISC stands for
Reduced Instruction Set Computer and CISC stands for Complex Instruction Set
Computer.
Comparing Factor

RISC

CISC

Reduced Instruction Set

Complex Instruction Set

Computers

Computers

Complexity

Smaller instruction

Larger Instruction

Operating Speed

Faster

Slower

Fixed Length

Every instruction has the same

Its not necessary to have the

Instructions

size

same size

Acronym

Allow register to register

Addressing Modes

addressing modes that can be

processes quickly
Depends on Hardware because

Dependency

it uses machine level language

Instructions.

Clock Signals

Allow Memory to Memory

Addressing Modes

Depends on Software because it

uses assembly level language

Needs one clock cycle per

Need multiple clock cycles per

instruction

instruction

Large number of

Uses the extra space for

Registers

additional registers

Compiler Design

Easy to design

Hard to Design

Code Size

High in code size

Less in code size

Instruction length

Single word instruction

Variable length instruction

Lot of work to translate (HLL to

Little work to translate (HLL to

MLL)

ALL)

Executes one instruction per

Multiple instructions are

clock cycle. ( fetched-decode-

executed simultaneously in one

execute)

Cycle.

Pipelining

Pipelining is the major feature

Doesnt support pipelining

Now days, Use

Less use

Maximum Use

Optimizing Compiler

Instruction

Uses for control logic

Summary:

CISC instructions utilize more cycles than RISC

CISC has way more complex instructions than RISC
CISC typically has fewer instructions than RISC
CISC implementations tend to be slower than RISC implementations
Computers typically use CISC while tablets, smartphones and other
devices use RISC

Pipelining:

Mostly used in RISC Computers.

Fetching instructions from memory takes long time which is major problem of
instruction execution speed.

Pipelining is an advance concept than pre-fetching since pipelining divides the

instruction execution into many parts and each part is handled by different
hardware and all of them can run in parallel.

It is more useful of wastage of time in fetching from the memory and thus
improves the system performance.