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Topic 9 - Understanding LDO Dropout
Topic 9 - Understanding LDO Dropout
VOUT
Gate
Drive
VIN
Gate
Drive
VOUT
5V
(1)
VIN
VOUT
3.3 V
Pass Element
Error Amplifier
+
Load
Gate
Drive
+
VREF
Sa
tur
atio
nL
ine
1.0
LDO's Programmed
Current Limit
VGS = 3.5 V
VGS = 3.0 V
0.5
VGS = 2.5 V
0
0
0.5
1.0
1.5
VDS = VIN - VOUT (V)
2.0
9-3
SC-70
RDS(on) - FET Drain-to-Source Resistance -
10.0
(3)
SOT-23
1.0
MSOP-8
SOT-223
PWP-20
0.1
0
10
20
Size - mm2
30
40
Dropout voltage(2)
(VIN = V OUT(nom) 0.1 V)
TEST CONDITIONS
IOUT 200 mA
IOUT 200 mA
IOUT 200 mA
IOUT 200 mA
IOUT 200 mA
Min
Typ
120
120
112
102
77
Max
200
200
200
180
125
Units
Typ
155
155
145
Max
210
210
200
Units
mV
Dropout voltage
(VIN = V OUT(nom) 0.1 V)
TPS79428
TPS79430
TPS79433
TEST CONDITIONS
IOUT 250 mA
IOUT 250 mA
IOUT 250 mA
9-4
Min
mV
110
100
IOUT = 200 mA
90
VDD - Dropout Voltage - mV
(4)
80
70
60
50
40
30
20
10
0
2.5
3.0
3.5
6.5
7.0
40
35
30
25
20
15
10
5
0
0
0.4
0.8
1.2
VDS = VIN - VOUT (V)
1.6
2.0
CONCLUSION
In summary, LDO dropout is rarely specified
for a designers specific operating conditions.
The actual dropout is easily determined by
interpolating the available datasheet information.
LDO dropout is influenced by FET size and input
voltage, and LDOs entering dropout affect circuit
performance. Once a designer understands this
information, he can select an LDO that is
optimized for his specific circuit requirements.
9-6