Computer Organisation

COMPUTER ORGANISATION
Que : 1 . Cached and interleaved memories are ways of speeding up memory access
between CPU' s and slower RAM.
Which memory models are best suited (i.e. improves the performance most) for which
programs ?
i) Cached memory is best suited for small loops.
ii) Interleaved memory is best suited for small loops
iii) Interleaved memory is best suited for large sequential code.
iv) Cached memory is best suited for large sequential code.(J-2012)

1.

(i) and (ii) are true.

2.

(i) and (iii) are true.

3.

(iv) and (ii) are true.

4.

(iv) and (iii) are true.

Please Select Ans Options .

Explanation
Option 2 is Correct Answer.
Comapred to the processor speed , the speed of the primary memory is slow. Cache memory
is small memory which ists in between the processor and primary memory and fetches
information to the processor at a much higher speed or it makes it appear so, Caching can be
effective based on a property of computer programs called locality of reference. Analysis of
program show that the majority of the execution time is spent around a small part of the
program may be a simple loop, nested loop or a few functions. The rest of the program is
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accessed infrequently . There is something called temporal licality and spatial licality also
which we need to know when we talk about cache. But cache memory is ideally suited for
small loops.

Interleaved memory is a technique for increaseing the speed of RAM. Here multiple memory
chips are grouped together to form what are known as banks . Each of them take turns for
supplying data . An interleaved memory with n banks is said to be n-way interleaved.
Macintose systems are considered to be one using memory interleaving.

Que : 2 . Interrupts which are initiated by an instruction are (J-2012)

1.

Internal

2.

External

3.

Hardware

4.

Software

Please Select Ans Options .

Explanation
Option 4 is Correct Answer.
Software interrupts are program instructions.
When a software interrupt instruction is executed, the processor executes and interrupt
Service Routine (ISR) stored in the vector address of that software interrupt instruction.
The software interrupts of 8085 are RST0, RST1,.......RST7.
The software interrupts of 8085 are vectored interrupts. software Interrupts cannot be marked
or be disabled.
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Que : 3 . A complete microcomputer system consists of (J-2012)

1.

Microprocessor

2.

Memory

3.

Peripheral equipment

4.

All of the above

Please Select Ans Options .

Explanation
Option 4 is Correct Answer.
A complete micro computer system consists of Microprocessor, Memory and peripheral
equipment.

Que : 4 . Where does a computer add and compare data ? (J-2012)

1.

Hard disk

2.

Floppy disk

3.

CPU chip

4.

Memory chip

Please Select Ans Options .

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Explanation
Option 3 is Correct Answer.
Every things computer does, is controlled by its Central Processing Unit (CPU).
The CPU is the brain of the Computer.
Sometimes refereed to simply as the Central processor.
In terms of computing power , the CPU is the most important element of a computer system.
It add and compare its data in CPU chip.
A CPU or processors of all computers, weather micro, mini or mainframe must have three
element or parts primary storage, arithmetic logic Unit (ALU), and Control Unit(CU) -decodes
the program instruction.

Que : 5 . Pipelining strategy is called implement (J-2012)

1.

instruction execution

2.

instruction prefetch

3.

instruction decoding

4.

instruction manipulation

Please Select Ans Options .

Explanation
Option 2 is Correct Answer.
Pipelining is a technique to build fast processors.
It allows the execution of multiple instruction by overlapping them.
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In an assembly unit every stage has one and only one activity to do.
It keeps repeating them again and again.
In the same way in a instruction pipeline at every instruction has multiple stages.
Say at the first clock cycle first step of instruction 1 is performed.
At the second clock cycle the second step of instruction 1 and 1st step of the instruction 2
would be performed and so on.
so pipelining is called instruction prefetch.

Que : 6 . Identify the addressing modes of below instructions and match them :

a) ADI

1) Immediate addressing

b) STA

2) Direct addressing

c) CMA

3) Implied addressing

d) SUB

4) Register addressing

1.

1234

2.

2143

3.

3214

4.

4321

(J-2012 III)

Please Select Ans Options .

Explanation
Option 1 is Correct Answer.
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The Instruction ADI adds some content to the accumlator.
It is an immediate addressing mode instruction.
The STA instruction stores the contents of the accumulator in the particular memory location
specified as operand.
CMA instruction takes complement of the contents of the accumulator.
SUB instructions substract the content of the register to the contents of the accumulator.

Que : 7 . If an instruction takes 's' microseconds and a page fault takes an additional 'j'
microseconds. The effective instruction time, if on the average a page fault occurs every k
instructions, is (J-2012 III)

1.

i + j/k

2.

i+j*k

3.

(i + j)/k

4.

(i + j) * k

Please Select Ans Options .

Explanation
Option 1 is Correct Answer.

Que : 8 . A CPU generally handles an interrupt by executing an interrupt service routine (J2012 III)

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1.

as soon as an interrupt is raised

2.

by checking the interrupt register at the end of fetch cycle

3.
instruction
4.

by checking the interrupt register after finishing the executing the current
by checking the interrupt register at fixed time intervals

Please Select Ans Options .

Explanation
Option 3 is Correct Answer.
An interrupt is a signal generated by some event external to the CPU, which causes the CPU
to stop what it is doing and jump to a separate piece of code designed by the programmer to
deal with the event which generate the interrupt request.
This interrupt handling code is often called an ISR(interrupt service routine).
When the ISR is finished, it returns to the code that was running prior to the interrupt,
which then resumes running with no awareness that it has been pre-empted by the interrupt
code

Que : 9 . Identify the devices given below with their IC numbers :

i) USART
ii) Micro controller

a) 8251
b) 8051

iii) Interrupt controller c) 8259

iv) DMA controller

d) 8257

(J-2012 III)

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1.

a) i b) ii c) iii d) iv

2.

a) ii b) i c) iv d) iii

3.

a) iii b) iv c) i d) ii

4.

a) iv b) i c) ii d) iii

Please Select Ans Options .

Explanation
Option 1 is Correct Answer.
The 8251 is a Universal Synchronous/Asynchronous Receiver/Transmitter packaged in a 28pin DIP made by Intel.
It is typically used for serial communication and was rated for 19.2 kilobits per second
signalling rate.
It is commonly confused with the much more common 8250 UART that was made popular as
the serial port in the IBM Personal Computer. The 8051 is the name of a big family of
microcontrollers.
The Intel MCS-51 (commonly termed 8051) is an internally Harvard architecture, complex
instruction set computing (CISC) instruction set, single chip microcontroller (C) series
developed by Intel in 1980 for use in embedded systems.
The Intel 8259 is a Programmable Interrupt Controller (PIC) designed for the Intel 8085 and
Intel 8086 microprocessors.
The initial part was 8259, a later A suffix version was upward compatible and usable with the
8086 or 8088 processor.
The 8259 combines multiple interrupt input sources into a single interrupt output to the host
microprocessor, extending the interrupt levels available in a system beyond the one or two
levels found on the processor chip. The 8259A was the interrupt controller for the ISA bus in
the original IBM PC and IBM PC AT.
The Direct Memory Access or DMA mode of data transfer is the fastest amongst all the
modes of data transfer. In this mode, the device may transfer data directly to/from memory
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without any interference from the CPU. The device requests the CPU (through a DMA
controller) to hold its data, address and control bus, so that the device may transfer data
directly to/from memory. The DMA data transfer is initiated only after receiving HLDA signal
from the CPU. Intels 8257 is a four channel DMA controller designed to be interfaced with
their family of microprocessors.
The 8257, on behalf of the devices, requests the CPU for bus access using local bus request
input i.e. HOLD in minimum mode.
In maximum mode of the microprocessor RQ/GT pin is used as bus request input.

Que : 10 . Suppose that a given application is run on a 64-processor machine and that 70
percent of the application can be parallelized. Then the expected performance improvement
using Amdahls law is(J-2012 III)

1.

4.22

2.

3.22

3.

3.32

4.

3.52

Please Select Ans Options .

Explanation
Option 2 is Correct Answer.
S(N) = 1/(1-P)+P/N
where P = portion of parallel
N= no.of.processor :
= 1/(1-0.7)+(0.7/64)
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= 1/0.3 + 0.0109375
= 1/0.31093
= 3.215
= 3.22

Que : 11 . In which addressing mode, the effective address of the operand is generated by
adding a constant value to the contents of register?(D-2012 II)

1.

Absolute

2.

Indirect

3.

Immediate

4.

Index

Please Select Ans Options .

Explanation
Option 4 is Correct Answer.
Index mode : The address of the operand is obtained by adding to the contents of the general
register called (index register) a constant value.
The number of the index register and the constant value are included in the instruction code.
Index Mode is used to access an array whose elements are in successive memory locations.
The content of the instruction code, represents the staring address of the array and the value
of the index register, and the index value of the current element.
By incrementing or decrementing index register different element of the array can be
accessed.
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Que : 12 . The efficiency (E) and speed up (sp) for Multiprocessor with p processors satisfies :
(D 2012 III)

1.

E P and sp P

2.

E 1 and sp P

3.

E and sp 1

4.

E 1 and sp 1

Please Select Ans Options .

Explanation
Option 2 is Correct Answer.
The efficiency is less than to 1 and speed up is less than equal to number of processors.

Que : 13 . Which of the following flags are set when 'JMP' instruction is executed ? (D-2012
III)

1.

SF and CF

2.

AF and CF

3.

All flags

4.

No flag is set
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Please Select Ans Options .
Explanation
Option 4 is Correct Answer.
JMP instruction executed the noflag is set.

Que : 14 . In an enhancement of a CPU design,

the speed of a floating point unit has been increased by 20%
and the speed of a fixed point unit has been increased by 10%.
What is the overall speed achieved if the ratio of the number of floating point operations to the
number of fixed point operations is 2:3 and the floating point operation used to take twice the
time taken by the fixed point operation in original design ? (D-2012 III)

1.

1.62

2.

1.55

3.

1.85

4.

1.285

Please Select Ans Options .

Explanation
No one Option is Correct Answer.
Speed up = Original time taken / new time taken
We assume x is the time for a fixed point operation.
Original time taken = (3x + 2*2x)/5 = 7x/5
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New time taken = ((3x/1.1) + (4x/1.2))/5 = 8x/(1.32 * 5)
So, speed up = (7 * 1.32)/8 = 1.155

Let say the total no. of instructions to be executed is 100

By the ratio of 2:3
Floating point instructions N(Ft): 40
Fixed point instruction N(Fd): 60
Before scenario
Time taken to process a floating point instruction T(Ft):2 units
Time taken to process a fixed point instruction T(Fd): 1 unit
Total time to execute T(B)=N(Ft) * T(Ft) + N(Fd) * T(Fd)=40*2+60*1=140 units
After scenario
When speed of floating point processing is increased by 20% means time to execute a
floating instruction in reduced by 20%.
Before T(Ft) was 2 units
Now time taken to process a floating point instruction T(Ft):2 - 20% of 2 =1.6 units (After)
Similarly speed of fixed point processing is increased by 10% hence
Before T(Fd) was 1 units
Now time taken to process a fixed point instruction T(Fd): 1 - 10% of 1=0.9 units
(After) Total time to execute T(A)= 40*1.6+60*0.9=118units
So Speed up gained is T(B)/T(A) =140/118=1.186 (approx)

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Que : 15 . Suppose a processor does not have any stack pointer registers, which of the
following statements is true ? (D-2012 III)

1.

It cannot have subroutine call instruction.

2.

It can have subroutine call instruction

3.

Interrupts are not possible.

4.

All subroutine calls and interrupts are possible.

Please Select Ans Options .

Explanation
Option 1 is Correct Answer but UGC declared marks to all
Stack pointer register hold the address of top of stack, which is the location of memory at
which CPU should resume its execution after servicing some interrupt or subroutine call.
So if SP register is not available then no subroutine call instructions are possible.

Que : 16 . Which one of the following is not an addressing mode? (J-2013 III)

1.

Register indirect

2.

Auto increment

3.

Relative indexed

4.

Immediate operand
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Please Select Ans Options .
Explanation
Option 3 is Correct Answer.
1) Immediate Mode
The operand is an immediate value is stored explicitly in the instruction: Example: SPIM
( opcode dest, source)
2) Index Mode
The address of the operand is obtained by adding to the contents of the general register
(called index register) a constant value. The number of the index register and the constant
value are included in the instruction code.
3) Indirect Mode
The effective address of the operand is the contents of a register or main memory location,
location whose address appears in the instruction.
Indirection is noted by placing the name of the register or the memory address given in the
instruction in parentheses.
The register or memory location that contains the address of the operand is a pointer.
4) Absolute (Direct) Mode
The address of the operand is embedded in the instruction code.
5) Register Mode
The name (the number) of the CPU register is embedded in the instruction. The register
contains the value of the operand. The number of bits used to specify the register depends on
the total number of registers from the processor set.
6) Displacement Mode
Similar to index mode, except instead of a index register a base register will be used. Base
register contains a pointer to a memory location. An integer (constant) is also referred to as a
displacement.

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The address of the operand is obtained by adding the contents of the base register plus the
constant.
The difference between index mode and displacement mode is in the number of bits used to
represent the constant. When the constant is represented a number of bits to access the
memory, then we have index mode. Index mode is more appropriate for array accessing;
displacement mode is more appropriate for structure (records) accessing.
7) Autoincrement /Autodecrement Mode
A special case of indirect register mode. The register whose number is included in the
instruction code, contains the address of the operand. Autoincrement Mode = after operand
addressing , the contents of the register is incremented. Decrement Mode = before operand
addressing, the contents of the register is decrement.

Que : 17 . Computers can have instruction formats with (J-2013 III)

1.

only two address and three address instructions

2.

only one address and two address instructions

3.

only one address, two address and three address instructions

4.

zero address, one address, two address and three address instructions

Please Select Ans Options .

Explanation
Option 4 is Correct Answer.
Computers can have instruction formats with zero address, one address, two address and
three address instruction.

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Que : 18 . Which is not a typical program control instruction? (J-2013 III)

1.

BR

2.

JMP

3.

SHL

4.

TST

Please Select Ans Options .

Explanation
Option 3 is Correct Answer.
SHL is not a contorl instruction. SHL means shift left
while BR is for branch.
JMP is for jump instruction and
TST is for testing a condition.

Que : 19 . Interrupt which arises from illegal or erroneous use of an instruction or data is (J2013 III)

1.

Software interrupt

2.

Internal interrupt

3.

External interrupt
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4.

All of the above

Please Select Ans Options .

Explanation
Option 2 is Correct Answer.
Interrupt which arises form illegal or erroneous use of an instruction or data is due to internal
interrupt.
An internal interrupt is a specific type of interrupt that is caused by instructions embedded in
the execution instructions of a program or process.
Typically, internal interrupts resist changes by users, and happen "naturally" or "automatically"
as a processor works through program instructions, rather than being caused by external
events or network connections.

Que : 20 . ______ refers to the discrepancy among a computed, observed or measured value
and the true specified or theoretically correct values. (Sep-2013)

1.

Fault

2.

Failure

3.

Defect

4.

Error

Please Select Ans Options .

Explanation
Option 4 is Correct Answer.
An error (from the Latin error, meaning "wandering") is an action which is inaccurate or
incorrect.
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In some usages, an error is synonymous with a mistake, though in technical contexts the two
are often distinguished.
For instance, in statistics "error" refers to the difference between the value which has been
computed and the correct value.
In statistics, an error (or residual) is not a "mistake" but rather a difference between a
computed, estimated, or measured value and the accepted true, specified, or theoretically
correct value.

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