Front End VLSI design using FPGA

28th April - 03rd May 2014

ORGANIZED BY Department of Electronics & Communication Engineering & Department of Applied
Electronics & Instrumentation

OBJECTIVE
Nothing touches and changes our era of exponential growth more than the digital VLSI. In few decades these
systems have grown (or shrunk) from a few transistors per device to well over a billion on a single chip. This
unprecedented growth in technology has led to entirely new design techniques where traditional schematic
designs have been replaced with Hardware Description Languages (HDLs) that look like computer code, but
are actually descriptions of hardware. These languages are used to design nearly all modern electronics from
microprocessors to controllers, and a host of other circuits.
The goal this Hands-on-training is to promote further the learning, discussion, and teamwork along with the
conception and development of exciting new ideas. The Workshop is designed to take a person from no
knowledge of VHDL, simulation, synthesis to a level of basic VLSI design competence.

Course Content
1. VHDL overview and Basics
2. VHDL Synthesis,
3. Combinational Design,
4. Sequential Design,
5. FSM,
6. IP Cores
7. Power measurement Tools
8. Chip Debugging Tools
9. Implementing the design into FPGA.

REGISTRATION DETAILS
Registration is mandatory for participants
1. For Students : Rs.2000/2. For Faculty : Rs.3500/3. For Industry : Rs.4500/4. Amount includes registration kit, e-material, tea & snacks during break.
5. Send your registration request to sushanta.pattnaik@silicon.ac.in

6. Registration fees can be deposited on the spot. However registration should be done in advance by mail
or through online process
For further details contact
Prof. Sushant Pattnaik, Course Coordinator, Contact No. 9437082906
Electronics & Communication Engineering Department
Silicon Institute of Technology
Silicon Hills, Patia, Bhubaneswar- 751024
Ph. No.: (0674) 2725448 Extn. 216/ 218
Website: www.silicon.ac.in