library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity OrExclusiva1 is
Port ( A,B : in BIT;
X : out BIT);--DECLARACION DE LAS VARIABLES
end OrExclusiva1;

architecture Behavioral of OrExclusiva1 is

begin
X <= (A NOR B) NOR (NOT (A NAND B));

end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity OrExclusiva2 is
Port ( A : in BIT;
B : in BIT;
X : out BIT);--DECLARACION DE LAS VARIABLES
end OrExclusiva2;

architecture Behavioral of OrExclusiva2 is

begin
X <= NOT((NOT((NOT A) NAND B))NOR(NOT(A NAND (NOT B))));

end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity OrExclusiva3 is
Port ( A,B : in BIT;
S,C : out BIT);
end OrExclusiva3;

architecture Behavioral of OrExclusiva3 is

begin
S <= A XOR B;
C <= NOT(A NAND B);

end Behavioral;
---------------------------------------------------------------------------------library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity MedioSubstractor is
Port ( A : in BIT;
B : in BIT;
X : out BIT;

P : out BIT);
end MedioSubstractor;

architecture Behavioral of MedioSubstractor is

begin

X <= A XNOR B;
P <= ((A NAND '0')NAND B)NAND '0';

end Behavioral;