DIGITAL TECHNIQUES oat OBJECTIVE TYPE QUESTIONS 1, The circuit given below is functionally equivalent to A > _ 8 a J (a) OR gate (0) NOR gate (c) AND gate (d) NAND gate 2. The circuit given below is functionally equivalent to (a) EX-OR gate (© inhibit gate (6) comparator (@ NAND gate 3. The cireuit given below is functionally equivalent to Ae: ‘ 8 (@) EX-ORgate (©) AND gate () NOR gate (d) NAND gate 4, Half-adder is also known as (a) AND circuit (c) NORcircuit 5. Which of the following is a universal gate ? (@) AND () OR (c) EXOR (d) NAND 6. Logic 1 in positive logic system is represented by (@ zero level (6) lower voltage level . (©) higher voltage level (d) negative voltage () NAND circuit (@ EX-OR circuit 10. Which of the following statements is true ? @ A+ AB =A () A(A+B) =AB (©) AB+ AB =A (d) CA+ CAB =CA+CB An AND cireuit @ (®) gives an output when all input signals are present simultaneously (©) isa negative OR circuit @) isa linear circuit is a memory circuit The following symbol represents a > (q@) inverter (b) buffer (c) schmitt trigger (d) flip-flop Which of the following symbols represents a buffer? @) () (c) @ >442 11, An alternative way of showing a two input NOR (a) 23> “=> Ww [ ye 12, An alternative symbol for two input NAND gate (a) TE cl @ ~~ + 13. Which of the following is not functionally a complete set ? (@) AND,OR (c) NOR @® NAND (d) AND, OR, NOT 14. In which of the following gates, the output is high if and only if all inputs are high ? @ NOT () AND © OR (a) XOR 15. In which of the following gates the output is high if and only if at least one input is high ? (a) NOT (6) AND () OR (@ NAND 16. In which of the following gates the output is high if and only if at least one input is low ? (a) NOT (b) AND (c) OR (d) NAND 17. In which of the following gates the output is 0 if and only if at least one input is 1? (a) NOT (®) AND (c) NOR (d) NAND 18. 19, 20. 21. 22, 26. 27. DIGITAL TECHNIQUES For which of the following logic gates, the output is complement of the input ? (a) NOT. (®) AND (@ OR (@) XOR Let A and B be the inputs to a NAND gate. Then the output is equal to @ A+B () A.B © AB (d) Let A and B be the inputs to a XOR gate. Then the output is given by @ A+B () AB © x @ KB+aB The NAND gate can function as a NOT gate if () inputs are connected together (©) inputs are left open (©) one input is set to 0 (d) one input is set to 1 What is the minimum number of two-input NAND gates used to perform the function of two- input OR gate? (a) one (©) three (6) two @ four Which of the following gates are added to the inputs of the OR gate to convert it into NAND. gate? @ NOT (®) AND (©) OR (@) XOR Which logic function is produced by adding inverters to the inputs of an AND gates ? (@) NAND ®) NOR (©) XOR @ OR Which logic function is produced by adding an inverter to each input and the output of an AND gate? @ NAND © OR Which of the following gates is known as “concidence detector” ? (a) AND @) OR (©) NOT (@) NAND An AND gate may be visualized as (@) switches connected in series () switches connected in parallel (©) MOS transistor connected in series (d) none of these (6) NOR @ XOR442 ue 12. 13, 14, 15. 16, 17. An alternative way of showing a two input NOR An alternative symbol for two input NAND gate is @ (6) “> - Which of the following is not functionally a complete set ? (@) AND,OR (e) NOR, Yo @ (® NAND @ AND, OR, NOT In which of the following gates, the output is high if and only ifall inputs are high ? @ Nor (6) AND © OR (d@) XOR In which of the following gates the output is high if and only if at least one input is high ? @ NOT () AND (© OR (@ NAND In which of the following gates the outputis high if and only if at least one input is low ? (a) NOT (6) AND (c) OR (d) NAND In which of the following gates the output is 0 if and only if at least one input is 1? (a) NOT (6) AND (c) NOR (d) NAND 18. “19, 20. 21. 22, 24, 26. 27. DIGITAL TECHNIQUES For which of the following logic gates, the output is complement of the input ? (@) NOT (6) AND (©) OR (@) XOR Let A and B be the inputs toa NAND gate. Then the output is equal to (a) A+B & AB (@) A.B Let A and B be the inputs to a XOR gate. Then the output is given by (a) A+B (6) AB ©) KB @) AB+AB The NAND gate can function as a NOT gateif (a) inputs are connected together (0) inputs are left open (©) one input is set to 0 (d) one input is set to 1 © KB What is the minimum number of two-input NAND gates used to perform the function of two- input OR gate ? (a) one (©) three ®) two @ four Which of the following gates are added to the inputs of the OR gate to convert it into NAND gate? (a) NOT (c) OR (®) AND (@ XOR Which logic function is produced by adding inverters to the inputs of an AND gates ? (@ NAND () NOR (© XOR @ OR Which logic function is produced by adding an inverter to each input and the output of an AND gate? (@ NAND @®) NOR (c) OR (d) XOR Which of the following gates is known as “concidence detector” ? (a) AND ® OR (c) NOT (d) NAND ‘An AND gate may be visualized as (@) switches connected in series () switches connected in parallel (©) MOS transistor connected in series (d) none of theseDIGITAL TECHNIQUES: 28. An OR gate may be imagined as (@) switches connected in series (®) switches connected in parallel (©) MOS transistors connected in series (d) none of the above 29, Which of the following gates would have output 1 when one input is 1 and the other input is 0? @ OR (®) AND (©) NAND (d) both (a) and (c) 30. Which gate is formed by adding an inverter at the output of an OR gate? (@ NOR () XOR (c) EQUIVALENCE (d) NAND 31. What is minimum number of NAND gates needed to perform the logic function A.B? @il (6) 2 © 3 @4 32, Which of the followings functionally a complete set? (@ AND,OR () AND,XOR (©) NOT,OR @ AND, OR, NOT 83. Which of the following is not true ? (@) 0+A=A @ 1+A (0) AtAsA @ 1.4 34, How many bits are required to encode all twenty six letters, ten symbols and ten numerals ? @ 5 ® 6 @7 @ 6 35. Which table shows the logical state of a digital circuit output for every possible combination of logical states in the inputs ? @ functiontable (6) truth table (© routingtable (d) ASC-IItable Clock signals are u sed in sequential logic circuits G@) to tell the time of the day @®) to tell how much time has elapsed since the system was turned on (©) ‘to carry serial data signals (@) to synchronize events in various parts of a system 37. Which table shows the electrical state of a digital circuits output for every possible combination of electrical states in the input? (@) function table (6) truth table (©) routingtable (d) ASC-IItable 1 36, 38. A comparison between serial and parallel adder’ reveals that serial order (a) is slower © is faster (©) operates at the same speed as parallel adder @ is more complicated 4.43 89. The circuit given below is a 2 A a. coturs oa (a) fulladder (©) parity checker () full subtractor @ none of these 40. The output D and E in the circuit of Q. 39 are (@) D=(A@B).C E=(A@B)@C 6) D=AB+BC+AC E=A@B@C (©) D=(A®B)@C E=(A@B)+C @ D=(AB+BC)@AC E=A@B@C 41. How many truth table can be made from one function table? @ one @) two © three @ any number 42. A positive AND gate is also a negative (@ NANDgate (6) NORgate (© AND gate @ OR gate 43, In the switching circuit shown, RC time constant is much longer as compared to the time period of its input pulse signal. The V,,, of this circuit is of the form op wit OF 0| aah ® vf I] ia [ ; ° “400 | @ ==T484 44, 45. 46. 47. 48, 49. 50. By placing an inverter between both input of an S.R. flip-flop, it becomes (a) J-K flip-flop (6) D-flip-flop () T=flip-flop (d) Master slave JK flip-flop Positive logic in a logic circuit is one in which (a) logic 0and 1 are represented by 0 and positive voltages respectively (®) logic 0 and 1 are represented by negative and positive voltages respectively (©) logic 0 voltage level is higher than logic 1 voltage level (d) logic 0 voltage level is lower than logic 1 voltage level As compared to MOS memories, bipolar memories have (a) slower success time but are cheaper (b) slower access time and are costly (©) faster access time and are cheaper (d) faster access time and are costly Most of the linear ICs are based on the two- transistor differential amplifier because of its (a) input voltage dependent linear transfer characteristic (6) high voltage gain (©) high input resistance (@) high CMRR Among the following, the slowest ADC Analogto- digital converter) is (a) parallel-comparator (.¢. flash) type (6) successive approximation type (c) integrating type (d) counting type ‘The output of a logic gate is “1” when all its input are at logic “O”, the gate is either (@) aNAND oran EX-OR gate (®) aNOR or an EX-OR gate (c) an AND or an EX-NOR gate (d) aNOR or an EX-NOR gate If xx ¥ = 0, then which one of the following is true? (@) H + pxtxzexy tye ® O Fy+F @) zyx=1 + aye sayz + =xy+ ry DIGITAL TECHNIQUES 51. Consider the following logic circuit consisting of 2-4 decoder for each of decoder. f,=1when i= 0, i, f,=1wheni;=1, i,=0 and 50 on, Which of the following gives value of g (x,y, 2)? @) x.y. @1 @ y+ Rye © lxy+ zp ].z 52. The open collector output of two 2 input NAND gates are connected to a common pull up resistor. If the input to the gates are P, Q and R, S respectively, the output is equal to @ P-QeRS (© P.Q+R.S (6) PQeRS @ P.Q.R.S 53. In standard TTL gates, the totem pole output stage is primarily used to (@) increase the noise margin of the gate (®) decrease the output switching delay (©) facilitate a wired or logic connection (@ increase the output impedance of the circuit 54, The Boolean expression for the output of the logic circuit shown in the figure is oe D> @) Y=AB+AB+C (6) Y=AB+AB+C (©) Y=AB +AB+C d)Y=AB+AB+C 55. The number of comparisons carried out ina 4 bit flash-type A/D converter is @ 6 © 5 @4 (d) 4 56. A 10 bit A/D converter is used to digitise an analog signal in the 0 to 5 V range. The maximum peak to peak ripple voltage that can be allowed in the dc. supply voltage is (a) nearly 100mV (©) nearly 25 mV () nearly 50 mV (d) nearly 5.0 mVDIGITAL TECHNIQUES 57. 58. 60. 61. ‘The output time period of a transistorised monostable multivibrator using base resistor R,, and coupling capacitor C,, for the output transistor is given by @ R,C, () 0.69R,C, (@ 2R,C, (d) 1.38R, .C, ‘The circuit given in the figure is a block commonly used in linear ICs. This is basically a @ } © @ current amplifier constant current source constant voltage source voltage amplifier ‘The switching circuit given in the figure can be expressed in binary logic notation as A c a (@) L=(A+B)(C+D)E (0) L=AB+CD+E () L=E+(A+B)(G+D) @ L=(AB+CD)E\ The number of comparators in a prarllel conversion type 8-bit A to D-converter is (a) 8 ) 16 (o) 255 @ 256 For the digital circuit shown in figure, the output Q,Q,Q,Q) = 0001 initially. After a clock pulse appear, the output Q,,@,@, will be 62. 63. 64, 65. 445, Ifthe negative logic is used, the diode gate shown in the given figure will represent (a) ORgate (© NORgate () AND gate (@) NAND gate Which of the following is the truth table of the given logic is truc? FAD = (a) © © @ == © o|n =e ele cools Ina half-adder having two inputs A and B and two output (S and C are the sum and carry output bits respectively) the Boolean expression for S and C in terms of A and Bis, @ S=KB+A-B; C=A.B ©) S=AB+AB; C=A+B @ S=AB+A-B C=A.B (@) None of these Acombinational circuit has inputs A, Band C and its Karnaugh map is as shown. The output of the circuit is given by AB c\ 90 o 110 ° 1 1 af 4 1 (a) 0001 fc) 0100 () 0011 @ 1100 (@ (AB+AB)C —— @) (AB+AB)C @ A®BeC4.48 66. 67. 68. 69. The output Q, of a J-K flip-flop is zero. It change to L when a clock pulse is applied. The input J, and K, are respectively @ landX (6) OandX (c) XandO @ Xand1 ‘To realise the given truth table from the circuit shown in the figure, the input to J in terms of A and B would have to be ‘ Combinational 1) oy Togie be ai A lock @ 3B ‘Truth Table Ox By a) J © B o| of a} o @ 4B of afa fa 1] of A] o afijo |x The circuit given in the figure is to be used to implement the function Z=f(A,B)= A +B. What values should be selected for I and J? q J a [= @ 0, J=B @ I=B, J=1 ® Isl, J=B @ 1=%, J=0 Given the logical function of four variables (A,B,C, D)= (4+8C) (B+CD) The function as a sum of product will be @) A B+BC+ACD+BCD () AB+A B +ATD+BCD (©) AB+AB+ACD+BCD @ AB+AB+ACD+BCD 70. n. 2. 14. DIGITAL TECHNIQUES: In the negative logic system, (a) the more negative of the two logic levels represents a logic "1" state (®) the more negative of the two logic levels represents a logic "0" " state (©) all input and output voltage levels are negative the output is always complement of the intended logic function @) ‘The combinational logic circuit shown in the given figure has an output Q which is c ie \, Ih ux Ih 1 1 1 S Se AB @) ABC (@) A+B+C © ABBeC Ad AOBOC The output of the gated network shown in the figure is sD AD- a (a) (AB) (CD) (EF)(6) AB + CD + EF (© AB+CD+EF @ (A+B)(C+D)(E+F) The digital multiplexer is _ basically a combination logic circuit to perform the operation @ AND-AND (6) OR-OR (©) AND-OR @ OR-AND Part of a digital phase meter is shown in the figure. If the input signals are V, (t) = V, sin ot and V, (t) =- V, sin (ot + 30°), the reading of the meter will be “0 ) 330° @ 210°DIGITAL TECHNIQUES 5. 16. 11. 78. Assuming that only the X and Y logic inputs are available and their complements X and ¥ are not available, what is the minimum number of two-input NAND gates require to implement X ey @ 2 o3 4 @5 A3-bit weighted resistor DAC shown in the figure has V, = 2V and R,\R = 2 For an input of 100, the output will be ; Prep @ -2V ® -4V (©) 2v @ 4Vv ‘The decoding circuit has been used to generate the active low chip. Select Signal for a micro- processor peripheral. (The address line are des- ignated as A 0 to AT for I-O address) s—D— :=—D—=p z =Dp— @) GOH to 63H (©) 70H to 73H Xb) A4toATH (@, 70 H to 73 H In a JK flip-flop wd have I = @ and K= 1. Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q then clock for 6 pulses, the sequence at the Qoutput will be ce fi ota ' k a (@) 010000 (®) 011001 () 010010 @ 010101 81. 447 Fora binary half-subtractor having two inputs A and B, the correct set of logical expression for the outputs D (= A minimum B) and X (= borrow) are @ D=AB+AB,X= AB (® D=AB+ AB,X=AB (© D=AB+AB,X=AB @ D=AB+AB,X=AB The "ECL" has very high switching speed because the transistors are (a) switching between cut-off and saturation regions (0) switching between cut-off and active regions (©) switching between active and saturation regions @) allof these The following sequence of instructions are ex- ecuted by an 8085 microprocessor : 1000 LXISP, 27 FF 10003 CALL 1006 1006 POP H The contents of the stack pointer (SP) and the HL, register pair on completion of excution of these instructions are (@) SP = 27 FF, HL = 1003 () SP =27 FD, HL = 1003 (c) SP = 27 FF, HL = 1006 (d) SP = 27 FD, HL = 1006 For a particular type of memory, the access time and the cycle time are respectively 200 ns and 200 ns. The maximum rate at which the data can be accessed is @ 2.5 x 10% @) 5x 10% (©) 2% 10%s @ 1*10%s ‘The Q output of a J-K flip-flop is ‘1’. The output does not change when a clock-pulse is applied: The inputs J and K will be respectively (X-denotes don't care state) (@) OandX @® Xando © Lando @ Oand1.4.48 84. The block diagram shown below represents (a) modulo —3 ripple counter () modulo ~5 ripple counter (©) modulo ~7 ripple counter (d) modulo ~ 7 synchronous counter 85. The circuit shown in the figure below is —q —C-__] (@) anadder (®) asubtractor (©) parity generator (d) comparator ity 86. The characteristic equation of the T-FF is given by @ Q@=TQ+TQ ) Q@=TQ+QT ©) Q=TQ @ Q@=TR 87. Figure shown below depicts the circuit of a gate in RTL family. The cireuit represents a (@) NAND (©) NOR (6) AND (d) OR 91. 92. 93, DIGITAL TECHNIQUES An R-Slateh isa (@) Combinational circuit (®) Synchronous sequential circuit (© One bit memory element (d) One clock delay element. Schottky damping is resosted to in TTL gates (@) to reduce propagation delay (8) to increase noise magins (©) to increase packing density (@) to increase fan-out. A Darlingtion emitter-follower circuit is some- times used in the output stage of a TTL gate in order to (@) increase its Tp, (©) reduce its Toy, (©) increase its speed of operation (@ reduce power dissipation The logical expression Y = A 4 Bis equivalent to = @ y=AB () y=AB © y=A+B @ y=A-B ‘The minterss corresponding to decimal number 1Bis (@) ABCD @) ABCD @ A+B+ © A+B+C+D D ‘The minimized expression for the K-map shown below is AB @\w a1 1 10 oof Ti | ol ufijafi 10) 1 @ ABC D+AcD ® ABC D+A CD+ABC | Ol © BE D+CD+ABC @ BC D+CD+BC A 4-bit presettable UP counter has preset input 0101. The preset operation takes place as soon as the counter becomes maximum 1111-The modulus of the counter is @ 5 © 1 ) 10 @ 15DIGITAL TECHNIQUES 95. A mod-2 counter followed by a mod-5 counter is, (@) sameas a mode-5 counter followed by a mod- 2 counter (6) adecade counter (©) amod-7 counter (d) none of the above. 96. Ananalogvoltageisin the range of 0 to 8 Vis divided in eight equal intervals for conversion to 3-bit digital output. The maximum quantization error is (@ ov () 0.5V @ 1V (d) 2V 97. The resolution of a D/A converter is approximately 0.4% of its full-scale range. It is (a) an 8 - bit converter (b) a/n 10-bit converter (©) alm 12-bit converter (@) aln 16 ~ bit converter 98, ‘The data-bus width of a 204 8 bits is @ 8 &) 10 © 2 @ 6 99. Four memory clips of 16 x 4 size have their ad- dress bases connected together. The system will be of the size (@) 64% 64 (©) 32%8 (©) 16x16 (d@) 256*1 100. A 4-bit-synchronous counter uses flip-flops with \ propagation delay time of 25 ns each. The maxi- ‘num possible time required for change of state will be (a) 25 ns (c) 75 ns (®) 50ns (@) 100ns 101. In the figure shown, X, X, X, will be 1's comple- ment of A, A, Ay if by (a) Y=0 © ) Y=1 » @ Y=A,=A,=A, 4.49 102. A switch-tail ring counter is made by using a single D FF. The resulting ciruit is (@) SR flip-flop (6) JK flip-flop (@ D-FF @) T-FF 103. A 4-bit modulo-16 ripple counter used JK flip- flop. If the progression delay of each FF is 50 ms, the maximum clock frequency is equal to (@) 20MHz () 10MHz © 5MHz @ 4MHz 4 104, A 12-bit ADC is operating with a 1u sec clock period and total conversion time is seen to be 14 hisecs. The ADC must to be of the (@) flash type ©) counting type (©) integrating type (@) successive approximation type 105. A pulse train can be delayed by a finite number periods usings of clock (@) a serial —in ~ serial shift register (®) a serial ~in ~ parallel — out shift register (©) a parallel in serial ~ out shift register (@) a serial ~in parallel — out shift register 106. The minimum number of NAND gates required to implement A+AB + ABC is equal to 1 @7 107. The switching speed of ECL is very high, because the transistors (@) are switched between cut-off and saturation regions. (®) and switched between active and saturation regions, (a) zero 4 (© and switched between active and cut-off regions. (d) may operate in any of three regions, 108.In standard TTL, the ‘totem pole’ stage refers to (@) the multi-emitter input stage (6) the phase-splitter (©) the output buffer (@) open collector output stage.4.50 109, 110. 1m. 112, 113. 14. Each cell of a station Random Access memory contains (@) 6 MOS transistors () 4 MOS transistors and 2 capacitors (©) Two 2-input NORs and One X-NOR gate * (@) XOR gates and shift registers. In a virtual memory system, the address specified by the address lines of the CPU must be wee. than the physical memory size and than the secondary storage size. (a) smaller, smaller (6) smaller, larger (d) larger, larger (©) larger, smaller Acomputor system has a 4K word cache organised in blockset associative manner with 4 blocks per set, 64 words per block. The number of bits in the SET and WORD fields of the main memory address formula is, (@) 15,4 (6) 6,4 (c) 7,2 4,6 Figure shown below the circuit of a gate in the Resistor Transistor Logie (RTL) family. The cireuit represents a Vee (a) NAND (6) AND (c) NOR . A (d) OR en The initial contents of the 4-bit serial-in-parallel- out, right-shift. Register shown in figure below is 0110. After three clock pulses are applied, the contents of the Shift Register will be (a) 0000 Clock __p— a 101 Seriatin Irie © 1010 _! @ un. —— Dual slope integration type Analog-to-Digital converters provide (a) higher speeds compared to all other types of A/D converters (©) very good accuracy without putting extreme requirements on component stability 19. A pulse DIGITAL TECHNIQUES (©) poor rejection of power supply hum (d) better resolution compared to all other types of A/D converters for the same number of bits. 115, The logic realized by the circuit shown in figure below, is co. 4 stot MUX ¢}—e —l, ct 'y SS Ae @ F=ACC ) F=A6C \ © F=Bec @ F=Bec 116. Choose the correct statement(s) from the following : (@) PROM contains a programmable AND array anda fixed OR array. (0) PLA contains a fixed AND array and a programmable OR array (©) PROM contains a fixed AND array and programmable OR array (d) None of these 117. Choose the correct statement(s) from the following (@) PROM contains a programmable AND array anda fixed OR array () PLA contains a fixed AND array and a programmable OR array {c) PROM contains a fixed AND array and a programmable OR array (@) PLAcontains a programmable AND array and a programmable OR array. 118, Boolean expression for the output of XNOR (Equivalent) logic gate with inputs A and B, is @ aB+AB @) AB+aB @ (A+B)(A+B) train with a frequency of 1 MHz is counted using a modulo 1024 ripple-counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per flip-flop stage 8 con SC. (a) 100 (ce) 20 (©) (A+B)(A+B) (b) 50 (d) 10 \DIGITAL TECHNIQUES 120. For the logic circuit shown in the figure below, the output Y is equal to (a) ABC (©) AB+BC+A+C @) ABEBC (©) A+B+C 121. In a microprocessor, the register which holds the address of the next instruction to be fetched is (@) Accumulator (6) Program Counter (©) Stack Pointer (d) Instructor Register 122. A 10bit A/D converter is used to digitise an analog signal in the 0 to 5 V range. The maximum peak ripple voltage that can be allowed in the D.C. is (@) nearly 10mV (6) nearly 50mV (© nearly 25mV — (d) nearly 5.0 mV 123. Data can be changed from spatial code to temporal code and vice-versa by using (a) ADCsand DACs (0) shift-registers (©) synchronous counters (d) timers. 124, The output of a logic gate is ‘1’ when all its inputs are at logic ‘0’. The gate is either (@) aNAND or an EX-OR gate (6) aNORor an EX-NOR gate (©) aOR or an EX-NOR gate (@) aANDor an EX-OR gate 125, A PLA can be used (a) as a microprocessor (®) asa dynamic memory (c) to realise a sequaential logic (d) to realise a combinational logic 126. A dynamic RAM consists of (a) 6 transistors (6) 2 transistors and 2 capacitors “(c)_ 1 transistor and 1 capacitor (d) 2 capacitors only 451 127. The output of the circuit shown in the figure is equal to sD} Lypyoueuy — @o ()1 () AB+AB (d)(A*B) *(A*B) 128, The minimum number of NAND gates required toimplement the Boolean function A+ AB +ABC is equal to (a) zero (1 (4 @7 129, A switch-tail ring counter ismade by usinga single flip-flop. The resulting circuit isa (a) SR flip-flop (0) JK flip-flop ()D flip-flop - (d)T flop-flop 130, Schottky clampoint is resorted to in TTL gates (a) to reduce propagation delay (0) to increase noise margins (©) to increase packing density (d) to increase fan-out 131. A pulse train can be delayed by a finite number of clock periods using (a) aserial-in serial-out shift register (b) a serial-in-parallel-out shift register (c)a parallel-in serial-out shift register (d) a parallel-in parallel-out shift register 132,A 12-bit ADC is operating with a 14 sec clock period and the total conversion time is seen to be 1491 sec. The ADC must be of the (a) flash type (6) counting type (o) intergrating type (d) successive approximation type. 183. The total number of memory accesses involved (inclusive of the op-code fetch) when an 8085 processor executes the instruction LDA 2003 is @1 (2 ©3 (aa452 134, The following sequence of instructions are executed by an 8085 microprocessor 1000 LXI SP,27FF 1003 CALL 1006 1006 POP H ‘The contents of the stack pointer (SP) and the HL register pair on completion of execution of these instruction are (a) SP = 27 FF, HL = 1003 (6) SP = 27 FD, HL = 1003 (c) SP = 27 FF, HL = 1006 (d) SP = 27 FD, HL = 1006 135. The number of bits in a binary PCM system is, increased from n ton + 1. Asa result, the signal to quantization noise ratio will improve by a factor nél @ ~~ (By Zim» (c) QR eetrn (d) which is independent of n. 136, In the following question, match each of the items in list I with an approximate item on the list II and select the correct answer from the codes given below lists List I List 1 A. Shiftregister 1. for code can be used conversion B. Amultiplexer 2. to generate can be used memory slip to select. C. Adecoder can be 3. for parallel-to- used serial conversion 4. as a many-to-one switch 5. for analog-to- digital conversion, Codes : A BC @1 23 0) 3 41 (ce) 5 42 (a1 35 137, 138, 139, 140, DIGITAL TECHNIQUES An excess-3 code is used to represent the integers 0 through 9, thus Number Code (ABCD) 0 1100 1 0010 2 1010 3 ono 4 110 5 0001 6 1001 7 0101 8 101 9 oon Which of the following expressions is the correct one for an invalid code? @) B.C.D.+CD @ B.C.D.+A.C.D © B.C.D.+B.C.D. +AC.D+X @ B-E.D-+A.C. D. A Lu pulse can be converted into a 1 ms pulse by using (a) a monostable multivibrator (®) anstable multivibrator (©) abistable miltivibrator (d) aJ-K flip-flop ‘The decimal equivalent of the hexadecimal number E5 is, (@279 (8) 229 (427 (@) 3000, How many 1 ‘s are present in the binary representation of Bx 5124 7x 6445x843? @s (b)9 (©)10 @uDIGITAL TECHNIQUES ia 142. 143. 144, 145. 146, The gate shown in the figure is Vee Vo vy [ we 4 (a) AND gate (6) NAND gate (c) NOT gate (d) OR gate When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero? (a)Sign-magnitude (6) 1’s eomplement (c)2's complement (d) 9"s complement A carry look ahead adder is frequently used for addition because, it (a) is faster (b) is more accurate (c) uses fewer gates (d) costs less The logic circuit given below converts a binary code Y, Y, Y, into . rol Y| whe ob (a) Exces-3 code (©) BCD code ‘The greatest negative number which can be stored in computer that has 8-bit word length and uses, 2's complement arithmetic is (a) -256 (6)-255 (c)-128 (197 A retriggerable monoshot is one which (@) can be triggered only once (®) has two quasi-stable states (©) cannot be triggered until full pulse has been (d) iscapable of being triggered while the output is being (6) Gray code (d) Hamming code 453 147. Which of the following statements is correct? 1. A flip-flop used to store 1-bit of information 2, Race-around condition occurs in a J-K flip-flop when both the inputs are 1 3, Master-slave configuration is used in flip-flops to store 2-bits of information 4, A transparent latch consists of a D-type flip- flop Select the correct answer using the codes gigen below (a)1,2and3 ()1,2and4 (6) 1,3and4 (d) 2,3. and 4 48. Which one of the following can be used to change data from special code to temporal code ? (a) Shift registers (6) Counters ()A/Deonverters (d) Combinational cireuits 149. Match List-I (computer terms) with List-II (definitions) and select the correct answer using the codes given below the lists List -1 List - IT A. Interface 1, A measure of rate of data transmission B.Abit 2. Abinary digit ‘The common boundary between various sections, and subsections ©. Baud Speed 4. Analog to digital converter Codes: A BC @ 3 2 1 ® 3 1 2 @ 2 4 1 @4 2 8 150. In the given network of AND and OR gates DP By fcan be written as () XX yo HFK Kye Hy HK, Kye Ky ee K, ©) XX, + XH HK () xy #X, +x + +X, (A) Xp XX one Ky + My My Kye Xp oy hae + Xp aXer +X454 151. Match List - { with List - IJ and select the correct answer using the codes given below the lists : List -1 List - Il A.A@B=0 LA#B B. A+B =0 2A=B C.K .B=0 B.As1&B=1 D.A®B=1 4.A=1&B=0 Codes : A BC D @i 2 4 8 @2 3 4 2 @1 38 2 4 @2 4 1 8 152. The minimum Boolean expression for the following circuit is 8 ex a c (a) AB+AC+BC (A+B (6)A+BC @A+B+C 153. The number of switching functions of 3 variables is (a8 (c) 128 (0) 64 (d) 256. 154. Match List-I with List-II and select the correct answer using the codes given below the lists : List -I List - II (Logic Gate) (Characteristic) A HTL 1. High fan-out B.CMOS 2. Highest speed of operation C.PL 3. High noise immunity D.ECL 4, Lowest product of power and delay Codes A BC D @4 3 2 1 ®4 1 2 8 3 1 4 2 @3 4 1 2 DIGITAL TECHNIQUES 155. The figure of merit of a logic family is given by (@) gain bandwidth product (b) (propagation delay time)*(power dissipation) (©) (fan-out)* (propagation delay time) (@) (noise margin)* (power dissipation) 156. A full-adder can be implemented with half-adders and OR gates. A 4-bit parallel full adder without. any initial carry requires (a)8 half-adders,4-OR gates (b)8 half-adders, 3-OR gates (c) Thalf-adders, 4-OR gates (d) Thalf-adders, 3-OR gates. 157. Which one of the following will give the sum of full adders as output? (a) Three input majority circuit (6) Three bit parity checker (c) Three bit comparator (d) Three bit counter. 158. Which one of the following is equivalent to AND- OR realization? (a) NAND-NOR realization (6)NOR-NOR realization (©) NOR-NAND realization (@) NAND-NAND realization. 159. A combinational circuit in one is which the output depends on the (@) input combination at that time © input combination and the previous output, (© input combination at that time and the previous input combination @ present output and the previous output. 160. The Q-output of J-K FLIP-FLOPis"1". The output does not change when a clock-pulse is applied. ‘The inputs J and K will be respectively (where ‘x-don’t care state) (a) Oand x (6)xand0 (©) Lando (d)0and1 161. A divide by 78 counter can be realized by using (@ 6 mos of mod-13 counters (®) 13 mos of mod-6 counters (©) one mod-13 counter followed by one mod-6 counter (d) 13 mos and mod-13 counters.DIGITAL TECHNIQUES, 162. 163. 164, 165. 166. 167. Ina sequential cireuit, the outputs at any instant, of time depends (a) only on the inputs present at that instant of time (b) © @ Ina 4bit weighted resistor D/A converter, the resistor value corresponding to LSB is 32-k ohm. The resistor value corresponding to MSB will be (a) 32 k-ohm (b) 16 k-ohm (c) 8 k-ohm (d)4k-ohm on past outputs as well as present inputs only on the past inputs only on the present outputs Hamming codes are used for error detection and correction. If the minimum Hamming distance is, 1m, then the number of errors correctable is (a) equal tom (b) less than m/2 (c) equal to 2m (@) greater than m If the memory chip size is 256 1 bits, then the number of chips required to make up 1 K (1024) bytes of memory is, (32 (24 (12 @s The decimal equivalent of the hexadecimal number (3 E 8),, is (a) 1000 (0) 982, (768 (d)323 Each instruction in an assembly program has the following fields : 1. Label field 2. Mnemonic field 3, Operand field 4, Comment field The correct sequence/order of these fields is (a) 1, 2,3,4 )1,2,4,3 (¢) 2,1,3,4 (d) 2,1, 4,3 168. 169, 170, 455 The circuit shown in the figure is equivalent to @ () fe) @ ‘The Venn diagram representing the Boolean expression A+(A “Bis (e) NOL @ S/ tii The complement of the Boolean expression AB. (BC+AC)is (a)(A + B)+(B+T).(A +) (A. B)+BE+ AT) ((K +B). B+ S). (A + 6) (d)(A+B). (B +C).(A+0)4.56 171. Match List-I with List-I and select the correct. answer using the codes given below the lists : List-1 List i A 45 110110100 B 9 211010010 C. 180 3.01011010 . D. 210 4.00101101 5. 10101000 Codes : ABCD @3 4 52 43 12 ©4352 @34 21 (@)(A+B)C+DE (6) AB+C(D +E) ()(A+B)C+D+E (d)(AB+C). DE 173. Storage of 1 KB means which of the following number of bytes? (a) 1000 (6) 964 (©)1024 @ 1064 174, Which of the following is a CORRECT definition of volatile memory? @) It loses its contents at high ambient temperatures (®) Its contents are lost on failure of power supply (©) Ithas to be kept in air-tight boxes always (@) It is the latest type of bubble memory. DIGITAL TECHNIQUES 175. Which of the following descriptions relates to a floppy diskette? (a) 9-track 1600 BPI (6) double-sized double density () 33 MHz -zero-wait time (d) 40 MB capacity. 176. Which of the following is NOT correct ? 17. 178, 179, 180. (a) A memory location is identified by a unique number called its address (6) The content of a memory location does not change its address (©) Entering data into a memory location does not change its address, (@) A memory location can hold only a data item and not a program instruction. Which of the following is an example of volatile memory? (a)ROM (RAM () PROM (d) HARD DISK. A storage medium which cannot support both direct-access and sequential access application is (a) magnetic drup (6)hard disk (c) magnetic tape (@) floppy disk ‘The major disadvantage of magnetic tapes is (a) cost (b) unrealiability of sotred data (c) slow data recording (@) data is to be accessed sequentially One Megabyte is equivalent to (a) 2” bytes (6) 2 bytes (c) 2” bytes (b) none of theseDIGITAL TECHNIQUES: 181. A system has a word length of 4 bits. If in this, system negative numbers are represented by their 2's compliment, then the range of numbers that can be represented by the word length is (a)-8 to +8 ()-Tt0+7 (c)-16 to + 16 (d) none of these 182. Which of the following is associated with optics ? (a) Winchester disk ()RSM ()CD-ROM (d) None of these 183. The number 7F00 in Hexadecimal when multiplied by 16 is @TFI6 (c) 7006 184. For a MOD-12 counter, the FF has a t,, = 60 ns. The NAND gate has a t,, of 25 ns. The clock frequency is (a) =3.774 MHz (c)< 3.774 MHz (6) 167F00 (d) none of these (6) > 3.774 MHz (@)= 4.167 MHz 185. The basic memory cell of dynamic RAM consists of (a)acapacitance (6) a transistor (©)aflip-floop (d)a transistor acting as a capacitor. 186. Which of the following use least power ? (a) TTL, (6) ECL () CMOS (d) Alluse same power 187. PROMs are used to store (a) bulk information (6) sequential information (c) information to be accessed rarely (d) relatively permanent information 188. A T-flip-flop function is obtained from a JK flip - flop. If the flip-flop belongs to a TTL family, the connection needed at the input must be @ J=Ke1 ® J=K=0 (©) J=landK=0 (d)J=OandK=1 189. In a negative edge triggered J-K flip-flop in order to the output Q state 0, 0 and 1 in the next three seccessive clock pulses, the J-K input states required would be respectively @ 00,01and10 (6) 00, 01and 11 © 00,10and01 — @) 01,10 and 11 487 190. The circuit shown in the given figure is x |_ E> >— = |~l>— a > @ anadder circuit (6) asubtractor circuit (©) acomparator circuit (d@) a parity generator circuit 191. CE configuration is the most preferred transistor configutaion when used as a switch because it (@ requires only power supply (®) requires low voltage or current (©) is easily understood by every one @ has small log 192, ‘The characteristic equation of the T - flip - flop is given by @ Qt=TQ+TQ ©) Qt=TQ+QT © Qt=TQ @Qr=TQ 193. The initial contents of the 4-bit serial-in-paral- lel-out, right-shift, shift register shown in the given figure is 0110. After three clock pulses are applied, the contents of the shift register will be (@) 000 “seus fof 1] afo @ 0101 a () 1010 @ un 194. A relaxation oscillator (@) has two stable states ®) oscillates continuously (©) relaxes indefinitely (@) produces non-sinusoidal output 195. Four memory chips of 16 x 4 size have their address buses connected together. This system will be of size (@ 64x4 © 1616458 196. Full adder circuit can be implemented by (@) Multiplexers (6) Half adders (c) AND & OR gates (d) Decoders 197. Ina 4-bit full adder, how many half adders and . OR gates are required ? (@) 8&4 (6) 7&4 © 7&3 @ 8&3 198. The type of gate shown in the given figure is DIGITAL TECHNIQUES 199. In a JK flip-flop, the output Q, is 1 and it does not change when a clock pulse is applied. The possible combination of J, and K,, could be (x denotes don't care). @ xando (®) xand1 (ce) Oandx @ landx e 200. The dual of A +[B +(AC)] + D, is B x (a) A+(B(A+C)]1+D a A @ A(B+Ac)D eter aie (A+(B(A+O)]D © NAND ater @ ABA+O1D ANSWERS [ 1@ 26 8@ 4 5 60 7@ 8&6 %@ 0 | IL@ 12.6) 13.@) 14.6) 15.) 16.2) 17) 18.(@)— 19.6) -20.(d) 21(a) 22.(c) 23.(a)-24.(6)25.(c) 26a) BT.) 28.6) -29.(d)—80.(a) 31.(0) 82.(@) 88.) 84.(0)-35.(6) 86.) 87.(a)88.(2)-39.(a)—40.(b) 41.(0) 42.(d) 48.(6) 44.(0) 45.(d) 46.(d) 47.4) 48.08) 49.(d)—50.(a) 51.(d) 52. (a) 53. (b) 54.(6) 55. (6) 56d) 57.(b) 58. (6) 59.(a) 60. (c) G1.(6) 62.(6) 63.) 64.(a)65.(d) 66.(a)67.(c)68.(6) 69.(a)_—70.(a) 71.(b) 72. (c) 73.(c) 74.(d) 75. (d) 76. (b) ‘T7.(a) 78.(d) 79. (c) 80. (b) 81.(d) 82. (d) 83.(b) B4.(c) 85.(d) 86.(b) 87.(d) 88. (c) 89. (a) 90.(d) 91.(d) 92.(d) 93. (d) 94. (6) 95. (a) 96. (c) 97.(a) 98.(a) 99.(6) 100.(a) 1O1.(a) 102.(d) 103.(c) 104.(d) 105.(a) 106.(@) 107.(c) 108.(c) 109.(a) 110.(c) U1(d) 112.2) 148.(c)114.(6)-115.(6) 16.) 117.) 118.) -119.(@) 120. (6) 121.(6) 122.(d) 123.(a) 124.(b) 125.(d) 126.(c) 127.(a) 128(a) 129.(d) 130.(a) AS1.(a) 132.(a) 183.(c) 184.(c) 135.(@) 136.(6)137.(c) 138.(d)_139.(4) 140.(a) T41.(c) 142.(c) 143.(@) 144.(6) 145.(c) 146.(d) 147.(c) 148.(a) 149.(a) 150.(d) 151.(6) 152.(a) 153.(@) 154.(d) 155.(6) 156.(d) 157.(a) 158.(d) 159.(a) 160. (b) 161.(c) 162.(6) 163.(d) 164.(6) 165.(a) 166.(a) 167.(6) 168.(b) 169.(a) 170.(a) 171.(6) 172.(a) 178.(¢) 174.(6)-175.(6)176.(d)177.(6) 178.()179.(@)180.(6) 181.(c) 182.(b) 183.(d) 184.(a) 185.(@) 186.(c) 187.(d) 188.(a)_ 189.(6)190.(c) 191.() 192.(6) 193.() 194.(d)195.(6) 196.(a) 197.(¢) 198.(d)199.(a) 200.(d)