Project 1

Project Name: Basic logic gates

Student name: Jaideep reddy Telukuntla
Student ID: 16231591
Course Name: Introduction to VLSI design
Course Number: EC-ENGR 5542-0001
Date of submission: 09/22/2016
University/Department Name: UMKC / CSEE

Table of contents:
1. and gate
schematic
symbol
test circuit and output
layout and output
2. or gate
schematic
symbol
test circuit and output
layout and output
3. xnor gate
schematic
symbol
test circuit and output
layout and output
4. nand gate
schematic
symbol
test circuit and output
layout and output

1. and gate:
schematic

 symbol

 test circuit

 output

 layout

 output

2. or gate:
schematic

 symbol

 test circuit

 output

 layout

 output

3. xnor gate:
schematic

 symbol

 test circuit

 output

 layout

 output

4. nand gate:
schematic

 symbol

 test circuit

 output

 layout

 output