Muc lue MUC LUC ~000— PhanI Tim hiéu vé ng6n ngif Verilog HDL 1 Chudng 1 So luge vé Verilog HDL 3 1.1 Module 3 1.2. M6 td m6 hinh dong dit lieu 4 1.3 MO hinh hanh vi 4 14 M6 hinh cau tric 4 1.5 M6 hinh thiét ké dang hén hop 5 Chung 2 Nhiing phan tif trong ng6n ngit 6 2.1 Hé théng Task va Functions 6 2.2. Nhitng chi thj bién dich ( Compiler Directives) 6 2.3. Dit gid ti ( Value set ) 7 2.3.1 Integers a 2.3.2 Reals 8 2.3.3 Strings 8 24 Kiéu ditligu 8 2.4.1 Net Types 9 24.2 Register Types uw 2.5 Parameters 12 2.6 Operators (todn tit) 13 2.6.2 Nhiing todn tit sO hoc 14 2.6.2 Nhitng todn tit quan he 14 2.6.3. Nhitng todn tit can bling 15 2.6.4 Nhitng todn tit logic 15 2.6.5 Todn tit lya chon theo bit 16 2.6.6 Todn tit rit gon 17 2.6.7 Ton tit dich chuyén 7 2.68 Toén tit diéu kign 18 Chuong 3 M6 hinh mite céng 19 3.1 Nhiing céng co ban xy dyng sin 19 3.2 Nhitng céng 6 nhiéu ngo vao 19 3.3. Nhitng céng c6 nhiéu ngé ra 2 3.4 Cée cing 3 trang théi 21 3.5 Nhiing céng day 22 3.6 Nhiing c6ng te MOS 23 3.7 Céng t&c déng mé Fai chiéu 24 3.8 Delay cng 24 SV:Phan Thj Mj Anh - Nguyén Pham Xuén ChungMuc luc 3.9 Sy thé hién mot ming Chuong 4 User-Defined Primitives (UDP) 4.1 Su dinh nghia mot UDP 4.2 Combinational UDP 4.3 Sequential UDP 4.3.1. Thanh ghi trang thai khdi tao 4.3.2 M6 hinh hanh vi t4c dong mite 4.3.3 M6 hinh hanh vi téc dong canh Chung 5 M6 hinh dong di ligu 5.1 Cau lénh gan lién tiép 52 MOtvidy 5.3. Lénh gan trong khai bao net Chung 6 M6 hinh hanh vi 6.1 Xay dung thi we 6.1.1 Céu lénh initial 6.1.2 Cau Ignh always 62 Cau lénh khéi 6.2.1 Khoi man ty 6.2.2 Khdi song song 6.3 Cau lénh gén thi tuc 6.3.1 Delay bén trong cau Iénh 6.3.2 Cau lénb gén thi tuc dang khéi 6.3.3. Cau Iénh gan thi tuc dang khéng kh6i 63.4 Cau Ignh gén lién tigp va cau Iénh gan thi tue 64 Cau lénh diéu kign 65 Cau lénh case 6.6 Cau lénh ip 6.6.1 C4u lénh lap forever 6.6.2 C4u lénh lap repeat 6.6.3. Cau Iénh lp while 6.6.4. Cau Ignh lip for 6.7 Cau Iénh gan lién tip thi tue 6.7.1 Assign-deassign 6.7.2 Force-release Chuong 7 M6 hinh cau tréc 7.1 Module 7.2 Ports 7.3 MOti module 7.3.1. Nhitng cOng khéng két néi 7.3.2, Chiéu dai céng khic nhau SV:Phan Thi Mj Anh — Nguyén Pham Xudn Chung 25 26 26 27 27 27 27 30 30 31 31 32 32 32 33 34 34 34 34, 35 35 36 36 36 37 37 37 37 38 38 39 39 39 40 40 40 41 41 41Muc luc 7.3.3. Nhiing tham bign trong module 42 Phin II Gidi thiéu vé cic phan mém hé tr¢ va FPGAs IL1 Gigi thigu vé phan mém Synario 4.1 43 IL2 Gidi thiéu vé nhiing ASIC cé sin cia FPGAs 50 112.1 Actel ACT 51 11.2.2 Xilinx LCA 53 1.2.3 Altera FLEX 55 11.2.4 Altera MAX 55 13 Dang phdn mém Max +plus II nap chic nang ctia thiét ké yao 56 mot thiét bj Phan INT Ung dung thiét ké CPU 8bits 63 IL1 M6taCPU 63 IIL1.1 T6 chife b6 nhd 64 ML.1.2 Céc lénh ciia CPU 64 HL1.3 Ché d6 dja chi ciia Iénh 66 THL.2 M6 ta cau tric bus va cau tric CPU 68 TIL3 Phan tich qué trinh thyc hign Iénh cia CPU 69 TL4 Lap tinh CPU 1 UL4.1 ALU (Arithmetic logic unit ) 78 IL4.2 SHU ( Shift Unit) 9 T1L4.3 SR( State Register ) 80 11.4.4 AC ( Accumulator ) 81 IIL4.5 IR( Intruction register ) 82 11.4.6 PC ( Program counter) 83 IIL4.7 MAR ( Memory address register ) 84 1.4.8 Két néi cdc bus, cdc thanh ghi va diéu khién CPU 85 SV:Phan Thi Mj Anh - Nguyén Pham Xuén Chung -‘Ngén ngit Verilog HDL Phinl TIMHIEU VE NGON NGU VERILOG HDL Ng6n ngif Verilog HDL 18 ng6n ngi m6 ta phan ciing vi thé trude khi tim hiéu vé ng6n ng Verilog HDL ching ta hay xem qua m6 hinh cia mot dong thiét ké ding dé thiét ké mot ASIC(Application-Specific Intergrated Circuit ) Gi6i thigu vé dong thiét ké: Hinh 1 duéi day hién thj ting budc thiét ké mgt ASIC; ching ta goi day 18 mot dong thiét ké ( design flow ). Nhiing bude duge ligt ké bén dui -véi sy’ m6 t4 t6m tit chite nang cla mdi bube. sor} e Rio = :/ a rea s ooo Teh na ig i e 1. Design entry : Bi vao thiét kE bén trong mét hé thOng thiét ké& ASIC, sit dung ng6n ngit mé t& phan cing (HDL) hay schematic entry. 2. Logic systhesis : Sit dung mot HDL ( VHDL hay Verilog ) va m6t cng cu téng hop mach logic dé dua ra m6t mang lui — mot sy md td nhiing té bao logic( cells logic ) va sy két néi cia chting. 3. System partitioning : Phan hoach mét hé th6ng 1dn ra thanh nhiing b6 phn ASIC véi kich thuéc xée dinh. 4. Prelayout simulation: Kiém tra dé xem sy chinh xéc cila chtfc nang thiét ké. 5. Floorplanning : Sap x€p nhitng khdi cia mang lu6i trén chip. ‘SV:Phan Thi Mj Anh ~ Nguyén Pham Xuan ChungNgén ngit Verilog HDL Placement: X4c dinh vj tri cita nhitng té bao trong khéi. Routing : Tao két néi gitta t€ bao va nhiing kh6i. Extracion: X4c dinh dign tré va dign dung cla mach. Postlayout simulation : Kiém tra € xem thiét ké vin lam vige v6i nhiéu két néi dug thém vao. OND Tir bude 1-4 1a thanh phiin ciia thiét ké logic, va tiy bude 5-9 1a thanh phan cia thiét ké' vat ly. C6 mét va syf tring Tap. Vi du, bude system partitioning c6 thé duige xem nhwt 18 bude logic hode bude vat ly. Khi thyc hign system partitioning chting ta cin phai luu ¥ dén c& hai nhan t6 logic va vat ly. tren chting ta di gidi thigu so luge vé dong thiét ké trong phin tiép theo sau day ching ta sé tim hiéu vé ng6n ngit Verilog HDL - ng6n ngit mé. t& phan citng. n Thi M§ Anh - Nguyén Pham Xudn ChungNgén ngit Verilog HDL -3- Chuong 1 SO LUQC VE VERILOG HDL 1.1. Module: Dan vi mé td co ban trong Verilog 1a module. Mot module mé té cfu triic hay chifc nang ciia m6t thiét ké. Dutt day 1a cu nic e¢ ban cia mot module : module module_name ( port_list ); Declarations: reg, wire, parameter, input, output, inout, function, task, . Statement : Initial statement Always statement Module instantiation Gate instantiation UDP instantiation Continuous assignment endmodule Nhitng khai bao va nhiing cfu lénh cé thé rai déu trong module nhung mét khai b4o phai duige xudt hign truéc khi sit dung. Tét hon hét 18 ta nén Khai béo trutéc mi cau lénh. Sau day 18 mOt vi dy don gidn cia mét module vé mé hinh mach cOng nifa hién thi 6 hinh 1.1 module HalfAdder( A, B, Sum, Cout); input A, B; output Sum, Cout; assign #2 Sum = A*B; assign #5 Cout= A&B; endmodule 8 jay Hinh 1.1 Ten cia module 1a HalfAdder. C6 4 c6ng; hai céng nhap 1a A va B, hai cng xudt la Sum va Carry. SV:Phan Thi My Anh - Nguyén Pham Xudn ChungNgn ngit Verilog HDL 4: Module chita hai cu lénh chi dinh lién tiép m6 ta hanh vi lung dit ligu ciia mach cOng nita. Hai c4u Iénh nay xdy ra déng thdi KhGng phan biét thi ty xudt hign cia ching trong module. Sy thyc thi ca mdi cu lénh dya trén co sd nhiing sy kién xuat hién én A va B. Trong mét module, mt thiét ké c6 thé dugc mé ta trong nhitng kiéu sau day: i. Kiéu dong dit liéu ii, Kiéwhanh vi ii, Kiéu cfu nic iv. Téng hgp bat ky cia nhitng kiéu trén. 1.2 Mo td mo hinh dong di ligu: Kj thuat co ban duge sit dung trong mo hinh dong dif liéu 1a cfu 1énh lién tiép. Cau tric ciia cu lénh 1a: assign [ delay ] LHS_net = RHS_expression; Bat ky gid tri cba mot todn tit dude sit dung trong biéu thitc bén phi thay dé6i , biéu thite bén phai sé duge x4c dinh gid tri va gid tri nay sé duge ‘g4n vao bén tréi sau thdi gian delay xéc dinh. Néu khOng c6 delay thi gid tri mic dinh cia delay 1a 0. Chit ¥ rling cde cau 1énh lién tiép dink m6 hinh dong di ligu mach; cdn cifu tréic thi dn kh6ng r6 rang. Thém vao 46, céc cau lénh lién tiép thue thi dng thoi ma khéng phy thugc vao thi ty’ cia ching, 1.3 Mé hinh vir Hanh vi cila mét thiét k€ duge mé ta bling céch sit dung cu tric thi tye. B6 la: i. Cau Iénh initial : cau Iénh nay chi thyc thi mot lan. ii, Cau Jénh always: cfu Iénh nay 1p lai nhiéu lan. Chi cé kiéu di liu thanh ghi mdi c6 thé duge gén gid tri trong nhitng cau lénh nay. Nhu vay kiéu dif ligu sé lfu gid trj ca n6 cho dén khi c6 mot gid tri méi duge gén. Tt cd nhiing cu Iénh initial va cau lénh always bit dau thyc thi HERE” M6t ki ty duge thé hién bing 8 bit ma ASCII vi vay dé Iuu dutgc chudi “INTERNAL ERROR" ta cin m6t bin c6 kich thu6c 1a 8*14. reg [1 : 8*14] Message ; Message = “INTERNAL ERROR” ; Kity “\" duge sit dung : \n —-xudng dong méi Me Gb: karl kia 24 Kiéu d@ligu: Verilog HDL cé hai nhom kiéu dif liéu : i. Net type : MOt net type thé hién mOt két ndi vat ly gitta nhing phan tit trong cu tric. Gié tri cla n6 ditge xéc dinh tit gid tri cia nhitng diéu khién cita né nhu 1 mét c4u Iénh chi dinh lién tigp hay mot cOng xudt. Néu khOng c6 diéu khién dé két n6i 4€n mt net thi net mic dinh Ja gid ti z, SV:Phan Thi My Anh ~ Nguyén Pham Xudn Chung‘Ngon ngit Verilog HDL “9+ ii, Register type: Mot register type thé hign mot phan ti Iuu trit dit liu tritu tung, N6 dude dinh gid tri trong cau lénh always hay cu lénh initial. N6 c6 gi tri mic dinh 18 x. 2.4.1 Net Types: Céc loai cia kiéu dif ligu net: © wire ui wor trior wand triand trireg wil tri0 supply0 | © supply! | Cau tric Khai b4o cho m@t net: { ‘Net_kind [ msb : Isb ] net1, net2,...,netN ‘Trong 46 net_kind 18 mot trong nhitng kiéu net 6 trén. msb va Isb 1a hing s6 xe dinh kich thuéc efa net ; néu pham vi khong xéc dinh thi kich thude mic dinh la mét bit. Wire va Tri: ay [a kiéu phé bign nbét cia net. Mot wire net va mOt tri net gidng nhau vé cu triic vA ng nghia ; tri net 6 thé dude sit dung dé mé ti mot net noi c6 da didu khién diéu khién mét net va khéng c6 ¥ nghia ndo khéc. wire Reset ; wire [ 3:2] Cla, Pla, Sla; tri[ MSB-1:LSB—1] Art; Néu da diéu khién digu khién mt wire ( hodc m6t tri ) net, gid tri cla net duige xéc dinh bang c4ch sit dung bang sau : wire (tri) o 1 x Zz 0 0 x x 0 1 x i x 1 rae Zz oO 1 x Zz | Wor va Trior CA wor va trior gidng nhau vé cu triic va chifc nang. “SV:Phan Thj My Anh — Nguyén Pham Xuan ChungNg6n ngit Verilog HDL -10- wor [ MSB : LSB ] Art; trior [Max - 1: MIN- 1 ] Rdx, Sdx, Bdx 5 Néu da digu khién diéu khién net nay, gid tri ca net duge xéc dinh bling céch sit dung bang sau : wor (rior) oi x = 0 o i x 0 1 11 11 x x 1 x x z o 1 xz 4 Wand va Triand Ca hai gidng nhau vé edu tric va chite nang. wand [ -7 : 0] Dbus; triand Reset , Clk; Néu da diéu khién diéu khién net nay, gid tri cla net duge xéc dinh bing céch sit dung bang sau : wand ( triand ) olelelele nlx }elole 0 1 x Zz oe [oe [ae [o> |e ns |x J fo fos Trireg net ‘Net nay hiu gi? gid tri ( gidng nhu mét thanh ghi ) va dutge sit dung dé thigt ké mit dién dung. Khi tt c& nhing diéu khign din dén mét trireg net 6 trang thai tng tré cao thi o6 gid tri 1a 2. Trireg [ 1:8] Dbus, Abus ; ‘Trio va Tril net Néu kh6ng c6 diéu khién nado 6 net nay thi gi trj cia n6 14 0 cho tri0 ( 1 cho tril ). Tri0 [ -3:3 ] GndBus ; Tril [ 0:-5 ] OtBus, ItBus ; Néu da digu khién diéu khién net nay, gid tri cla net duge xéc dink bing cdch sit dung bang sau : woh [O 1 x =z 0 ox x 0 1 x tox 1 x paeerxoen ener Zz o 1 x _ 0d) ‘Phan Thi My Anh - Nguyén Pham Xuén ChungNeon ngit Verilog HDL Supply0 va Supply net: Supply0 net tao ra mot sai day vee Két n6i 06 dink 4én mee 0 trong xehi Supply] net tgo ra mot soi day duce ‘két n6i o6 dinh dén mite 1 supply0 Gnd, ClkGnd + supply! { 2:0] Vee s 2.42. Register Types? C6 5 kiéu register: reg integer + time « real «realtime Reg Register: Reg Ia kidu dat ligu thanh ghi tnvdng duge sit dung abst. Ct phép khai béo Ia: reg [ msb : Isb ] regl, 1082. - wstegN 5 sb va Isb Ta hing 86 cho biét pham Vi ie than ghi. Néw pham vi khong dutge xée dinh thi gid tri mge dinh 1B thanh ghi 1 bit. Gi tri cila thanh ghi duige higu la mot s6 khong dau. Memories ‘Mot memory 1a mot mang ce thanh ghi. Dang: reg [ msbilsb ] memory! {uper! slowerl] memory? luper2:lower2} y-+-5 Vidu: reg [0:3] MyMem (0:63] j/MyMem la mot mang 64 thanh ghi Abit reg Bog{1:5] y/Bog 18 mot mang 5 thanh ghi 1 bit ‘MyMem va Bog 18 nhitng memory ‘Met memory thude 1oai thank Bhi ag ligu. ‘Mot khai béo reg 66 thé duge sit dung aé khai bao cd registry lin memory. Integer Register (Thanh ghi integer) ‘Mot thanh ghi integer chia nhane gid trj nguyen. NO 06 thé duge sit dung nhu 1a mot thanh ghi két qua chung » tigu biéu cho md hinh hanh vi mic cao.Khai béo 06 dang: integer integerl, integet2, --- » integerN { msb : Isb ; Cha ¥ ring mot 56 nguyén ti thigu 1a 32 bit, Mot thanh ghi integer khOng thé tray cap nh 1a bit-vector. ‘Time Register: ‘SV:Phan Thi My ‘Anh - Nguyén Pham Xudn Chung‘Ngdn ngit Verilog HDL 212- Mt thanh ghi time duge sit dung dé lun tr va digu khién nhing si4 tj thdi gian, Khai bdo dang = time time_idl, time_id2, ..., time_idN [msb:lsb]; insb va Isb Iu giit pham vi xéc dink, khi khong Khai béo pham vi th} méi cai ‘git m6t gié tr it nhdt 1a 64 bit. Real va Realtime Register: ‘Thanh ghi real ( hoe thanh ghi Realtime) khai béo mht sau: real real_regl, real_reg2,.. .. real_regN; realtime real_regl, real_reg2, . . . real_regN + Gi ty} mac jah cia real 1a 0. Khi gi tr x va z dutje dink cho real ch nhiing gid tri nay duge xem 1a 0. real RamCnt ; RamCat = ‘b01x1z; ‘Thi Ram cé gid tr) 14 : 01010 sau khi gan. + bit-select: Bit-select IA mét bit dude chon trong mot vector. N6 c6 dang: Net_or_reg_vector [bit_select_expr] Vidu: State[ 1] && State[4] _ // Register bit-select Pri{0] | Bbq 1Net bit-select Neu bit chon 1A x hay z hay mt gid tr} ngodi gidi han thi gi tri ela bit select 1a x. Vi du : State[x] I8 x. * part-select: ‘Trong part-select, mt s6bit in tiép ké nhau due chon.N6 o6 dang: net_or_reg_vector [msb_const_expr : Isb_const_expr] Vi du: State [1:4] _// Register part-select Prt [1:3] //Net part-select Néa chi s6 xée dinh pham vi 1d mOt gié trj x hay 2 hay mot gié ti ngodi gidi han thi part-select 18 x. 2.5 Parameters: ‘Mot parameter 18 mot hing s6, N6 thuing dude sir dung a6 xéc dinh delay va chiéu rong cia bign, Mét parameter chi duge gén mot gid tri. Khai bio dang 5 parameter param| = const_exprl , param? = const_expr?2,« paramN = const_exprN ; Vidu: parameter LINELENGTH = 132, ALL_XS 16°bx ; ‘SV:Phan Thi My Anh — Nguyén Pham Xudn ChungNgén ngit Verilog HDL. 2.6 Operators (todn ti ) Operator trong Verilog HDL : i. Arithmetic operators ii, Relational operators iii, Equality operators iv. Logical operators v, _ Bitwise operators vi, _ Reduction operators vii, Shift operators viii, Conditional operators ix, Concatenation va replication operators ‘Trong bang sau hién thj quyén tu tién (ti ten xudng duioi va ten cla nhitng todn tit, Nhitng todn ti cing tren mét hang c6 quyén wu tién bling nhau: Phép ton Y nghia + Phép cong, - Phép triv ! Phép phi dinh - Lay phan bi theo bit & Riit gon theo phép ton and ~& Lay bd ciia phép todn and 44 rot gon * Rit gon theo phép toan xor ~Ahoic~ —_Lfy bi ciia phép xor da rit gon \ Rait gon theo phép todn or -l Lay bd ciia phép or d& rit gon . Phép nhan. / Phép chia % Phép chia lay du + Phép cOng theo bit : Phép triv theo bit << Phép dich tréi > Phép dich phai < Nhé hon < Nhé hon hodc bing > Lén hon > Lénhonhojcbing ‘SV:Phan Thi Mj Anh - Nguyén Pham Xuan Chun,Negén ngit Verilog HDL -14- ence eee Phép bing logic Phép khong bing logic = Tring hgp bing ' Trung hgp khong bing _ & and theo bit chon * xor theo bit chon A~ hodc ~* xnor theo bit chon t or theo bit chon. && Phép va logic Phép ho§c logic 2 Phép diéu kign ‘Tat cd nhitng todn tit ket hop tir tréi sang phai ngoai tit todn tir diéu kién thi két hop ti phai sang trai. Vi du: AtB-C tuong dong : (A+B) -C // Tit trdi sang phai Trong khi : A?B:C2D:F tudng duong: A?B:(C?D:F) // Phai sang tréi 2.6.1 Nhiing todn tit so hoc: Nhitng todn tif s6 hoe 1a: © + cng theo bit © - strit theo bit © * :nhan © J cohia % : chia lly duv Néu bat ky bit nao cita mot todn hang trong todn tif sé hoc 1a x hay 2 thi két qua la x .Vi dy : “b1Ox1 + ‘bOLLL két qua 18 “bxxxx 2.6.2, Nhifng todn tif quan h¢: Todn tif quan hé 1a: > (1dn hon ) © <(nhé hon) >= (én hon ho§e bing ) © <=(nhé hon hodc bling ) Két qua cia todn ti quan hé [a true ( qua lax tri 1) hode ( gid tri O). Két “SV:Phan Thj Mj Anh ~ Nguyén Pham Xuén ChungNg6n ngit Verilog HDL -15- néu bat ky bit nao trong méi tosn hang Id x hole z. Vi dy = 23>45 IA false ( gid tri 0) trong khi: 52.<8°hxFF 1a x N6u tosn hang khOng bing nhau vé kich thie , ton tit nhé hon sé duge 1am diy v6i bit 0 ti bén trai, 2.6.3 Nhéing todn ti cin biing : Nhiing todn tit cn bing la : bing logic ) (_khéng bing logic ) (tring hop bing ) (truding hgp khéng bing ) Két qua phép so sénh 1a false ( gid tri 0) hoge IA true ( gid tri 1) -Gid trj x va z dude xem 1a nhing gid tri khdng rd rang va két qué cila phép so sénh khong bao gid 18 mot gid tr unknown, trong khi trong phép so sénh logic thi gid tri x va gid tri z c6 J nghfa riéng cilia n6 va két qud 6 thé Ia gid tri unknown. Trong phép so sénh logic néu todn tia x hay 2 thi két qua 1a x. Néu chigu dai cia todn tit khOng bing nhau, todn tf nhd hon sé duye lam day véi 0 tir bén trai. 2.6.4. Nhitng todin tif logic = Nhitng todin tif logic la: © && (and logic ) © II(or logic ) ©! (toan tit bi logic ) Crd=‘b0; //01a false Dgs=‘b1; //1 ate thi: Crd && Dgs 18 0 (false ) Crd liDgs 141 (true ) !Dgs 180 (false ) ‘Véi todn hang vector, mot vector khéc 0 duge xem 1a 1. Vidu: A_Bu: B_Bus = ‘b0100; thi: A BusilB_Bus a1 ‘SV:Phan Thi My Anh ~ Nguyén Pham Xudn Chung‘Ngon ngit Verilog HDL =16- A_Bus && B_Bus cing la 1 va: 1A_Bus gidng !B_Bus BO Néu mét bit bit ky cia todn tir 1a x, két qua Ia x. Vid: kx 2.6.5 Toan tit hfa chon theo bit : Cée toan tit gm = .~ Phép dio bit o& Phép and theo bit ot Phép or theo bit . Phép xor theo bit © ~*hodc ~ Phép xonr theo bit Nhitng bing sau hién thi két qua cia ning todn ti tén: &(and)|O 1 x z_|[_ Wor) |O 1 x z olo o 0 0 Oo o= =i 1 jo 1 x x hjel = t al 1 x |O x x x xix 1 ox x z\0 x x x mele x Xx | a(xor) [OI xz Ax(xnor)|O_ 1 xXx ojo 1 x oj1 oO x ijt 0 x x ijo 1 = 4 x|x ox x Xx x|x ox x Xx z\|x x x z\x x xk Xx _SV:Phan Thi Mj Anh - Nguyén Pham Xuén Chung‘Ngén ngit Verilog HDL 217 ~ (negation) [01 x7 ul 0 x x 2.6.6 Todn ti rit gon: hing tofin tif rdt gon hoat dong trén tat od ede bit ca tosn hang don va két qua 1a 1 bit. Nhing todn tira : ¢ & (and) : N6u bat ky bit ndo 1a O, thi két qud 18 0 ; cdn néu bit nao Ia x hay z,, thi két qua Ia x ; néu khéng nifa thi két qua Ta 1. © ~& (nand ) : Dao cila phép and. © Cor) : Nu bat ky bit ndo 1a 1, thi két qua 1a 1 ; con néu bit no Ia x hay z, thi két qua 18 x; nu khong n(fa thi két qué 1a 0. ¢ ~1( nor) : Dao cia phép or. «9 Cxor) : NGu bit ky bit ndo [a x hay z thi két qué 1 x; néu sO ugng bit 1 trong todn hang 1a chain thi két qué 1a 0 ngude lai 18 1. * -*(xnor ) : Ddo cia phép xor. 2.6.7 Toan tit dich chuyén ( Shift operators ) : Nhitng todn ti dich chuyén 1a © << (dich wai) «>> (dich phai ) Toan tit djch chuyén sé dich chuyén toan hang bén tri véi s6 Ian dich chuyén 1 s6 ton hang bén phai. D6 Ia phép dich logic. Nhting bit bi bd tng sé duge lam day v6i gid tri 0. Néu todn hang bén phai c6 gid trj 1a x hay 2 thi két qua cla phép dich chuyén 1a x. Vi dy: reg (0:7] Qreg 5 Qreg =4"b0111; thi: Qreg>>2 18 8"b0000_0001 Verilog HDL khéng c6 todn ti lay s6 m(. Tuy nhién, todn tit dich chuyén c6 thé duge sit dung dé hd tro digu nay mt phan, Vi dy, néu ban tham gia vao vic tinh tons 28" thi ban 06 thé dat duge bing céch sit dung toan tit dich chuyén, nhu sau 32’bl << Numbits //Numbit phdi nhd hon 32. SV:Phan Thi Mj Anh ~ Nguyén Pham Xuan ChungNgon ngit Verilog HDL 18 Voi cach tutong ty, bd gidi ma 2-to-4 due xdy dung bling céch sit dyng toan tir dich chuyén : Wire [0:3] DecodeOut = 4'd1 << Address [0:1] ; ‘Address [0:1] c6 thé c6 nhitng gi tri 0, 1, 2 va 3. Do 46, DecodeOut 6 gid tri 14 470001, 4°b0010, 4°b0100, va 4761000. 2.68 Todn ti diéu kign : ‘Todn tif digu kién chon mot bidu thife dyva wén gid tri cla biéu thee digu kign va n6 06 dang sau : cond_expr ? exprl : expr2 N&u cond_expr la true ( gid tri 1) ,exprl dutge chon , néu cond_expr 1a false ( gid tri 0 ), expr2 duge chon. ‘Néu cond_expr 1a x hay z thi két qua 1 Ot bit chon trén expr] va expr2 v6i sy logic sau : 0 voi 0 cho 0, 1 véi I cho 1, edn Iai la x. ‘SV:Phan Thi Mj Anh - Nguyén Pham Xudn ChungNgén ngit Verilog HDL +19 Chung 3 MO HiNH MUC CONG 3.1 Nhitng céng co ban xy dung sin : Nhiing c6ng co ban x4y dung sn sau day c6 sin trong Verilog HDL : i. Nhing céng 6 nhiéu ngé vao : and, nand, or, nor, xnor ii, Nhiing c6ng c6 nhiéu ngé ra : buf, not iii, Nhiing cdng 3 trang thai : bufif0, bufif1, notif0, notif1 iv. Nhitng céng day ; pullup, pulldown vy. Nhitng cOng tfc MOS :emos, nmos, pmos, remos, mmos, rpmos vi. Nhiing c6ng téc diéu khién hai chiéu: tran, tranif0, tranifl, rtran, rtranifO, rtranifl Day 1A dinh dang ed ban : ,termN ) ; gate_type [ instance_name ] ( terml, term2, Chi § rng instance_name Ia tu) chon ; gate_type 1a mét trong nhiing céng duge ligt ké 4 wn. Con nhing term thi x4c dinh kiéu net va kiéu register duc két ni dén dau cuéi ciia cOng. Néu c6 nhiéu sy thé hién cia cing mot kiéu cdng ta o6 thé sit dung cau tric sau : gate_type Linstance_namel ] (term11, term12, ..., termiN ); [ instance_name? ] ( term21, term22, . . . , term2N ) ; [ instance_nameM ] ( termM1, termM2, . . ., termMN ) ; 3.2 Nhifng céng cé nhiéu ngo vao: and nand or nor xnor Nhiing céng logic nay chi c6 mOt ngd ra va mot hay nhiéu ngd vao. Dui day 1a cdu trie cla 6: multiple_input_gate_type [instance_name ] ( OutputA, Input, Input2, .. ., Input SV:Phan Thi Mj Anh - Nguyén Pham Xuén ChungNgén ngit Verilog HDL -20- ‘M6 hinh logic thé hién 6 hinh 3.1: moD™ & Jy a Budi0) sar 0] he baat! ST Sep (2) Sut{2] au sii) Sse oe Hinh 3.1 Dui day 1 céc bang sy that cho nhitng céng mé 14 6 wén. Chi ¥ ring gid tr] z tai ngd vao thi duyc diéu khién gidng gid tri x, thém vao 46, ng ra cia c6ng c6 nhiéu ng6 vao khéng thé 1a gid tri z. and|O 1 xz nand|Q 1 xz O00 0-0 ofl roi ot Ot x x 1 jt 0 x x x |O x ox x eel x x Oe x zilox ox x o |O 1 x z nr [QO 1 xz ONG) at of] x et 100) 0 0) x |x 1 ox x x jx 0 x x z]x tox x z ix 0 x x } i SV:Phan Thi Mj Anh - Nguyén Pham Xuén ChungNgén ngit Verilog HDL -21- xo {OQ 1 xz patio | Odie Geet ojo i x «x oft o x 1/l 0 x x r/o 1 x x x fx ox ox x eee z ix x x ox a x 3.3 Nhiing cng cé nhiéu ngé ra : buf not Nhiing cdng nay c6 m6t ng6 vao va mét hay nhiéu ngo ra. Hién thi & hinh 3.2. Ci phép : multiple_output_gate_type Linstance_name ] ( Out1, Out2, ... , OutN, Input ) ; out Fes ron Do] rot — Bun ar Inga [>| 08? be L— oun hinh 3.2 Bang sy that: buf jo 1 xz {no [0 output]Q_1 x x _|loutput{1 0 x x 3.4 Céic céng 3 trang thai: im N bufif0 bufifl notif0 notifl Nhiing cng nay c6 mét ng6 ra, mt ngd vao dif ligu va mot ngd vo diéu khién . Ca phdp : Isitafp_gate [instance_name J ( OutputA, InputB, ControlC ) ; Wihag iFM} Ath — Nguyén Pham Xudn Chung _aniziani,_ |Negén ngit Verilog HDL +22 Xem hinh 3.3. Tuy thude vao ngé vao diéu khién, ngé ra c6 thé & trang thai td khéng cao ( gid tri z). V6i cOng bufifO, ng6 vao la z néu digu Khién 1a 1, ngugc Iai thi dé ligu sé dugc chuyén ra ngé ra. V6i bufifl, ng6 ra la znéu diéu khién 1a 0, nguge lai thi dit ligu sé duge chuyén ra ngé ra. Véi céng notif0, ngé ra 1a z néu diéu khién 1a 1 nguoe lai thi ng6 ra Ia gid tri dado ctia ng6 vao dif ligu. Tuong ty cho notif1, ng6 ra 1a z néu diéu khién 1a 0. nit butt oo t OupHA ayy Outputs Control Conttol nati. bes trea oi to a Conte Conta: Hinh 3.3 Sau day 1a bang sy that: bufif0 Control bufifl Control Or ox 2 Ol xz 0f0 2 Oz ofz 0 02 OZ Data} 1 {loz Vz Vz Data | 1 | z 1 Vz Ve aie x es z|x zo x x z x x x notif0 Control notifl Control Oi x 2 Ooi x 2 | oll 2 ik it Olz 1 kk it Data} 1/0 2 Oz Of ||Datal1|z 0 Of Ol x[/x oz ox x wiz x x ox z\x 2 ox x zlz x x x 3.5 Nhiing céng diy : pullup pulldown "han Thi Mj Anh - Nguyén Pham Xuan ChungNgén ngit Verilog HDL Nhiing c6ng nay chi cé mét ng6 ra kh6ng c6 ngé vao. Mét cdng pullup dat gid tri 1 trén ng ra cia nd, Mot cdng pulldown dat gid tr} 0 trén ngo ra ciia né. N6 6 dang sau: pull_gate [ instance_name ] ( Output ) ; Vi dy: pullup PUP ( Pwr) ; Céng pullup nay e6 tén 18 PUP v6i ng6 ra Pwr néi t6i 1. 3.6 Nhiing cong tic MOS: cmos — pmos mos remos—rpmos_—_ mos Diy Ia nhiing cng the déng mé mét chiéu, nghia 1a dong dif ligu tir ng6 vao dén ngé ra va dong dif ligu o6 thé bj ngét bling céch thiét lap ng vao diéu khién Cai phap: gate_type [instance_name ] ( OutputA, InputB, ControlC ) ; Véi nmos va mmos néu diéu khign 1a 0 thi cong the d6ng ( ngé ra gid tri z), néu diéu khién 1a 1 thi di ligu tai ngo vao sé duge dua ra ng6 ra. Voi mos va rpmos thi ngudc Iai, Input Oupus a) up Conta: Conte moe witch procs svitch Hinh 3.4 Du6i day 1a bang sy that: pmos | Control nmos. Control ] rpmos |O_ 1 xz mmos [0 1 xz 0 [0 z Oz Oz 0 |z 0 Of” Oz ee ay ee Lz. We We Datal x |x z x x Data | x jz x x x z[zzze zilzx x x SV:Phan Thi Mj Anh - Nguyén Pham Xudn ChungNg6n ngit Verilog HDL Céng t&e cmos ( complimentary MOS ) va remos ( resistive version of cmos ) €6 mOt ng ra dif ligu, mét ng6 vao dif ligu va hai ng vao didu khién. Cé phap: (©) cmos [ instance_name } ( OutputA, InputB, NControl, PCotrol ) ; Céng tde cmos duge xem la sy két hgp cilia pmos ( rpmos ) va nmos (rnmos) vi ng6 vao va ngo ra ding chung. Xem hinh 3.5 arte ee LJ Corto Hinh 3.5 3.7 Cong tac déng mé hai chiéu: fran tran tranif0 —rtranif0 ~—tranif1—_rtranifl Nhiing c6ng tfc nay 1 hai chiéu, nghia 1a dong d@ ligu c6 thé i tir ng6 vao dén ng6 ra va nguge Iai. KhOng c6 delay khi dit ligu truyén qua cOng tée, BOn cOng t&c sau cing c6 thé bj déng bling cdch thiét lap mét tin higu diéu khiénthtch hgp. Cdn cbng t4c tran va rtran khong bi dong. Ci phép cho tran va rtran : (tran [ instance_name ] ( SignalA, SignalB ) ; Ci phép cho nhitng céng the con lai : Gate_type [ instance_name ] ( SignalA, SignalB, ControlC ) ; Néu ControlC 18 1 cho tranif0 va rtranif0, va 0 cho tranifl va rtranifl thi dit ligu bi nga, 3.8 Delay céng: Viée delay sy truyén tin higu tir ngo vao dén ng6 ra c6 thé duige xée dinh bang céch sit dung mét delay céng. Co phép : gate_type [ delay ] [ instance_name ] (terminal_list) ; Khi kh6ng c6 delay thi mac diah la zero. M6t delay céng c6 thé c6 ba gid tri sau: © Rise delay «Fall delay © Tum off delay SV:Phan Thi M3 Anh — Nguyén Pham Xuan ChungNg6n ngit Verilog HDL Vi du: notifl #( 2, 8, 6 ) ( Dout, Din1, Din2 ) ; tise delay 1a 2, fall delay 18 8, turn off delay 1A 6, V6i nhitng céng c6 nhiéu ngo yao va nhing céng c6 nhiéu ngé ra th) chi c6 hai gid tri delay cdn nhitng céng ba trang théi thi c6 thé cé ba gid tri 2 delay va nhiing cOng déy thi khong cé delay. 3.9 Sy thé hién mt mang: Cai phép ctia sy thé hign mét cng trong trudng hgp nay: gate_type [ delay } instance_name [ leftbound : rightbound | (list_of_terminal_names ) ; Vidu: wire [ 3:0] Out, InA, InB ; nand Gang [ 3:0] ( Out, InA, InB ) ; tuong dung: nand Gang ( Out [3], InA [3], InB [3] ), Gang ( Out (2], In [2], InB [2] ), | Gang ( Out [1], InA [1], InB [1] ), Gang ( Out [0], In [0], InB [0] ) ; SV:Phan Thi My Anh ~ Nguyén Pham Xudn ChungNgén ngit Verilog HDL Chuong 4 USER-DEFINED PRIMITIVES (UDP) 4.1 Sy dinh nghia mot UDP: MO6t UDP duige dinh nghia bing cach sit dung mt khai b4o UDP c6 cu tric nhu sau : Primitive UDP_name ( OutputName, List_of_inputs ) ; Output_declaration List_of_input_declarations [ Reg_declaration ] [nitial_statement ] table List_of_table_entries endtable endprimitive M6t dinh nghia UDP khéng phu thugc vao dinh nghia module vi vay ‘n6 xudt hién ngoai module. M@t dinh nghia UDP ciing c6 thé chéa trong mot text file rigng biét. MOt UDP chi c6 thé c6 mot ngé ra va mOt hay nhiéu ngd vao. Ngo dau tién phai 1a ng6 ra. Thém vao a6, ng6 ra c6 thé 6 gid tri 0,1 hay x (z KhOng dude cho phép ). Néu mt gid tri z xudt hign trén ng6 vao thi né duge xem nhu la gi tri x. Hanh vi cia mot UDP thi duge m6 td trong dang bang. C6 hai loai hanh vi duge m6 td trong mot UDP: 7 i, Combinational ii, Sequential 4.2 UDP két hgp : Trong UDP két hyp, bing xc dinh nhiing sy két hyp ngé vio khac nhau va nhitng gid tj ng6 ra tong ting cia chting . Bat ky sy két hgp nao déu khong duge xéc dinh gid trj 0 cho ngé ra. Dui day Ia vi du : primitive MUX2x1 (Z, Hab, Bay, Sel) ; output Z ; . input Hab, Bay, Sel ; table WHab Bay Sel oO ? 1 0; 1 ? 1 : a 0 2 41 0 Oo x 1oo4 x endtable han Thi M§ Anh ~ Nguyén Pham Xuan ChungNgén ngit Verilog HDL 227 endprimitive Ki ty ? biéu hign m6t gid ui don't-care, 46 1a gid tri 0, L hay x. Thit ty cla cée ngé vao phai twong ting v6i thi uf cba ngO vio trong bing, d6 la, c6t dau tién trong bang twong ting v6i ngé vao dau tién trong module (46 1a Hab) , c6t thif hai la Bay va cOt thif ba Ia Sel.Trong bang kh6ng c6 sy két hgp ng6 vio nao 1a O1x ; trong trung hgp nay ng ra mc dinh 1a x ( cing cho nhitng ngé ra khong xéc dinh khéc ), 4.3 UDP tudn ty: Trong mot UDP tun ty, trang théi bén trong dtc mé td bing céch sit dung mét thanh ghi L-bit. Gi tri cia thanh ghi nay 18 ngé ra cla UDP tudn ty, C6 hai loai khée nhau ca UDP tudn wf, mot 14 mo hinh hanh vi téc dong mie va m6t cdi khéc 14 m6 hinh hanh vi tic dng canh . M6t UDP tuén ty sit dung gié tri hién tai cila thanh ghi va nhitng gid tr ngo vao dé xéc dinh gid wi ké tiép cia thanh ghi. 4.3.1 Thanh ghi trang théi khdi tao: Trang thdi cia mét UDP tun ty 6 thé duye khdi tao bling cach sit dung mt cu Iénh initial ma e6 mét cau Iénh chi dinh thi tye. Day Ia dang: initial reg_name =0, 1 or x; Cau Iénh nay xudt hign bén trong sit dinh nghia UDP. 4.3.2. M6 hinh hanh vi tac dong mite: Du6i day 1a vi du vé mét UDP tudn ty téc dong mic _ma né xay dung mit latch loai D. Khi xung clock 18 0, dit ligu truyén tir ng6 vao dén ng6 ra , ngutge lai gid tr lvu dude chét lai. primitive Lacth ( Q, Clk, D); output reg Q input Clk, D ; table NCk D Q(state) Q(next) o 1 al; O70 1? +5 endtable endprimitive Ki ty “-" nghia la kh6ng d6i. Ché ring trang thai cia UDP duge ‘hau trong thanh ghi Q, 4.3.3 M6 hinh hanh vi tée dng canh : SV:Phan Thi Mj Anh ~ Nguyén Pham Xuén ChungNg6n ngit Verilog HDL 28. Dudi day 18 vi dy vé mot UDP tudn ty tée dong canh_ma n6 xay dung mot flip-flop loai D. primitive D_Edge_FF ( Q, Clk, Data ); output Q; reg G input Data, Clk ; initial Q=0; table HCIk = Data ~~ Q( state ) Q( next ) 1) 0 7 2 0; @D 1 ei, (x) 1 1 ds (Ox) 0 0 05 (20) 2 2 a CD 2 2 endtable endprimitive Dua vao sy dinh nghia UDP 6 trén thi n6 c6 thé duige thé hién trong m6t module ging nhu mot céng co ban hién thi trong vi du ca mét thanh ghi 4-bit sau day: module Reg4 (Clk, Din, Dout ); input Clk ; input [ 0:3 ] Din; output [ 0:3 ] Dout ; D_Edge_FF DLABO ( Dout{0], Clk, Din [0] ), DLABI ( Dout{ 1], Clk, Din [1] ), DLAB2 ( Dout(2}, Clk, Din [2] ), DLAB3 ( Dout{3}, Clk, Din [3] ); endmodule Ta c6 thé tron nhing myc cia m6 hinh téc dong mite va m6 hinh téc Ong canh trong cling mOt bang ( téc dng mie bao trim téc dong canh ). SV:Phan Thi Mj Anh ~ Nguyén Pham Xuén ChungNeg6n ngit Verilog HDL ‘Téng két nhing muc trong bang Ki higu Y¥ nghia 0 Logic 0 Logic 1 ‘Unknown 0, Thay x Ohay 1 - Kh6ng adi (AB) Gié tri d6i tty A sang B 7 Tuong ty (2?) r Tuong ty (01) Tuong ty (10) Jo Joo oe J P (1), Ox) hay (x1)_| A (10), (1x) hay (x0)‘Ngin ngit Verilog HDL Chuong 5 MO HINH DONG DU LIU 5.1 Cau lénh gin lien tiép: Cau lénh gén lién tiép sé gan mot gid trj cho mét net ( n6 khGng duge sit dung dé gan gid trj cho register ). N6 c6 dang sau : assign LHS_taget = RHS_expression ; Khi cau lénh gan lién ti€p dugc thyc thi, bat cit mét suv kign ndo xuét hign trén todn hang 6 vé phai thi cau Iénh sé duge thu thi va n€u gid tri thay 6i né sé duge gan vao ton hang 6 vé tri, Trong cau lénh gén lién tiép thi toan hang & v6 tréi chi 06 thé 6 nhitng dang sau : © Scalar net © Vector net + Hing s6 bit-select cia mt vector + Hing s6 part-select cia mét vector © Két hop cia nhitng kiéu én assign BusErr = Parity | (One & OP); assign Z = ~(A 1B) & (CID) & (EIF); Trong vi du tiép theo, ton hang vé tréi 18 mOt su két hgp cila mot scalar net va mét vector net. wire Cout, Cin; wire [3:0] Sum, A, B; assign {Cout, Sum) = A +B + Cin ; ViA va B rong 4-bit, két qua ciia php cOng t6i da 5-bit. VE trai duige dinh _5-bit ( 1-bit cho Cout va 4-bit cho Sum ), Vi vay cho nén 4-bit thap cla két qua sé dugc gan cho Sum va 1-bit cdn lai ( carry bit )gén cho Cout. Vi dy tiép theo hién thj cich ma nhiéu cau Iénh duge viét trong mot cu Ignh gan lién tigp. assign Day 1a cdch viét rit gon, né twong ty nhu nhitng cau Jénh sau: assign Mu: assign Mur assign Mux = SV:Phan Thi My Anh ~ Nguyén Pham Xuén ChungNgon ngit Verilog HDL assign Mux = (S = = 3) 2D; ‘bz; 5.2 MOt vi dy: Day 1a vi du vé mach cOng dii 1-bit duge mé ta bling céch sit dung mo hinh dng dit ligu : module FA_Df (A, B, Cin, Sum, Cout ) ; input A, B, Cin; output Sum, Cout ; assign Sum=A*B Cin; assign Cout = (A & Cin) | (B & Cin) | (A & B); Trong vi du nay, c6 hai cau lénh gan lién tigp. Nhing cau Iénh nay xdy ra déng thdi va chting dc lap vé thet ty, Nhiing cu lénh nay thyc thi da trén nhitng sy kién xudt hién trén todn tit d vé phai. Néu A thay d6i thi c& hai cu Iénh nay dutge thuc thi, ve phai s® duge tinh ton va gén cho vé tri. 5.3 Lénh gén trong khai bo net: Vi du: wire [3:0] Sum =4’b0 ; wire Clear = ‘bl ; wire A.GT_P=A>B,B_GT_A=B>A; ‘Thay vi phai khai b4o xong mdi thyc hién gén thi 6 day sit dung viée ‘gén trong khi khai béo sé rat gon hon. Vi du: wire Clear = ‘bl; thay vi phai viét: wire Clear ; assign Clear = ‘bl; Néu khong 6 delay xéc dinh trong cau lénh gén liGn tip thi gid tr} delay 14 zero. Mét delay o6 thé xuat hign trong céu Iénh gén lién tiép trong vidu sau: assign #6 Ask = Quiet II Late ; N6u mét sy thay Adi vé gid tri xudt hién trén Late tai thdi diém 5, thi bigu thie vé phdi_ ca cau lgnh dugc tinh todn tai thoi diém 5 va Ask sé duye gan gid tr] méi tai thoi diém 11 (=5 +6 ). Xem hinh 7.1. Quiet... inh 7.1 SV:Phan Thi Mj Anh ~ Nguyén Pham Xuén ChungNgén ngit Verilog HDL 32 Chuong 6 MO HINH HANH VI 6.1 Xy dyng thi tye : Kg thuat chinh cho mé hinh hanh vi ca mot thiét ké 1a hai cau lénh sau day: i, Cau Iénb initial ii, Cau lénh always MOt module 6 thé chia tay § so Iugng cau Iénb initial hay cau lenh always . Nhdng cau Iénh nay thyc thi ding thdi tai thoi diém 0 ma khong phu thudc vao thif ty cila ching. Sy thyfc thi ciia cu lgnh initial hay cfu lénh always sé bit ddu mét dong diéu khign dgc lap. 6.1.1 Cau lénh initial : ‘Mot cau lénh initial chi thyc thi mét dn. N6 bat ddu thyc thi tai thai diém 0 ( thési diém bat ddu m6 phéng ). Cui phép cia céu lénh : initial [timing_control ] procedural_statement (Cau lénh thi tuc ( procedural_statement ) 1a m6t trong nhitng cau Iénh sau: procedural_assignment ( blocking hay non-blocking ) procedural_continuous_ assignment conditional_statement case_statement loop_statement wait_statement disable_statement event_tigger sequential_block parallel_block task_enable (user or system ) Kh6i tudn ty (sequential_block ) 14 khéi “begin end” thi thudng duige sit dung nhiéu trong cau 1énh thi tyc. Véi timing_control cé thé 6 delay, nghia 1a dgi mot thdi gian hay mot diéu khién sy kién ( dgi cho dén khi c6 mOt sy kién xuét hién hay didu kign 1a true ). Sy thue thi cla cu lénh initial 1a 1y do cau Iénh thi tuc thyc thi mt ldn. Chi ¥ ring cu lénh initial thyc thi tai thdi diém 0, n6 06 thé thye thi tr hon ty thuéc vao diéu khién thoi gian dugc thé hign trong cu Iénh thd tue. SV:Phan Thi Mj Anh ~ Nguyén Pham Xuén Chung| Ngén ngit Verilog HDL Vidu: reg Yurt; initial Yurt = 2; Cau IGnh initial chia mét cau lénh gan va khong c6 thdi gian diéu khién. Cu Iénh initial thy thi tai thai diém 0, vi vay Yurt duge gan bing 2 tai thei diém 0. 6.1.2 Cau lenh always: ‘Tréi nguge v6i cau 1énh initial, cau 1énh always lap lai nhiéu Lan. Cling nhv cau 1¢nh initial, cau 1énh always cfing bat ddu thyc thi tai thai | diém 0. Ca phap always [ timing_control ] procedural_statement Vi du: always Clk =- Clk; Vong lap vo han Du6i day 18 mot vi du vé cau lénh always véi mot kh6i tudn af ma duige diéu khign bdi mét diéu khién su kién. reg [0:5 | InstrReg ; reg [ 3:0 ] Accum ; wire ExecuteCycle ; always @( ExecuteCycle ) begin case ( InstrReg [ 0:1] ) 2'b00 : Store ( Accum, InstrReg [ 2:5 ]) ; 2'b11 : Load ( Accum, InstrReg [ 2:5 ]) ; 2°01 : Jump ( InstrReg [ 2:3 ]) ; 2"b10 endcase end // Store, Load va Jump thi duige dinh nghia bai user 18 n6i Khéc. Nhing cau Iénh trong khéi tuan ty thye thi mOt céch tudn ty méi khi 6 m6t su kién xuat hign trén ExecuteReg. "han Thi M¥ Anh - Nguyén Pham Xuén Chung SsNgén ngit Verilog HDL -34- 6.3 Cu lenh khéi: Mot cau Iénh khdi cung c&p m6t ky thuat nhém hai hay nhiéu cau Jenh ma ci phép téc dOng giGng mot cdu Iénh don. C6 hai loai khoi trong Verilog HDL, d6 1a: i Khdi tudn tf (begin... end) : Nhitng cau 1énh thy thi mét céch tudn ty theo thi ty cia n6. ii, Khdi song song ( fork . . . join ) : Nhitng cau lénh nay thyc thi cling ltic véi nhau. MOt khdi 06 thé duge dat nhan mét céch wy chon. Néw e6 nhan duige 43t, nhing thanh ghi o6 thé duige khai_ béo cuc b6 trong khéi., 6.3.1 Khéi tuan ty: Nhiing cu Iénh trong khdi tudn ty thuc thi mOt c4ch tudn ty. Mét gid tai delay trong méi cau Iénh lién quan dén thdi gian thyc thi m6 phéng cila cau lénh truéc, Mét khi kh6i tudn ty hoan tat vige thy thi, sy thyc thi tig tue voi cu lénh ké tiép theo sau khéi tudn ty. Dui day la ct phép cia khéi tuan ty: begin [:: block_id ( declarations ) ] procedural_statement (s) end 6.3.2 Khdi song song: Nhiing cau 1énh trong khdi song song thyc thi dng thoi, Nhing gid tri delay xc dinh trong méi cau Iénh trong khdi song song lién quan dén thdi sian bit ddu thyc thi cila khdi. Khi kh6i thu thi song, cau Iénh ké tiép sau Kh6i sé ti€p tuc thye thi.Cii phép : fork [block_id { declarations } ] procedural_statement (s) join 6.4 C4u lénh gén thi tye: Mot cu Iénh gén thé tuc 14 mOt cau Ignh gén trong cau Iénh initial hay trong cu Iénh always. N6 duge sit dung chi dé gén dén mot kiéu dt ligu thanh ghi. Vé phai ciia cau 1@nh c6 thé 1A mot bidu thie bat ky. Vi dy: reg [1:4] Enable, A, B; #5 Enable = ~A & ~B ; “SV:Phan Thi My Anh — Nguyén Pham Xuan ChungNgén ngit Verilog HDL 35, Enable la mt thanh ghi. Sau 5 don vj thdi gian tht cdu lénh duge thye thi, VE phai cia cdu lénh due tinh todn va gid tri cla no dutge gan cho Enable, Vidu: always @(AorBorCorD) begin : AOL reg Templ, Temp2; Templ =A &B; Temp2 Temp1 end Bon cu I@nh trén cé thé duge thay bling mot cau Iénh : Z=~((A&B)I(C&D)); Tuy nhién 6 day chting ta mudn Jam r6 sy tudn ty trong kh6i. C6 hai logi cau lénh gén thi tye: i, Dang khdi ii, Dang khéng khoi Nhung trudc hét ching ta hay m6 ta vn tft vé delay bén trong cAu 1énh. 6.4.1 Delay bén trong cu I¢nh: Delay nay Lam cho gié trj cila biéu thie bén phai trong cau Iénh bj tr hoan m6t théi gian truée khi n6é due gén qua bén trai. Vi du: Done = #5 ‘bl; Chi ¥ ring biéu thife vé phai duge tinh toan trudc khi delay, Bé hiéu hon vé delay bén trong cu Ignh va delay bén ngoai cdu Iénh thi ching ta hay xem xét vi dy sau day: Done =#5 ‘bl; // Delay bén trong thi tuong ty. begin Temp = ‘bl ; #5 Done = Temp ; // Delay bén ngoai end 6.4.2 Cau lénh gén thi tyc dang khéi: Cau Iénh gén thi tue ma trong 46 todn tit gén 1a“ = "thin 1a cau enh gén thi tuc dang khdi.. Vi du : SV:Phan Thj My Anh ~ Nguyén Pham Xuén ChungNgén ngit Verilog HDL RegA = 52; 14 mot cu 1énh gén thd tue dang khéi. Mt cau Iénh gén thd tuc dang khéi thyte thi trutée khi cu I@nh ké tiép duoc thyc thi. 6.4.3 Cau lénh gan thii tue dang khong khéi: Trong céu Iénh gén thi tuc dang khdi, todn uf gén dién hinh la “<=”, Vi du: end Trong cfu Iénh gén thi tue dang khong khGi, vige gén dén muc tiéu thi Khéng bj ngain can nhung n6 duge hen gid dé xuat hién trong tong lai. Khi cu lénh gén thi tue dang khéi thufc thi, biéu thite vé phai duge tinh toan Va gid tri cila n6 duye hen gid dé gan qua vé tréi va su thu thi tiép tuc v6i cau lénh ké tiép. Ngo ra sé duc hen gid tai du cudi cla bude nhdy thai gian hign hanh; trudng hop nay sé xudt hién néu kh6ng 6 delay trong cau Jénh gén. Tai dau cudi cita bude nhdy thdi gian hign hanh hay bat ky ndi nao ‘ma ng6 ra duge hen gid, vige gén sang vé trdi sé duige thy thi. 6.44 Cau lénh gén lién tip va cu Iénh gén thé tue: Su khéc nhau giita hai cau lénh: Cau Iénh gén thie | Xudt hign bén trong cau lénh | Xudt hién bén trong module always hay cu Iénh initial. Thye thi theo thi tyciané | Thye thi dng thdi cing cde cau Ignh khéc; thue thi bat cif Khi ndo c6 mot suf thay déi vé gid tri cia todn hang bén vé phai ciia nd. Diéu khién nhing thanh ghi Diéu khién nhing net Sit dung toan ti “= " hay “ <=] Sitdung toan ti =” * wong cau Iénh Kh6ng ding ti’ khod assign —_| Sit dung tir khod assign 6.5 Cau lénh diéu kign: Cé php cia cau lénh if : if( condition_1) _SV:Phan Thi My Anh - Nguyén Pham Xudn ChungNgén ngit Verilog HDL 37 procedural_statement_1 elie if ( condition_2) procedural_statement_2 else procedural_statement_N NEw condition_1 c6 gid tri 1 thi procedural_statement_I thu thi. Néu condition_I c6 gid trj 0, x hay z thi procedural_statement_1 khéng dude thife thi vA m6t nhénh khée néu tn tai sé thie thi. 6.6 Cau lénh case: Cai phap: case ( case_expr ) case_item_expr{, case_item_expr } procedural_statement [default : procedural_statement } endcase Cu lénh case hoat dong dya vao case_expr, biéu thife nay duige tinh todn ,sau d6 biéu thtic case_item_expr xéc dinh gi va so sinh véi case_expr. Nhing cau lénh thich hgp sé dude thyc thi. 6.7 Cau lénh lip: C6 4 loai cia cau [enh lap: i, Cau lénh lap Forever ii, Cau Iénh lap Repeat iii, Cau lénh lap While iv. Cau Iénh lp For 6.7.1 Cau lénh lip Forever: Cu phap: forever procedural_statement Cau Iénh lap nay thye thi cdu Iénh procedural_statement mét cach lin tue. Vi vay mudn thodt ra khoi vong lap ta cdin phdi c6 mOt cu lénh ngat duge sit dung vdi cau lénh procedural_statement. Ngoai ra, c6 mot vai dang diéu khién thdi gian cin phai dugc sit dung trong c4u Iénh procedural_statement, néu khong thi vong lip forever sé Lp mai mai, 6.7.2 Cu lénh lip repeat: SV:Phan Thj Mj Anh - Nguyén Pham Xuén ChungNgén ngit Verilog HDL Cau lgnh lap repeat cé dang: repeat ( loop_count ) procedural_statement Su thye thi cfu Iénh thi tye duge xac dinh bai sé Kan loop_count. Néu loop_cunt la x hay z thi né dutgc xem 1a 0, Du6i day 18 m6t vai vi du: repeat (Count ) Sum = Sum +10; repeat ( ShiftBy ) P_Reg=P_Reg<<1; Cau lénh lap repeat khac véi diéu khién su kién repeat. Hay xem: repeat ( Count ) // Cau Iénh lip repeat @( posedge Clk ) Sum =Sum + 1 ; nghia 1a Count 1A s lan Lip, doi cho canh lén ciia Clk xudt hién thi ting Sum 1én 1 don vi. Noung ngugc lai Sum = repeat ( Count ) @ ( posedge Clk ) Sum +1; ngbia 1a tinh Sum + 1 truéc, sau 46 dgi s6 lén Count cia canh 1én trén Clk thi gan cho Sum. 6.7.3 Cau Iénh Kip while: Cui phap : while( condition) procedural_statement Vong lap thyc thi cau lénh thi tue cho dén khi diéu kign duge xée dinh 1a false. Néu ngay d4u tién bigu thifc 1a false thi cu Iénh thi tuc khéng bao gid thye thi, Néu digu kién 1a x hay z, thi né duge xem Ia 0 ( false ). 6.7.4 Cau Ienh lip for Cau lénh c6 dang ; for ( initial_assigment; condition; step_assignment ); procedural_statement Cau Iénh nay sé lap lai sy thyc thi cdu lénh thi tye theo mét s6 Kin nhét dinh nao 46, Phin ti initial_assigment xéc dinh gié tri ddu tién cla chi sO lip. Phan tit condition x4c dinh diéu kién khi nao vong lap ngiing. Khi diéu kién 1a true, cau Iénh trong vong lap duge thyc thi. Phdn ti step_assignment x4c dinh sy thay adi, 1a tang hay gidm s6 lin nhay. SV:Phan Thi M§ Anh ~ Nguyén Pham Xuan ChungNgén ngit Verilog HDL -39- 6.8 Céu lenh gén lien tiép tha tue M6t cau lénh gan lién tigp thd: tuc 1a mot cau Ignh gan thi tuc, ma né xudt hign bén trong cu lénh always hay trong cu Iénh initial. Cau lénh gan nay c6 thé chéng 1én nhiing céu lénh gan khéc dén m6t net hay mot register. Né cho phép biéu thie trong cau lénh gén diéu khién mot céch lién tiép trong mt net hay mt register. Chit ¥ rling n6é khOng phai 1a mOt cu Iénh g6n lién tiép ; mOt cu Ign gén lién tiép xudt hign ngoai cau Iénh initial hay cau Iénh always C6 hai i ciia céu Iénh gén lién tiép thi tue : Cu lénh thi tuc assign va deassign ; tac d6ng dén thanh ghi. ii, Cau leah thd tue force va release : téc déng chi yéu dén net mac di chiing ciing dug sit dung cho thanh ghi. Cau Iénh gan lién tiép thi tuc khong gan gid tri dén part-select hay bit-select. 6.8.1 assign-deassign: ‘M6t cu lénh thi tuc assign tac dong chdng lén tat cd nhitng cau lénh thi tue dén thanh ghi. Cau Jénh thi tyc deassign két thie cau lénh lién tip 4€n m6t thanh ghi. Gié trj trong thanh ghi due Iwu gidt cho dén khi né duge gén gid tri khéc, 6.8.2 Force-release: cau lénh force va release ciing rt giGng cau lénh assign va deassign, ngoai tri force va release c6 thé ting dung cho net va déng thdi ciing t6t cho thanh ghi. _SV:Phan Thj My Anh - Nguyén Pham Xudn ChungNgén ngit Verilog HDL Chuong 7 MO HINH CAU TRUC M6 hinh cfu tric due mé td sit dung: * Sythé hién nhiing céng © Sy thé hign nhiing UDP © Suthé hin module Trong nhting chuong trudc ta di m6 ta vé m6 hin mic céng va m6 hinh UDP. Trong chuong nay ta sé mé td vé module, 7.1 Module: C6 dang: module module_name ( port_list ) ; Delaration_and_statements endmodule Nhiing port thong qua module truyén théng véi nhiing module bén ngoai. 7.2 Ports : M6t céng c6 thé duye khai b4o nhw I ng6 vao , ng6 ra hay ngo vio ra. M6t cng c6 gid tri mic dinh 18 m6t net. Tuy nhién, n6 6 thé dug Khai ‘béo mét céch linh hoat nhy 1a mét net. M6t céng ra hay eng vao ra cé thé tuy chon dé duge khai béo lai nhw 1a mét thanh ghi kiéu reg. Trong mdi suv khai bao thanh ghi hay net, net hay thanh ghi can phai c6 kich thuéc nhu mot suf xc dinh trong khai b4o céng. Vidu: module Micro ( PC, INstr, NextAddr ) ; Khai béo céng input [3:1] PC; output [1:8] Instr ; input [16:1] NextAddr ; wire [16:1] NextAddr ;// NextAddr duge khai bao lai. reg [1:8] Instr ; /* Instr duge khai béo lai nhu 14 mét thanh ghi kiéu reg 48 n6 06 thé duge gén gid tri trong cau lénh initial hay cau lénh always */ endmodule SV:Phan Thi Mj Anh - Nguyén Pham Xuan Chung‘Ngdn ngitVeriog HDL ~al- 7.3 M6 ti module: Mét module 06 thé duge mé ta trong mét module khéc. Mot cau Iénh thé hién module c6 dang: module_name instance_name( port_associations ) ; trong d6 port_associations ¢6 dang: port_expr 11 bing vi tet -PortName (port_expr) // bling tén trong d6 port_expr c6 thé 1a nhiing dang sau: i, Thanh ghi hay ‘net ii, M@tbit-select iii, M6t part-select iv. MOt sy tron lin trong nhiing dang tren ¥. Mét biéu thtte ( chi cho nhing céng nhap ) vi. 7.3.1 Nhiing cOng khong két ndi: Nhitng céng kh6ng két n6i duige xdc dinh bing céich cho phép khoang trdng trong biéu thitc céng, nhu dang sa DFF dl ( .Q(QS), .Qbar(), Data(D), .Preset(), .Clock(CK) ) ; // theo tén DFF d2(QS, ,D, , CK) ; / theo vi tri // ng6 ra Qbar khéng duge két n6i // ngO vao Preset mé va vi vay 06 gid tri z. Ng6 vio module khéng duge két néi thi duge diéu khién dén gid ti z. Ng6 ra module khéng duge két néi thi don gidn 1A khéng sit dung. 7.3.2. Chiéu dai cdng khéc nhau : Khi m6t cdng va biéu thtic c6ng cyc b6 khdc nhau vé chiéu dai, céng thich hgp duge thye hign bing céch ct cut hay x4p cho diing thf ty tir bén phai. Vi du: module Child( Pba, Ppy) ; input [5:0] Pba ; output [2:0] Ppy ; endmodule module Top ; wire [1:2] Bdl ; SV:Phan Thi Mj Anh — Nguyén Pham Xudn Chung‘Ngén ngit Verilog HDL 42. wire [2:6] Mpr ; Child C1( Bdl, Mpr) ; endmodule Trong module Child : Bdlf2] dude két n6i dén Pba{0] va Bdl(1] duge két ni dén Pba[l]. Nhiing céng nhgp cdn lai, Pba[5], Pba{4], Pba[3) thi khong dufge két n6i vi vay ching c6 gid tri z. Tuong ty, Mpr[6] thi duge két n6i Ppy[0], Mpr[5] thi duge két n6i dén Ppy{1] va Mpr[4] dude két néi dén Ppyl21. 7.3.3, Nhitng tham bién trong module: Khi m6t module duge thé hién tong m6t module khéc, module & mite cao hon cé thé thay di gid tri cia tham bién trong module thap hon. C6 hai cach thyc hién diéu nay: i, Cau Iénh defparam ii, Gan gié trj cho tham bién Cau Iénh defparam: defparam hier_path_namel = valuel, hier_path_name? = value2, ... ; Nhiing tén dutting diin thit bac cia tham bién trong module thp hon ob thé dat bing céch sit dung nhu mt cau Iénh . Vi du: module TOP( NewA, NewB, NewS, NewC ); input NewA, NewB ; output NewS, NewC ; defparam Hal.XO_DELAY = 5; Hal.AND_DELAY = HA Hal( NewA, NewB, NewS, NewC ) ; endmodule SV:Phan Thi Mj Anh ~ Nguyén Pham Xuén Chungthigu vé cée phén mém hé trg va FPGAs 4B Phén It GIGI THIRU VE CAC PHAN MEM HO TRO VA FPGAs 11 Gidi thigu vé phan mém Synario 4.1: Phan mém Synario duge sit dyng nhiéu trong céc ng6n ngit Ip tinh nhu VHDL, Verilog HDL, ABEL, vé so d6 thiét k€ mach. Sau day Ia mot s thao téc sit dung trong méi truting Synario 48 viét chuong trinh bling ng6n ngit Verilog. Diu tién vao méi trudng Synario : trén menu program, chon Synario, méi_ truing Synario Project Navigator xudt hign va sin sing am viée trong méi trudng nay: M6 mét project: Trong menu fie chon open project, hp thoai xudt hign chon thy muc va file mudn md. Tao mot project méi: True khi tao file verilog module ta tao mét project méi. Tir mi truing Synario Project Navigator vio menu file chon new project thi hop thoai xudt hién: SV:Phan Thj My Anh - Nguyén Pham Xuén ChungGi6i thigu vé cdc phdn mém hé trg va FPGAs 44-Gidi thigu vé cdc phn mém hé trg va FPGAS 45 Sau d6 vio menu source chon new: Chon Verilog Module h6p thogi tigp theo xudt hién: Ceres Dat tén cho module va file sau dé 1a viét chuong tinh, Sau khi viét song file.v nay ta tigp tuc tao file.tf dé kiém tra file.v nay. Dé tao file.tf ta 1am nhy sau: chon new source: SV:Phan Thi My Anh - Nguyén Pham Xuén ChungGidi thigu vé cdc phdn mém hé tr va FPGAs -46- Sau d6 chon Verilog Test Fixture, hp thoai tiép theo xudt hién: SV:Phan Thi Mj Anh ~ Nguyén Pham Xudn ChungGidi thigu vé cde phén mém hé trg va FPGAs 7 Ta chon file.v can test sau d6 dat tén cho file.tf nay: Sau dé thy hign vige viét file nay. Sau khi da viét song ta thy hién compiler cho chuong tinh bing céch chon file.tf -> nhép dup vao Verilog Functional Simulation hop thoai sau xudt hién: SV:Phan Thi Mj Anh — Neuyén Pham Xudin Chungthiéu vé cdc phan mém hé trg va FPGAs - 4 Sau 46 chon Run, tiép theo vio Window->Waveform Viewer lap tite hp thoai sau xudt hién cho phép chon tin higu ma ban mu6n hién thj: Hay ban cé thé vao Window->Simulator Transcript dé xem két qua, Sau day 1a mét vi dy sit dung ng6n ngi verilog dé viét chudng trinh m6 phéng mét mach céng dit 1 bit: Day la file.v: module FA_Seq(A, B, Cin, Sum, Cout ); input A, B, Cin; output Sum, Cout; reg Sum, Cout; reg Tl, T2, T3; always @( A or B or Cin) begin SV:Phan Thi My Anh - Nguyén Pham Xuan ChungGidi thigu vé cdc phén mém hé trg va FPGAs 49 Sum =(A*B) Cin; TI=A &Cin; T2=B&Cin; T3=A&B; Cout = (T11T2)1T3; end endmodule Con day 1a file.tf: “timescale Ins/Ins module Top; reg PA, PB, PCin; wire PCo, PSum; FA_Seq F1(PA, PB, PCin, PSum, PCo); reg [3:0] Pal; initial begin W need 4bit so that Pal can have the value 8 for (Pal = 0; Pal <8 ; Pal = Pal + 1) begin (PA, PB, PCin) = Pal; #5 Sdisplay (" PA, PB, PCin = %b%b%b", PA, PB, PCin, ":xPCo,PSum=%b%b", PCo,PSum); end end endmodule SV:Phan Thi Mj Anh — Nguyén Pham Xuan Chung