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Karnaugh Mapsss
Karnaugh Mapsss
Objectives
This section presents a technique for simplifying logical
expressions. It will:
Define Karnaugh and establish the correspondence between
Karnaugh maps and truth tables and logical expressions.
Show how to use Karnaugh maps to derive minimal sumof-products and product-of-sums expressions.
Introduce the concept of "don't care" entries and show how
to extend Karnaugh map techniques to include maps with
don't care entries.
Reading Assignment
Elec 326
Karnaugh Maps
Z A
0
B
0 0
1
1
0
Type 2 Map
Type 1 Map
Two-Variable Maps
AB C Z
0 00 0
0 01 1
0 10 1
0 11 0
1 00 1
1 01 0
1 10 0
1 11 1
Truth Table
Z A
B,C
0
00 0
1
1
01
11
10
Type 1 Map
Type 2 Map
Three-Variable Maps
Elec 326
Karnaugh Maps
A
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
C
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Z
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
1
D
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Z A,B
C,D
00 01 11 10
00 0 0 1 0
01 0
11 1
10 0
B
Type 1 Map
Type 2 Map
Four-Variable Maps
Truth Table
Elec 326
Karnaugh Maps
A
D
C
B
A=1
region
A
D
B
B=1
region
A
D
B
C=1
region
B
D=1
region
Elec 326
Z A
0
B
0 0
1
2
Z A
B,C
0
00 0
1
4
Z A,B
C,D
00 01 11 10
00 0 4 12 8
01
01 1
13 9
11
11 3
15 11
10
10 2
6 14 10
Karnaugh Maps
= ABC'D' + (A'+B')(C+D)
= ABC'D' + A'C + A'D + B'C + B'D
Elec 326
Karnaugh Maps
The labels for the type 1 map must be chosen to guarantee this
property.
Elec 326
Karnaugh Maps
A
0
= (A'+A)BC'D
= 1BC'D
= BC'D
A'
B
C'
D
A
B
C'
D
= m5 + m13
= A'BC'D + ABC'D
B
C'
D
Example
A B C'
A' C D
C
Elec 326
Karnaugh Maps
A
0
Z=
=
=
=
=
=
Elec 326
m5 + m7 + m13 + m15
A'BC'D + A'BCD + ABC'D + ABCD
(A'C' + A'C + AC' + AC) (BD)
(A'(C' + C) + A(C' + C)) (BD)
(A' + A) (BD)
BD
Karnaugh Maps
Z3
Z5
C
B
Z2
Z4
A
1
1
1
Z6
A
1
1
B
Elec 326
C
B
Karnaugh Maps
Z8
Z9
Z10
1
1
1
C
Elec 326
Z12
B
A
1
A
1
Z14
1
D
1
B
10
A
1
Z13
C
B
B
Z11
D
C
1
D
1
B
Karnaugh Maps
Z15
Z16
Z17
1
1
D
C
C
B
Elec 326
1
B
11
Z20
A
1
Z19
A
1
Z18
A
1
1
B
Karnaugh Maps
Elec 326
Karnaugh Maps
loop 1
D
C
loop 2
D
Violates Rule 1
Violates Rule 2
Elec 326
13
Karnaugh Maps
implicant.
cell.
Examples:
#1
C
#4
Elec 326
#2
B
14
#3
Karnaugh Maps
#4
C
#3
#2
#5
#3
#4
D
C
#1
A
1
#5
a. Non-minimal
Product Terms
#2
#3
D
C
#1
A
1
#4
#2
D
#1
b. Non-minimal Selection
of Prime Implicants
c. Minimal
Grouping
a. Z = ABD+AB'C'+A'BC'+A'CD+A'B'D'
b. Z = BD+AB'C'+A'BC'+A'CD+A'B'D'
c. Z = BD+AB'C'+A'C'D'+A'B'C
W3
W3
D
C
a. W3 = C'D+AC'+BC+A'B'D'
b. W3 = BD+AB+B'C'+A'CD'
Elec 326
15
Karnaugh Maps
D
C
Elec 326
16
Karnaugh Maps
A
1
A'
B'
C'
A
B'
C'
B'
C'
OR-AND Networks
Karnaugh Map
M3M7 = (A+B'+C')(A'+B'+C')
= (AA')+(B'+C')
= 0 + (B'+C')
= B' + C'
Elec 326
17
Karnaugh Maps
Prime Implicate:
Elec 326
18
Karnaugh Maps
Examples:
Z B'+C+D
A+D'
A'+B+C'+D
Z = (A+D')(B'+C+D)(A'+B+C'+D)
Z1
Z2
D
C
Z1 = (A+B'+D)(B+C+D')(A+B+D')
Z2 = D'(A+B')(B'+C')
Elec 326
19
Karnaugh Maps
Z1
A
1
D
C
A
1
Z1 = (A+B')(A+D')(B'+D')(A'+B+C)
Z1 = (ABD') + (AB'C) + (A'B'D')
Elec 326
20
Karnaugh Maps
10
A
1
A
1
B
D
1
D
C
Elec 326
21
Karnaugh Maps
C
B
C
B
C
B
Z = B'+A'C Z = AB'+B'C'
Z
A
0
D
C
A
1
Z = BC + AD'
Elec 326
Z = B'
Z = (C+D')(A'+B')
22
Karnaugh Maps
11
Elec 326
23
Karnaugh Maps
0
1
D
3
2
12
B
8
7
6
13 9
E
15 11
14 10
B
16 20 28 24
17 21 29 25
E A
D 19 23 31 27
18 22 30 26
B
0
12 8
13 9
15 11
14 10
C
B
16 20 28 24
E
D
17 21 29 25
19 23 31 27
18 22 30 26
C
A
Elec 326
24
Karnaugh Maps
12
Six-Variable Maps
C
12 8
1
5 13 9
F
3
7 15 11
E
2
6 14 10
0
C
16 20 28 24
17 21 29 25
F
E 19 23 31 27
18 22 30 26
12 8
13 9
15 11
16 20 28 24
17 21 29 25
F
E
14 10
D
18 22 30 26
D
33 37 45 41
A
49 53 61 57
35 39 47 43
48 52 60 56
32 36 44 40
C
48 52 60 56
49 53 61 57
F
E 51 55 63 59
50 54 62 58
19 23 31 27
34 38 46 42
F A
51 55 63 59
50 54 62 58
D
C
32 36 44 40
33 37 45 41
F
E 35 39 47 43
34 38 46 42
25
Karnaugh Maps
Examples.
Z
E
BE
C
A
Z = B'C'E'+BE
Z
C
A
Elec 326
26
Karnaugh Maps
13
C
A
Z = (B+C)(B+E(A'+D+E)(A+C+E)
Z
C
A
Z = BC + D
Elec 326
27
Karnaugh Maps
Timing Hazards
Exercise: Draw a timing diagram for the following
circuit assuming an equal unit delay for each gate.
X
A
B
A
B
X
Y
Elec 326
28
Karnaugh Maps
14
Static 1 hazards
A=1
S
P
NS
B=1
S
P
NS
Q
Z
Elec 326
29
Karnaugh Maps
Elec 326
The hazard occurs when the output is 1 before and after the
transition.
It happens because one of the AND gates is holding the
output 1 before the transition and the other AND gate holds
it 1 after the transition. The spike occurs if it is possible for
the first to turn off before the second turns on.
This can happen anytime there are to adjacent squares on
the Karnaugh map that are both 1 and not both covered by
a common loop. The hazard occurs in making a transition
from one square to the other.
The way to prevent it is to put in an extra product term that
is 1 on both sides of the transition. On the Karnaugh map
this is a loop covering the two adjacent one squares.
30
Karnaugh Maps
15
Elec 326
31
Karnaugh Maps
Static 0 hazard
S
A=0
S
P
NS
B=0
A
S
A
0
Elec 326
32
Karnaugh Maps
16
Elec 326
33
Karnaugh Maps
17