--------------------------------PWM entity PWM is Port( CLK: in Std_Logic; RST: in Std_logic; PWM: out Std_logic; DPS: in Std_Logic_Vector(7 downto 0) ); end PWM; architecture Behavioral of PWM is Signal Ta: integer range 0 to 255; Signal Contador: integer range 0 to 255; begin Process(CLK) Begin If(Rising_Edge(CLK)) then IF (RST='0') Then //Hacer Reset Else Programa End If; End If; End Process; end Behavioral;