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Module-1 Digital and Analog Signals: CS2201 Switching Circuits and Logic Design
Module-1 Digital and Analog Signals: CS2201 Switching Circuits and Logic Design
Module-1
DIGITAL AND ANALOG SIGNALS
An electrical signal can be defined as the variation of electrical quantity i.e
voltage or current with respect to time.That means the signal which does not vary with
respect to time is not a signal.For example D.C is constant with respect to time even
though it is a signal.
Fig:Analog Signal
An analog signal is a signal which takes any value from the given by taking the values
of electrical signal at different time intervals.
A system can be defined as a physical device that performs an operation on a signal.
Signals can be categorized in various ways:for example, discrete time signals and
continuous time signals.Even when the signal functions are not continous,continuous
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Module-2
NUMBER SYSTEM
Digital
System
Analog in
Computer
Analog out
a-1 = 7
a-2 = 1
a-3 = 2
a-4 = 3
Binary numbers:
The binary number has a radix of 2. As r = 2, only wo digits are needed.These are 0 and
1.For the decimal system, radix is 10 which needs 10 digits.
Example:The decimal equivalent of the binary number 101010
N = (101010)2
= 1X25+0X24+1X23+0X22+1X21+0X20
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For N symbols to be represented, the minimum no.of bits required is the lowest
integer r that satisfies the relationship
2r > N
For example If N=26, minimum r is 5 since 24=16 and 25=32
Octal numbers:
Octal systems use a base or radix of 8.Thus it has digits from 0 t0 7(r-1)
Ex:- The decimal equivalent of the octal number 15.2
N = (15.2)8
= 1X81 + 5X80 + 2X8-1
= 13.25
Hexadecimal numbers:
The hexadecimal numbering system has a base of 16.There are 16 symbols.The
decimal digits 0 to 9 are used as the first ten digits in the decimal system, followed by
the letters A,B,C,D,E,F which represents the values 10,11,12,13,14 and 15 respectively.
Below table shows a relatioship between decimal, binary, octal and hexadecimal
number systems.
Binary
Octal
Hexadecimal
0000
0001
0010
0011
0100
0101
0110
0111
1000
10
1001
11
10
1010
12
11
1011
13
12
1100
14
13
1101
15
14
1110
16
15
1111
17
1 ---- LSD
2 5
2
2
2
1
1
0
1 ----- MSD
a-1 = 1
0.5708X2=1.1416;
a-2=1
a-3=0
0.2832X2=0.5664;
a-4=0
For converting a binary number to octal, the following procedure can follow
1. Group the no.of bits into 3s starting at least significant symbol. If the no.of bits
are not evenly divisible by 3, then add os at the most significant bit.
2. Write the corresponding 1 octal digit for each group
Ex: 100
4
010
2
011
For converting a binary number to hexadecimal, the following procedure can follow
1. Group the no.of bits into 4s starting at least significant symbol.If the no,of bits is
not evenly divisable by 4, then add 0s at the most significant end.
2. Write the corresponding 1 hex digit for each group.
Ex: 1001
9
1110
E
0111
0000 (binary)
0 (hexadecimal)
Assignment:
Convert any given decimal number into a binary form.
Module-3
LOGIC GATES
Digital signal takes discrete level, we realize this by taking switch as an example on and off
represents two different states in the case of switch. If we have two level signal than we call it as
binary signal. We can convert analog signal into digital signal by using analog to digital converter. We
can represent the output signal in analog to digital converter by using multiple bits
In case of switch or in binary signals we represent ON state as 5V OFF state as 0V.
0V 0 level
Nominally
5V1 level
TYPES OF LOGIC:POSITIVE LOGIC;If 0 level represents low level and 1 level represents high level than we call such type of logic as
positive logic.
Level 0 0v or -5v
Level 1 5v or 0v
1 level value of the variable is greater than the 0 level value.
NEGATIVE LOGIC :If 0 level represents high value and 1 level represent low value than we call such type of logic as
negative logic.
Level 0 5v
Level 1 0v
1 level value of the variable is less than the 0 level value.
i.e 0 level 1 < 5 level 0
CS2201 Switching
witching Circuits and Logic Design
system always work on signals.
nals. We can develop systems with the help of subsystems. Subsystems contain
modules as basis. Each module contain several function, contain logic level.
The hierarchy diagram is
systems
Subsystems
Modules
Functions
Logic levels
2.SEQUENTIAL FUNCTION:Output values are depends on the current inputs and past outputs. Memory element is required to
store the previous output. Sequential logic contains combinational logic also.
BASIC COMBINATIONAL BULDING BLOCK:Basic combinational building block in digital circuits is logic gates.
LOGIC GATES;A logic gate is an electric circuit that performs a particular logic function. Logic gates
have one or more inputs terminals and one output terminal. Each input terminals represents an
independent variable. At any given instance of time every terminal is one of the two binary
conditions as high or low. In most logic gates, low state is approximately 0 or high state is 5v.
Logic gates are different types depending upon the logical function preformed by the gate.
The different types are AND, OR, NOT, NAND, NOR, XOR, XNOR, gates.
AND GATE:The output is true if both inputs are true. Other wise the output is false.
SYMBOL:- the symbol of AND gate is given below
OR GATE:The output is true when one of the input is true and when the both inputs are true other wise the
output as false.
SYMBOL:-
TRUTH TABLE
A
TRUTH TABLE:A
NAND GATE;It has two or more inputs terminals and one output terminals. The output is an inversion of
output of AND gate. If A and B are inputs, output is NOT (A and B)
SYMBOL
TRUTH TABLE
NOR GATE;It has two or more input terminals and one output terminal. The output of a NOR gate is an
inversion of the output of an OR gate i.e, if A and B are the inputs the output is NOT (A OR B)
SYMBOL;
TRUTH TABLE;A
TRUTH TABLE
A
EX-NOR GATE;It has two or more inputs terminals, and one output terminal. The output of EX-NOR gate is an
inversion of output of an EX-NOR gate. i.e, if A and B are the inputs and the Output of and EX-NOR
gate is NOT (A+B)
SYMBOL;
TRUTH TABLE
A
Module-4
Universal Gates
Both NAND and NOR gates are called as universal gates , because we design any gate by
using any one of the two gates. First of all we see the construction of AND, OR, NOT, XOR, XNOR
gates by using NAND.
In the
implementation of NOT using NAND we have to take only one input A.
Eliminate 2 and 3 rows from the NAND truth table and make B=A. we get NOT gate.
AND
We get AND with the help of NAND by inverting the output of the NAND gate.
Replace NOT gate with equivalent NAND then we get AND gate.
The truth table of the above circuit diagram is same as AND gate.
0R
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NOR GATE
Invert output of OR then we can get NOR gate by using NAND gate.
The truth table of OR and NOR as same as previous. Because now we are constructing these gates
by using NAND GATE
X-OR GATE
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X-NOR GATE
Inverting X-OR gives X-NOR gate.
NOR
A
NOT GATE designing;Remove 2 and 3 and make B=A and give A as input to NOR then we get NOT gate as the output
TRUTH TABLE
A
0
AND GATE:We design AND gate using NOR by inverting the both inputs A and B to the NOR gate.
MODULE -5
BOOLEAN ALGEBRA
1. Boolean algebra works with binary variables.
2. A Boolean algebra is an algebraic system consisting of the set {0,1} the binary operations called
OR,AND,NOT and denoted by the symbols "+","." and "prime" respectively.
3. Boolean algebra enables the logic designer to simplify the circuit used achieving economy of
construction and reliability of operation.
4. Boolean algebra suggests the economic and straight forward way of describing the circuitary used in
any computer system.
5. Boolean algebra is unique in the way that , it takes only two different values either 0 or 1
a. it doesn't have negative number.
b. it doesn't have fraction number.
6. the basic boolean postulates
a. logical multiplication based on AND function.
* 0 . 0 =0
* 0.1= 0
* 1 .0=0
* 1.1=1
* 0 +1 =1
*1+0 =1
*1+1= 1
* 1 = 0.
7. boolean properties.
a. properties of AND function
1. x . 0 = 0
2. 0 . x = 0 3. x . 1 = x
4. 1 . x = x.
b. properties of OR function.
5. x+ 0 =x
6. 0 + x = x 7. x + 1 = 1 8. 1 + x = 1 9. 0 + =
11. x . x = x
12. x + x = x
13. X + x = 1
14. X = x
d. commutative laws.
15. x . y = y . x
16. x + y = y + x
e. distributive laws.
17. x(y+z) = x.y + x.z
f. associative laws.
19. x(y.z) = (x.y)z
g. absorption laws
21. x+xy=x
22. x(x+y) =x
23. x+ x y = x+y
h. demorgans laws.
25.(x+y) = x . y
26. (x.y) = x + y
[ 1+ Z = 1 ]
[1+Y= 1]
= X + YZ = L.H.S
22. X+ XY = X+ Y
L.H.S = X + XY
=(X + X)(X+Y)
=X+Y = R.H.S
23. X(X + Y) = XY
LHS = XX + XY = 0 + XY = XY =RHS
9. logics circuits can be simplified by simplifying the boolean equation using any one of the following
methods :
a) applying boolean properties.
b) karnaugh map method of simplification
c) tabulation method
10. The properties of boolean algebra are useful for the simplification of boolean equation leading to
minimum structure.
11. simplify the boolean equation Z = XY + X (X+Y)
XY + X (X+Y) = XY + XX + XY
= XY + XY
= (X+ X) Y = Y
DUALITY PRINCIPLE : The important property of boolean algebra is the duality principle.
It states that every algebraic expression deducible from theorems of boolean algebra remains valid if the
operators and identify elements are interchanged.
EXAMPLES:X+X=X
X.X= X
X+1=1
x.0= 0
X + x y= x
x(x +y)=x
X + y= y + x
xy=yx
BY duality
by duality
by duality
by duality
X (YZ)= (XY) Z
By duality
12. Standard product or minterm (M): consider two binary variables x and y combined with
an AND operation. Since each variable appears in direct form or in its complement form there are
four possible combinations X Y, X Y, X Y and XY. Each of these four AND terms is called a
minterm or a standard product.
X
MINTERM
XY
m0
XY
m1
m2
1
1
0
1
XY
XY
m3
Standard sum or Maxterm (M): Two binary variables X and Y combined with an OR operation we will
an OR operation we will get four possible combinations X+Y, X+, +Y and +. Each of these four
OR terms is called a Maxterm or a standard sum term.
X
0
Y
0
Maxterm
(M)
M0
X+Y
M1
X+
M2
+Y
M3
+
Each Maxterm is the compliment of its corresponding minters and vice versa.
Eg: - XY = Minterm
The compliment of minterm = (XY) = + = Maxterm
X
0
0
1
1
Y
0
1
O
1
F
0
1
1
1
F(X, Y) = X + Y = m (1, 2)
This representation is called SSOP form. minterm or product of maxterm are said to be canonical form.
3. Sum of products form can be implemented by using NAND NAND realization.
4. NAND-NAND realization is same as AND OR.
5. Product of sums form can be implemented by using NOR- NOR realization.
6. NOR NOR realization is same as OR - AND.
7. If the signals are propagating through two stages of gates, then it is called two level gate network.
DEGENERATIVE FORM: A two level gate network is said to be degenerative if it degenerates
to a single operation. The following two level gate networks are degenerative.
Forms:
AND-AND
OR-OR
AND
OR
OR -NOR
NOR
NOR -NAND
OR
NAND -NOR
AND
AND -NAND
NAND
the minimal
algebra
We are not sure that the given function or logical circuit is in its simplest form. It is possible to
design a circuit having less number of gates and inputs to realize the same function , then it saves
hard ware. Reduction at gate level is important.
*Characteristic table of given function;
IN PUTS
OUTPUT
F(A,B,C)
They are:-
F ( A, B, C ) = A B C + A B C + A B C + AB C + ABC
= m(2,4,5,6,7)
(SOP)
NOTE; Reduction means reducing the number of terms and number of variables in each term. Our
goal is to make it as minimum sum of products beyond which we can not reduce further
F ( A, B, C ) = A B C + A B (C + C ) + AB (C + C )
= A B C + A B (1) + AB (C + C )
= A B C + A B + AB
= A B C + A( B + B )
= A B C + A(1)
= A B C+ A
= ( A+ A)( B C + A)
= (1)( B C + A)
= B C+ A
F ( A, B, C ) = A B C + A B C + A B C + AB C + ABC
= A B C + AB C + A
Alternative:-
= ( A+ A) B C + A
= B C+ A
= A + BC
we can use the minterms for which the output is false i.e 0. To
realise the function instead of using minterms for which the output is true i.e 1. Complement of the
function ( F ) is the sum of minterms for which the output is false i.e 0.
From this we can realize that the given function is the product of max terms for which output is false i.e
0.
For max terms 0-variable ; 1- complement of variable.
A + B + C (000) M 0
A + B + C (001) M 1
A + B + C (011) M 3
Module-6
Simplification of Boolean functions
Map method of Boolean simplification
KARNAUGH maps( K-maps):
A BC 00
0
1
01
11
10
[ = 0][A=1]
Adjacency Rule:
Allowing only one of the variable to vary from one cell to neighbor cell in
horizontal and in vertical direction, but not diagonally
In the map we are denoting 11 after 01 because of adjacency rule.
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A
First min term m0 ------ 0
Second min term- m1----- 0
Third min term- m2----- 0
Fourth min term m3----- 0
Fifth min termm4---- 1
Sixth min term ---m5----- 1
Seventh min term ----m6--- 1
Eighth min term ----m7 --- 1
BC
00
01
11
A
0
1
B C
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1
1
F
0
0
1
0
1
1
1
1
10
1
1
Combine the cells that are having 1, side to side or top to bottom and find which variable has
compliment in one cell and true in adjacent cell that variable can be eliminated.
(I)
It is the sum of minterms 2 and 6
A variable is eliminated.
II = A
1
1
1
10
NOTE: here 8th min term comes in last because we followed the denoting order 00, 01, 11, 10
1) Try to combine as many ones as possible in a given group, but they should all be adjacent.
2) Always start with a highest possible group of ones because sometimes the smaller group may
submerge with in the larger group.
3) We can combine a cell with 1 more than once.
4) Every one (1) should be included without leaving any one.
I-this is the maximum block of ones. Here PQ varies vertically and RS remains same. This is the combination of 3,
7, 15, 11. So we can eliminate variables PQ and RS remain in the final solution.
I= RS
II- this is the combination 13, 15. In it R only varies horizontally and PQS remains constant. So
II= PQS
III- this is the combination of 14,15. Here S varies horizontally. So III= PQR
2) {3,2}
3) {3,7}
4) {7,5}
5) {13,15}
6) {14, 15}
8) {3,7,15,11}
Prime Implicant:- largest possible group ones. Implicants may be submerged into a prime implicants.
Eg: {0,2},
{3,7,5,11},
{13,15}, {14,15}
Essential Prime Implicant:- A group with at least one cell with truth value 1 has not been covered in any
prime implicant.
Eg: {0,2},
{3,7,5,11},
{13,15}, {14,15}
Those are the four essential prime implicants because they have at least one truth value 1 which is not
covered.
Note1:- To eliminate n variables there should be a combination of 2n adjacent cells having output as true i.e. 1
Note2:- An essential prime implicant covering all min terms having unique minimal form
Eg:- F= m(12,15,13,7,15,6,11)
Note3:- For the given function in K-map every min term is covered exactly by two prime implicants such a K-map
is called cyclic.
Module-7
VARIABLE MAPS
INTRODUCTION:
In the last lecture we introduce the map method of boolean simplification. we
use a karnaugh map which is a graphical representation of a truth table, filled this graph
with 1's corresponding to the cells whose minterms had a output true. The object is to
identify groups of 1's as large as possible with satisfying the adjacency rule.
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m1
m3
m2
m4
m5
m7
m6
m9
m11 m10
PRIME IMPLICANTS:
In choosing adjacent squares in a map, we must ensure that
1. All the minterms of the function are covered when we combine the squares.
2. The number of terms in the expression is minimized, and
3. There are no reduntant terms. some times there may be two or more expressions that
satisfy the simplification criteria.
Any group of 1's is an implicant. A prime implicant is a product term obtained by
combining the maximum possible number of adjacent squares in the map. If a minterm in
a square is covered by only one prime implicant, that prime implicant is said to be
essential.
Module-8
CODE CONVERTERS
INTRODUCTION:
We have seen the techniques for reduction of boolean functions by using
boolean algebra as well as kmaps. The object is to design circuits as per the given
specifications by using these techniques.
There are two types of the digital circuits i.e., combinational and sequential
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Example:
When we speak into cellular phone, an encoder converts the sound of our voice
into electrical signals. which can travel very fast over very long distances. When the
electrical signal get to another cellular phone, a decoder converts the electrical signal
back to the sound of our voice.
So code converters are used for more than protecting private information from
spies.
The class of codes which are used for simplification of hardware one is called
excess-3 code and other is called gray code.
b2
b1
EXCESS-3
b0
E3
E2
E1
E0
Sk.Riyaz Hussain Page 42
0
0
0
0
1
1
1
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X
Gray Code
B
G3
G2
G1
G0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
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0
0
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1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
GRAY CODE:
The gray code belongs to a class of codes called minimum change codes, in
which only one bit in the code changes when moving from one code to the next. The gray
code is non weighted code, as the position of bit does not contain any weight. The gray
code is a reflective digital code which has the special property that any two subsequent
numbers codes differ only by one bit. This is also called a unit distance code. In digital
gray code it has got a special place.
Module-9
PARITY GENERAROR
Parity Generator:
A parity bit is used for the purpose of detecting errors during transmission of binary
information .A parity bit is an extra bit included with a binary message to make the
number of is either odd or even. The message including the parity bit is transmitted and
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output
B
From k.map
P= ABC+ABC+ABC+ABC
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b2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
b1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
b0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
p
0
1
1
0
1
0
0
1
1
0
0
1
0
1
1
0
INPUTS
0
1
2
3
4
5
6
7
8
9
A
0
0
0
0
0
0
0
0
1
1
B
0
0
0
0
1
1
1
1
0
0
OUTPUTS
C
0
0
1
1
0
0
1
1
0
0
D
0
1
0
1
0
1
0
1
0
0
a
1
0
1
1
0
1
0
1
1
1
B
1
1
1
1
1
0
0
1
1
1
c
1
1
0
1
1
1
1
1
1
1
D
1
0
1
1
0
1
1
0
1
0
e
1
0
1
0
0
0
1
0
1
0
f
1
0
0
0
1
1
1
0
1
1
G
0
0
1
1
1
1
1
0
1
1
a = A + BD + CD + B D
c = B + C+ D
e = B D+ C D
b = B + C D + CD
d = B D+ C D+ B C + B C D
f = A + C D+ B C + B D
g = A + B C+ B C + C D
There are so many gates common for some segments.So make as many as common
terms and rest of them are cant be accommodated with them.Make that common
terms unique and reduce design effort.
Module-10
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ARITHMETIC CIRCUITS
Arithmetic circuits:
Simplest arithmetic operation is adder
1. Half adder
2. Full adder
1. Half adder:
Half adder is one which can only take two digits and add the sum and
get the carry and not taking carry of previous position of addition.
A logic circuit for the addition of two one bit numbers is referred to as
an half adder.
A and B are the two inputs and s(sum) and carry(c) are the outputs
S=A+B
A
Carry is when we have a digit over flowing that over flow has to accomdated
else where in the next time computation stak.you have to take into account
this over flow.
The half adder is used for 1 bit addition.No practical use except for every
first bit position.It not used for multibit number.To over come this we need
another circuit known as full adder.Half adder has only two inputs and there
is no provision to add a carry coming from the lower order bits when multibit
addition is performed.
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Sum=A B Ci
Carry C0=AB+BC+CA
=AB+Ci(A+B)
C0=AB+Ci(A A B )
But we will use this occasionally for to know next carry to reduce time delay
Circuit Diagram:
In this circuit carry in is the carry out of previous addition such a adder
which take carry from previous addition is called full order.
This is used for practical purpose and for multibit
Truth table:
A
Cin
C0
But we mainly consider carry propagation delay because the carry has
to propagate through are the gates but no need of sum propagation.The sum
has to leave in every stage.
4-bit full adder:
The very first carry of total circuit we will take as 0 and to calculate
sum in every stage we need carry out of previous stage so there is a delay of
carry propagation.
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Module-11
CARRY LOOK A HEAD ADDERS
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A3
B =
B3
C3
S3
A2
B2
S2
A1
A0
B1
S1
B0
S0
Ci
C0
1
1
1
1
0
1
1
1
B = 1 is Ci = 1
Here the carry output is 1 if A & B are 1 irrespective of the previous carry and the carry output is 1. If
A
AB + (A
B) Ci = G + PCi
Carry generate
Carry propagate
If A and B are 1 then irrespective of the carry input the output carry is generated . so , we refer to it as carry
generate.
If A
B I is 1 and ci=1 then output is generated that means the carry is generated based on the previous
+
carry that is propagrated. So, we refer to it as carry propagate.
Let us consider a 4-bit adder
B3
A3
B2
A2
B1
A1
CI
C2
B0
A0
Cin
C1
C-1
C0
C3
Ci = Gi + Pi Ci-1
C0 = G0 + P0C-1
C1 = G1 + P1C0
C2 = G2 + P2C1
C3 = G3 + P3C2
= G1 + P1G0 + P1P0C-1
= G2 + P2(G1+P1G0+P1P0C-1)
= G3 + P3G2+P3 P2 (G1 + P1G0 + P1 P0 C-1)
Now from each Pi , Gi and C-1 we can generate each Ci from the set of equations that we have derived earlier .
so now the 4-bit adder can be remolded as.
So, carry look ahead adder is one of basic techniques to improve speed of addition. In the basic adder
We have to wait for previous carries which is in contrast with this technique as it just the matter of extra
combinational logic.
Fan in : no. of inputs can give to a gate without any degradation in the performance.
Fan out : no.of outputs you can take from a gate to feed similar gates without degradation in the
performance of output.
Though CLA adder is quite advantareous regarding speed or the performance it has two
disadvantares.
1) Non uniformity or non modularity of CLA adder and
2) There is limit on no.of bits we have to do
So here in CLA adder each bit in a binary sequence to be added, the CLA logic will determine
whether the bit pair will generate a carry or propagate a carry.
Module-12
12. SUBSTRACTORS
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RADIX COMPLEMENT :
The rs complement of an n-digital number N in base r is defined as rn-N , for N 0 and 0 for N=0
.
EG: the 10s complement of decimal (1725)10 is 104 1725 = (8275)10
The 2s complement of binary (101)2 is 23 -101 = 1000-101 = (011)2.
Or
9s complement = (103-1)-729=999-729=27010
For a binary number 1101 of base 2 the (2-1)s complement or
1s complement = (24-1) 1101 = (10000-1)-1101 =1111-1101 = (0010)2.
We can obtain rs complement from (r-1)s complement by adding 1 to it.
[ rn = M-N]
Without discarding carry the sum will be M+(rn-N) which rearranged as M-N+rn. so, inorder to obtain M-N, rn
should be removed.
M-N = M+(rn-N)-rn
In the previous example the sum is 10011 and rn =10000
=>M-N = 1001 10000 = 00011 ---------- 3
CASE 2 :
Here M<N and the sum doesnt produce an end carry and is equal to M+(rn-N) which can be rearranged
as rn (N-M) that means the sum is rth complement of (N-M).
Therefore
M-N = -(N-M)
= -(rn (rn-(N-M)) ) = -(rn - SUM)
= -( 2S COMPLEMENT OF SUM )
where SUM = rn-(N-M).
Here sum is not the actual result . as the discarded bit is 0 in this case the result is a negative with
magnitude equal to 2s complement of sum . actually the sum is signed representation of the negative result as
most significant bit is 1.
To demonstrate this above hypothesis let us consider an example.
E.g.: M = 0011 , N = 0101
2s complement of N = 1010 + 1 = 1011
Therefore
M ----------- 0 0 1 1
2s complement of N ------------ 1 0 1 1
Sum------------- 1 1 1 0
MSB
Therefore
MODULE-13
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Here Most Significant Bit is singed bit and remaining three are magnitude bits.
If MSB is Zero then number is greater than or equal to zero (>=) that is positive.
If MSB is one then number is less than Zero (<) that is negative.
Ex: (1)
b3 b2 b1 b0
if b3 is '0' then it is "positive".
if b3 is '1' then it is "negative".
(2)
Q: 0 0 0 1
A: + 1
(3)
Q: 0 1 0 1
A: +
5
(4)
Q: 1 0 1 1
A: 6
Here MSB is '1", it is negative. So we have to do 2's complement.
Q: 1 0 1 0
1's complement of number
101
2's complement of number
1 1 0 (101+1)
Therefore 1010 is -6
In 4- bit representation, we have only three magnitude bits.
So,
The maximum "+ve" number is +7 "0111"
Ex: (1) + 5 : 0 1 0 1
(2) + 7 : 0 1 1 1
(3) - 5 : 1 0 1 1
1 0 0 ( 1's complement of magnitude bits )
+ 1 (adding one to get 2's complement)
1 1 0 1 (-5)
(4) - 8 : 1 0 0 0
1 1 1 (1's complement of magnitude bits )
+ 1 (adding one to get 2's complement)
1 0 0 0 (-8)
Decimal
Binary sum
BCD sum
Number
C*
S3*
S2*
S1*
S0*
C*
S3*
S2*
S1*
S0*
10
11
12
13
14
15
16
17
18
19
In this conversion, upto '9' the BCD number is same as the binary number.
When the sum is greater than '9', we obtain non - valid BCD representation. so, the addition of binary
6 (0110) to the binary sum, converts it to the correct BCD representation and also produces an out
put carry as required.
The logic circuit that detects the necessary correction can be derived from the table entires.
The correction is needed when C* = 1 (or)
S*3 S*2 =1 (or)
S*3 S*1 = 1
Therefore, the Boolean function C = C*+ S*3 S*2 + S*3 S*1
When C = 1, it is necessary to add 0110 to the binary sum and provide an output carry for the next
stage.
BCD adder is a circuit that adds two BCD digits in parallel and produces a sum digit also in BCD.
BCD adder must include the correction logic in its internal construction.
The two decimal digits, together with the input carry are first added in the top 4 - bit binary adder to
produce the binary sum.
When the output carry is equal to zero, nothing is added to the binary sum. When it is equal to one,
binary 0110 is added binary sum through the bottom 4 - bit binary adder.
The output carry generated from the bottom binary adder can be ignored, since it supplies
information already available at the output carry terminal.
The BCD adder can be constructed with three IC packages. Each of the 4- bit adder is an MSI
function and the three gates for the correction, logic need one SSI package. However, the BCD adder
is available in one MSI circuit. To achieve shorter propagation delays, an MSI BCD adder includes
the necessary circuits for look - ahead carries.
The adder circuit for the correction does not need all four full - adders, and this circuit can be
optimized within IC packages.
NOTE :
A decimal parallel adder that adds 'n' decimal digits need ' n' BCD adder stages.
SUMMARY :
MODULE 14
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ARRAY MULTIPLIER
ARRAY MULTIPLIER:
This array is used for the nearly simultaneous addition of the various product
terms involved. To form the various product terms, an array of ' AND' gates is used
before the adder array.
The main advantage of array multiplier over traditional bit serial multipliers is, it
improves the speed.
Shift and add several times - working all with same times.
EXAMPLES
(1) 2 - Bit array multiplier :
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------- multiplicand
b1 b0
------- multiplier
a1 b 0 a0 b 0
a1 b 1
p3
p2
a0 b1
p1
p0
------- product
p0 = a0 b0
p1 = a1 b0 + a0 b1
p2 = a1 b1 + c1, where c1 = carry generator during the addition for p1 term.
p3 = c2 , where c2 = carry generator during the addition of p2 term.
LOGICAL DIAGRAM :
HA = half adder
pi = product terms ( i = 0,1,2,3 )
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a1
b1
a0
b0
------- multiplicand
------- multiplier
a2 b0 a1 b0 a0 b0
a2 b1 a1b1 a0 b1
a2b2 a1b2 a0b2
p5
p4
p3 p2
p1
p0
product terms
p0 = a0 b0
p1 = a1 b0 + a0 b1
p2 = a2 b0 + a1 b1 + a0b2 + c1
p3 = a2 b1 + a1b2 + c2
p4 = a2b2 + c3
p 5 = c4
where c1, c2, c3, c4 are carry generators during the addition for p1, p2, p3, p4
respectively.
LOGIC DIAGRAM :
Where
HA = half adder
FA = full adder
pi = product terms ( i = 0,1,2,3,4,5 )
c = carry
s = sum
Ts = sum bit propagation time
Tc = carry bit propagation time
a3
b3
a2
b2
a1
b1
b0
a3b0 a2 b0
a3b1 a2 b1 a1b1
a0
a1 b0 a0 b0
a0 b1
p6
a2b3
p5
a0b3 a0b3
p4
p3
p2
p1
p0
Logic Diagram
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= n
Numbers of 'FA'
= (m-2) *n
Even through it improves the speed, still there is a level of delay invovled in an
array multiplier before the final product is achieved. That is
For an " m * n" bit multiplier
Let Ta = AND gate propagation delay
Ts = sum bit propagation delay
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CONCLUSION :
Array multiplier is an electronic circuit used in digital electronics to
multiply two binary numbers.
ADVANTAGE :
It improves the speed.
DISADVANTAGE :
Even though it improves the speed it has some propagation delay.
SUMMARY :
Array multiplier definition
Advantages and disadvantages of array multiplier.
Examples of Array Multiplier.
Knowledge about m * n array multiplier.
Module-15
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There are two main types of sequential circuits and their classification depends on the
timing of their signals. A synchronous sequential circuit is a system whose behavior can
be defined from the knowledge of its signal at discrete instant of time. The behavior of
an asynchronous sequential circuit depends upon the input signals at any instant of time
and the order in which the inputs change. The storage elements commonly used in
asynchronous sequential circuits are time delay devices. Thus, an asynchronous
sequential circuit may be regarded as a combinational circuit with feedback. Because of
the feedback among logic gates, an asynchronous sequential circuit may become
unstable at times.
A synchronous sequential circuit employs the signal that affects the storage elements
only at discrete instant of time. Synchronization is achieved by a timing device called a
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LATCHES
The basic storage (memory) elements are latches. The latches introduced here basic
circuits from which all flip-flops are constructed. Although latches are useful for storing
binary information and for the design of asynchronous sequential circuits, they are not
practical for used in synchronous sequential circuits.
SR LATCH
The SR latch is a circuit with two cross-coupled NOR gates or two cross coupled NAND
gates. It has two inputs labeled S for SET and R for RESET. In digital language SET
means output is 1 and RESET means output is 0. This latch has two useful states.
When the output Q=1 and QI=0, is said to be SET. When the output Q=0 and QI=1,
is said to be RESET. The each outputs Q and QI are normally the complement of each
other. How-ever when both inputs are equal to 1 at same time, an undefined state with
both outputs equal to 0 occurs.
When S=0 and R=0 the outputs are depends upon previous output of Q and QI. it is
called memory state.
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FLIP-FLOPS
A flip flop circuit can maintain a binary state indefinitely (as long as power is delivered to
the circuit) until directed by an input signal to switch states. The major differences
among various types of flip-flops are in the number of inputs they posses and the
manner in which the inputs effect the binary state.
SR FLIP-FLOP
The operation of the basic flip flop can be modified by providing additional control input
that determines when the state of the circuit is to be changed. An RS flip-flop with a
clock pulse (cp) input is shown.
CS2201 Switching
witching Circuits and Logic Design
The pulse input acts as an enable signal for the other two inputs.
Let us assume previous output is zero for starting time. At t1 cp and S=0 and R=1 so Q=0
until t2 and now cp=0 means it assigns its previous state i.e. Q as 0. In this SR flip-flop
flip
to
get output as 1 we have to supply two inputs S and R as 1,0 respectively. To avoid this
we have another flip-flop
flop called D
D-flip-flop.
SET operation
RESET operation
MEMORY operation
TOGGLE operation
All these operations can be performed by JK-flip-flop. Before going to JK-flip-flop, let us
look at this special or modified SR-flip-flop.
Toggle means complement of previous outputs. Here one disadvantage that is while S, R
and clk are at logic level 1 , it gives output Q ,QI, Q ,QI, Q ,QI............ and this
phenomenon is called RACING.