Ex.

No: 4

Comparators

Date:

AIM:

To write VHDL programs to implement the various comparators using

dataflow, behavioral and structural abstraction models.

ALGORITHM:

Step 1: Declare the entity with input and output ports.

Step 2: Declare the required signals in the architecture section.

Step 3: Begin the architecture.

Step 4: Use withselect / when.else statements for designing adders/subtractors using

dataflow model.
Step 5: Use the various statements like ifelse or case.when statement to design the
various adders / subtractors using behavioral model.

Step 6: Declare and instantiate components in order to design adders / subtractors using
structural model.

Step 7: End the architecture

MODEL PROGRAM:
library ieee;

use ieee.std_logic_1164.all;
entity comparator is

generic(n: natural :=4);

port(A:in std_logic_vector(n-1 downto

0); B:in std_logic_vector(n-1 downto 0);

less:out std_logic;

equal:out std_logic;

greater:out std_logic);
end comparator;

architecture behv of Comparator is

begin

process(
A,B)

begin

if (A<B)

then less <=

'1'; equal
<= '0';

greater <=
'0'; elsif

(A=B) then
less <= '0';
equal <=

'1'; greater

<= '0'; else

less <=

'0'; equal
<= '0';

greater
<= '1';

end if;
end

process;
end

behv;

RESULT: