Tanner Tools v13.

00

Tanner Tools Version 13.00..................................................................................................................... 2

S-Edit v13.00 .......................................................................................................................... 2
T-Spice v13.00 ....................................................................................................................... 3
W-Edit v13.00 ........................................................................................................................ 3
L-Edit Pro v13.00 ................................................................................................................... 3
HiPer Verify v13.00 ............................................................................................................... 5
HiPer PX v13.00 .................................................................................................................... 7
.......................................................................................................................................... 7
.............................................................................................................................. 7
.............................................................................................................................. 7
...................................................................................................................................... 7
.......................................................................................................................................... 7
.......................................................................................................................... 8

Tanner Tools Version 13.00

S-Edit v13.00

S-EditHierarchy Navigator

S-EditHierarchical Find

S-Edit UI
> > Trace nets on push and pop context
/
/
/

> >
Shift

Verilog

EDIF

SPICE

property get tcl

-double

EDIF
Revision Control

EDIF

 S-Edit

Copy Cell

T-Spice v13.00
Verilog-A
Verilog - A

T-Spice Verilog - A Verilog - AMS2.2

Verilog-A Language Reference and
Verilog-A User Guide

Run Simulation Simulation >

Simulation Settings

Spice
File > Open Folder Containing filename

Simulation Manager 2Input

Output Diff (
Diff Simulation Settings

-
T-Spice Dynamically Linkable Libraries
(DLLs) tspicemodels
BSIM3, BSIM4, RPI TFT, Bipolars,

Known Issues
There are known issues with convergence and performance for the Verilog-A
examples, due to problems in the Verilog-A models.

W-Edit v13.00
W-Edit v13.00

L-Edit Pro v13.00

X-Ref
tdb X-Ref
File1:Cell(A)

File2:Cell(B) File2:Cell(B) File3:Cell(C)

File1 File3:Cell(C)
X-Ref :
v13 X-Ref
Setup Design > Xref files Xref
V13.0
X-ref
"cellname:libname"

i)ii)iii) iv)
Tools > Assign Instance Names.

Schematic Driven Layout SDL

SDL 3 By Net, By Instance By
Unrouted Segment. By Net
By Instance
By Unrouted Segment
SDL

Verilog SDL

SDL
v13SDL
Keepouts

SDL

LVS
MOSFETM,B,J,Z BJT
FET, BJT, R, C L

.lib

Setup Application >

General Instance Stretching

Implicit Selection Setup Application > Selection

Highlighting implicit selections
Setup Layer Palette

Nudge

Virtuoso *.*

DRC

LCell_GenerateLayers_v11_10
LVS

HiPer Verify v13.00

HiPer Verify Calibre Dracula v13
HiPer Verify Tanner Standard Extract
Calibre Dracula
Spice MOS
Calibre Dracula
Calibre

Spice Extract
Summary Report
Spice L-Edit
Cells > Assign Instance Names

Calibre

DEVICE

LVS GROUND NAME

LVS POWER NAME

LVS NETLIST COMMENT CODED SUBSTRATE

$SUB 33
3

Calibre DRC
DEFINE DRC Setup
TRUE
Name=Value
PUSH HiPer Verify

HiPer Verify command file parser can now handle large deeply nested implicit
layer definitions.
The single layer INT operation now only compares edges from the same polygon
for edge layer input. Polygon input was working correctly, but not edge input.
This will eliminate certain false errors from the INT operation on edge layers.

Polygon containment tests are now performed correctly for edge layer input. This
will eliminate certain false errors on INT, EXT and ENC commands.
Obtuse angle violations on DRC checks are now correctly found. They were
previously not found.
Expand Edge Outside By now parses correctly.
Implicit layer definitions now work correctly in the STAMP command.
ATTACH, CONNECT, LABEL ORDER, and SCONNECT with DIRECT option are
now ignored. Direct verification set commands are not run in Calibre.
Fixes to SCONNECT and STAMP are made.
Secondary keywords may now be used as layer names in any operation, except
the operation itself that uses that name as a secondary keyword. Many layer
names that would previously cause errors are now allowed.
The secondary keyword INTERSECTING is now allowed as an abbreviation of
INTERSECTING ONLY.
Problems with NET AREA RATIO commands split over multiple lines are fixed.
Problems when using WITH WIDTH in a rule deck with DRC INCREMENTAL
CONNECT YES are fixed.
Parsing of include file paths is fixed.
"Negative Edge output is now working correctly for edge input layers, for example
Rule { EXT (Layer1) Layer2 <= d } where Layer1 is an edge layer.
TOUCH and NOT TOUCH with constraints are now working correctly.
WITH WIDTH now supports the != constraint.
DEVICE NETLIST ELEMENT

TRUNCATE is now allowed as well as TRUNC in the extract property language.

The EXCLUDE SHIELDED option in INT, EXT, and ENC is now parsed and
ignored.
A problem with EXPAND EDGE is fixed.
False errors reported by ENCLOSE with constraints is fixed.
Missing errors on EXT with PERPENDICULAR ONLY option is fixed.
SCONNECT now reports hierarchical results without unnecessary flattening.
Incorrect results on RECTANGLE operation with >= constraint is fixed.
False errors in INSIDE operation are fixed.

Dracula
Dracula
ELEMENT BJT
ELEMENT CAP
ELEMENT DIO
ELEMENT LDD
ELEMENT MOS
ELEMENT RES
:
ELEMENT BOX
ELEMENT PAD
EQUATION
LEXTRACT
PARAMETER CAP
PARAMETER RES

Dracula DRC
Dracula

WIDTH Conjunctive

HiPer PX v13.00
HiPer-PX
polysilicons

HiPer PX
3
HiPer-PX3-D2D
3-D HiPer-PX Tools > Parasitic Extractor

Microsoft Windows XPWindows Vista

Intel Pentium IV SSE
512 MB RAM
100 MB 100 MB
64 MB
3

Microsoft Windows XP
Dual Core Intel Xeon 2.66 GHz
PC Intel Core 2 Duo 2.00 GHz
2 GB RAM
100 MB 100 MB
256 MB
Microsoft Intellimouse
1280 x1024 True Color (24)

Tanner Tools Windows

Tanner Tools CD CD-ROM
CD
SETUP.EXE
Tanner Tools

Tanner Tools
Tanner Research, Inc. Tanner Tools

Tanner Tools

Tanner Research Sentinel C-Plus-B Interlink

LapLink
Sentinel C-Plus-B

Tanner Research, Inc.

825 South Myrtle Avenue
Monrovia, CA 91016-3424, USA
Telephone:
Fax:
E-mail:
Web:

1-877- 304-5544 (Toll Free)

1-626-471-9700
1-626-471-9800
support@tanner.com
www.tannereda.com

Japan
Tanner Research Japan K.K.
BUREX Kojimachi 6F,
3-5-2 Kojimachi, Chiyoda-ku
Tokyo 102-0083
Japan
Tel:
+81 (3) -3239-2840
Fax:
+81 (3) -3239-2860
Email: sales.jp@tanner.com
Web: www.tanner.jp

Europe
EDA Solutions Limited
Unit D, 58 Botley Street
Park Gate
Southampton, SO31 1BB
United Kingdom
Phone:
+44 (0) 1489 564253
Fax:
+44 (0) 1489 557367
Email:
tanner@eda-solutions.com
Website:
www.eda-solutions.com