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Analysis Procedure
We need to analyze digital circuits to verify
our designs (as well as understand designs
without documentation)
Assume we have the logic diagram (and
some minimal info about the inputs)
Steps in Analysis
Label all the outputs of the gates that are
connected directly to the inputs with (short)
arbitrary names
Label all the outputs of the gates that are
connected directly to the previous set
Repeat till all gates are done.
Symbolic Manipulation
Substitute symbolically till all intermediate
symbols are gone
Build the truth table
HDL compiler packages have good tools to
speed this up
Design
The purpose is to translate a high level
description of the circuit to a logic diabram
or something that is directly implementable
Normally we are expected to minimize some
cost measure
Design Procedure
Give short names to all inputs and outputs
Derive truth table from the specification
Simplify
Draw diagram
HDLs
The first two steps cannot be handled by
HDLs
but the compiler packages provide tools
there are libraries that can be reused or modified
Example: BCD-Exc3
We design a converter from BCD to Excess3
Excess-3 is essentially BCD+3
Truth Table
ABCD
wxyz
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
Handicraft...
The boolean expressions are
w = A + BC + BD = A + B(C + D)
x = BC + BD + BCD=B(C+D)+B(C+D)
y = CD + CD = CD + (C+D)
z = D
Add-Subtract
Extremely important subcomponent of most
digital systems
Does not have a good solution
Astonishing amount of ingenuity has been
invested
There are many researchers that still hope...
Half Adder
2 inputs, 2 outputs
So simple that can be done without maps etc
S = xy + xy
C = xy
CS
00
01
10
11
00
01
01
10
Full Adder
A bit more interesting
Adds 3 bits (2 bits plus a carry-in)
Produces 2 outputs
Needs maps
00
01
01
10
01
10
10
11
Multi-bit Adders
For multi-bit adders we cascade several full
adders
Easier to package because we do not need
the intermediate carries (but our ingenuity
may come back to hunt us)
Carry Propagation
For a N bit adder we have 2N gate delays
Addition is very important for memory
management, array access, etc,
multiplication, and on its own rightCant
leave it like this!
Carry LookAhead
Find nice tricks to reduce the number of gate
levels
Define Carry-Propagate and Carry-Generate
P_i = A_i (+) B_i
G_i = A_i B_i
Subtraction
We have to take the 2s complement
we use the trick with the carry-in
Why is that?
The rule is that we have an over(under)flow
when
the sum of two positive numbers is negative
the sum of two negatives is positive
Truth Table
A3B3C3
S3C4
000
001
010
011
100
101
110
111
0
1
1
0
1
0
0
1
0
1
0
0
0
0
1
0
0
0
0
1
0
1
1
1
BCD Addition
Just like binary addition but with an extra
step: if the result is greater than 9:
we generate a carry
and add 6 to skip the unused numbers
Example:0111+0101=1100<=>1100+0110=
10010=C:1,S:10
Binary Multiplication
Like the decimal one we SHIFTMULTIPLY_ADD
It is easier with binary 1-bit multiplication
because it is just AND
Comparator
A comparator compares two numbers
Can tell us if they are equal
Can also tell us which one is the biggest
How it works
A 4-bit comparator contains 4 1-bit
comparators
An 1-bit comparator is easy to design in an
ad-hoc way
Two numbers are equal if all the 1-bit
comparators shout equal
How it works
A is greater then B if
The MSB of A is greater then the MSB of B
Or the MSBs of A and B are equal and the
second MSB of A is greater then the second
MSB of B
etc
A_0<B_0
Decoder
A standard and quite useful MSI chip
Has n input and 2^n outputs
The output with number that corresponds to
the binary value of the input is high and the
rest are low
Produces all the minterms
Enable pin
Decoders usually have an ENABLE pin
Very often ENABLE pins have negative
logic (active low)
Without the ENABLE one of the decoder
outputs is always true
Many uses
The main advantage of the ENABLE is that
it allows us to build big decoders out of
smaller ones.
E.g. build a 4x16 decoder out of two 3x8 and
a 1x2.
Combinational Logic
Decoders produce all the minterms
So can be used to implement functions
Very good for hard to minimize functions
Very good for MSI-SSI implementations
General Procedure
The simplest way to design a combinational
circuit with N inputs is to use an N x (2^N)
MUX
Connect the inputs to the control inputs
Assign 1 to the data inputs that correspond to the
minterms, zero o/w
Too simple...
Too simple to be mentally satisfying
We could use a smaller MUX and very little
other hardware (or have more inputs)
General Procedure
Assign the N control inputs of the MUX to
the first N inputs to the circuit we want to
design
Separate the truth table to 2^N blocks
Treat each block as an individual truth table
and minimize it
Advantages
We can implement efficiently quite large
combinational circuits
with a 16x4 MUX we can implement a 10 input
circuit using nothing but maps.
Disadvantages
It is not always a standard form (AND-OR
or OR-AND)
The advantages are less significant if we do
not use MSI