Scribd Logo
Upload

Welcome to Scribd!

  • Us 20120061796 A 1

    Uploaded by

    Arvind Shrivastava
    6 views13 pages
    programmable efuse wirbond pads

    Original Title

    Us 20120061796 a 1

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    programmable efuse wirbond pads

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    6 views13 pages

    Us 20120061796 A 1

    Uploaded by

    Arvind Shrivastava
    programmable efuse wirbond pads

    Copyright:

    © All Rights Reserved
    Download as PDF or read online from Scribd
    Flag for inappropriate content
    of 13
    US 2012006179¢ 20 6 10 00 cu») United States cz) Patent Application Publication co) Pub. No.: US 2012/0061796 A1 Wang (4s) Pub, Date: Mar, 15, 2012 (4) PROGRAMMABLE ANTE-FUSE WIRE BOND (62)._US.C1 2578530; 438/60; 2571023.) PAbs 257121 92 (75) veer; James Jemtfe Wang, Phoenix, AZ = co ABSTRACT A mechanically programmable at-fuse is configured in (03) Assience: Power Gold LLC ahh, top mote yer of a semivondoctr. The metalic layer selected of material tat possesses malleable prop (1) AppLNos — rRRO7 756 tris. The meal antfase programming pod i saranda titer whly orn prt, bya pad seu. An interven (22) Filed: Sep. 14, 2010 bs ie ad space between the anticise pad and the pad segment is ‘Selected from a predetermined Value such that capilary pees: sre, exerted when abal-bond is placed atop the anti-fse pad () Ince. ‘and the pad seyment, eases the pads o deform aad shorts to OIL. 23525 (2005.01) the antisuse pad to the pad segment. The shorting. created HOLL 217768 (2005.01) ‘during the wire bonding process, progzaais the an-fise Publication Classification Patent Application Publication Mar. 15,2012 Sheet 1 of 7 ‘US 2012/0061796 AL FIG.1 ‘US 2012/0061796 AL Mar. 15, 2012 Sheet 2 of 7 Patent Application Publication itD it F Circuit E 40 32 ircui aL c > FIG. 2A ‘US 2012/0061796 AL Mar. 15, 2012 Sheet 3 of 7 Patent Application Publication FIG. 2B Patent Application Publication Mar. 15,2012 Sheet 4 of 7 ‘US 2012/0061796 AL | 292 FIG. 2C ‘US 2012/0061796 AL Mar. 15, 2012 Sheet 5 of 7 Patent Application Publication 350 FIG.4 ‘US 2012/0061796 AL Mar. 15, 2012 Sheet 6 of 7 Patent Application Publication 550 our FIG. 5 ‘US 2012/0061796 AL Mar. 15, 2012 Sheet 7 of 7 Patent Application Publication ie FIG. 6 US 2012/0061796 AI PROGRAMMABLE ANTI-FUSE WIRE BOND Paps: 10001} ‘The following patent application is based upon and ‘las priority fom provisional patent application number US. Ser. No. 61/276,313 filed Sep. 11, 2009, BACKGROUND OF THE INVENTION 10002] The present vention ates to elesteosie iets nd more particularly to programmable eget, and even ‘more pariclarly to programing of ani-fuses ia clestonic irc. 10003] Poses snd snticiscs are wilized in integrated cir ‘exis (C's to permit selective outing of eect and selec- tive ehoiees of optional componcats within the crete. FPses and ent-foses reintegrate int a semicondtor nt jie iri to provide programming capabilities afer se onducior wafer processing is compet, ether electrically, ‘ea. dng electrical texting o the wafer, oroptclly. eg BY laser cutting, or mechanically, during assembly of the 1 di, ‘eg, shorting of ant-uses by bonding {0008} Eectcaly programmed fses ace typically struc- tured as conetve polysilicon ks oF conductive met zation links, sich o& akin. The condocting fms are “Blow” with ref eument spike or cu with laser terete an ‘open circuit in the nk path A conductive fe, ale ts bowen or eu, becomes highly resistive. However, with ime, the highly resistive blow fse has 8 tendency to fase back togeter through the process of eleeteal metal migration “hus, the fase becomes potetally conductive and ussabe. Likewise, laser ut fis presents relibility issues duet ‘ncontlled migration of metal cased by heat generation ‘uring the laser eating proves, To work around this ss, spacings must be inereased inthe lsc cing are 0 po ‘de an additional safety ateasueounding the fuse. Ths the ‘emiconductor wafer ar se becomes inllicca. [0005] Anti-fses function i everse and ate typically fab- Fealed as semicondoelor junctions or thin dickctc lms. Under low voltage, a reverse bias semiconductor junction ‘appears open. Aller slicenly high clovecal eee is spiked though a dede junetion or dielectric, “shoe” is formed inthe fsing pai. In practice © minimize current needed to “shor antieuses, odes are small. Since the eit itis optimized for low eurent atcfosing, once the clement is shorted the resulting resistive atifse eicui is not seal to support higher cureat apliations in the resistive cic {0006} "Fuses fr caialereuits typically rou kilo oa range site ina “open” state ad ohm ange resistance iva “shored” state, Thee is yield loss due to resistance ‘aviation of ot ses andantcses with present processes 0007] Analog eireuits typically require antitises above the megs ringe ina “open” slate es than 001 oma rangeinashorte tat. For analog cet the valves must beestemely consistent anl accurate, especially for applicae tions such as power integrated cies and for analog. to ‘isital converters. {0008} Thus, clctically programmed fses o antiuses Jabcued within inewated eeu, bo analog and digital, require additonal ler cutting steps oF addtional power spike steps o erate the resting fase or ant-fuse hats not ‘eal and not avtable for high carent or high voltage [0009] "Attcmptstocizcomvent snes with cletally poe summed fses snd atisses can be ilsteated by reference Mar. 15, 2012 art patent US. Pat, No, 7,301,436, In FIG. 1 (a copy of FIG. 1of the patent) an ant-fse pad clement is shown, The ant {use consists of interleaved fingers, which when covered with ‘ball bond, prograns the corresponding unt-fuse element. Although the ati-fise finetion is accomplished, the method is inefficient, For high voltage and high eurrent plications, spacing between the intecloaved fingers must be increased 10 prevent metal migration shorting of on-fased elements. Fur thermore, each antiusing element requires an associated interleaved pad that may or may not be wie in the conf ‘ation of the final eireutry. Extra silicon chip “real estto™ is aired to accommodate the anti-fusing pas [0010] Additionally, a potential for voiding under the asso- ciated ball bond may occur due wo the son-planarized areas between the metal runners of the interleaved fingers, There- {ore the quality of eletrcal probing and of ball bond onto ‘hin, narow metal runners with spacings is questionable. [O11] Inaninterleaved aatisuse approach, thi plus thin interlayer dielectric films are common tothe inte- ‘rated cient The thin pads do not cushion iter-meal layer Giolectrics (ICDs) against impact from acapilary during wire bonding nor do the thin pads relieve subsequent package ‘mechanical stresses. As such the pods ofan interleaved sys- {em are unsuitable for placement directly on top of sensitive active eircits Prt interlayer diclecric oxide, used it “interleaved” process bonds [0012] Therefore, what needed isa “real estate” efficient method of producing. anticfise programming. elements ‘capable of supporting high curents and voltages, and furher capable of being placed on top of active circuitry within @ semigonductor circuit, BRIBE DESCRIPTION OF THE DRAWINGS. {0013} FIG. 1 itloseaes an ant-se reference art example fiom US. Pat No. 7301.36 (0014) FIG. 28 itstates the top view ofa programmable dutfse ecuit implemented with multiple pal seam Sand aulple atise pace. {0015} FIG. 28 ilstates the tp view of programmable ‘nif crit mplemented witha single pt seyment and ‘uli anticise pads {0016] FIG. 2Cilsrates a typical via coupling of secon aun fist layer metlizatins {0017] FIG. 3illusrtesacros-svionl view of FIG. 2A {0018} FIG. illustrates the wp view of an antifose pad design with adjacent octagonal shaped bond pods {0019} FIG. 8itlusrstes the top view of muliplean-fises, ach having the capability for programming a capacitor ina tuning configuration, {0020] 116. illustrates the top view ofanon-ehip inductor ‘ling the preseotantitase proces of FIG. 4 ‘SUMMARY OF THE INVENTION [021] A mechanically programmable ant-fse is contig- ‘ured in a metallization layer ofa semiconductor. The metal lization layer is selected ofa thick material that possesses ‘malleable properties. Themetal anti-fase programming pais surrounded, either wholly or in par, by a pad segment, An intervening space between the ant-fise pac and the pad seg- ‘meat is selected from a predetermined value so thatthe ant fise pad deforms and totally shorts, oF near shorts to the pad segment under capillary pressure exerted when abal-bond is US 2012/0061796 AI placed atop the anti-fuse pad and the pad sepment dur final manufacturing stage of the semiconductor. The total shorting or near short programs the antifuse. The resulting ‘ntifise exhibits @ rage of resistance values from zero 10 Jow value milli-ohms, 10022] "Selective placement ofa polyimide-type layer under the respective anise fclitates placement of the ant-fuse ‘overactive areas i the semiconductor integrated circuit The malleable properties of the metal layer, combined with the ‘cushioning eflect of the polyimide reduce wire bond induced stress to the brite interlayer dilocteic and active ciruits Within the silicon, Multiple ant-fase pads ure combined into ‘one pad structure. Thus, realestate area ofthe semiconductor ‘application is conserved while reliability ofthe structure is ‘enhanced 10023] The novel anti-fse is well suited, but isnot Fimited 'o, © analog and digital circuit applications, high current Jietions, analog. to digital converters, precision tuning, pro- sgrammable circuits, ete DEI 10024) Active components, passive components, and lay- es, eg, seed metal, anti-reflective coating and adhesion lay- ers, interlayer passivation, and metal tiles are omitted from the drawings for simplification and to add clarity w the description ofthe invention 10025] FIG. 2A deseribes an embodiment of the present invention as applied to mechanical programming of circuit ‘options inanintewrated circuit, 10026] _Anti-fuse pad 28 is adjacent, in part, to pol sepment 24 and wo pad segment 26, with intervening space 33 lying there between. Pad segment 24 is coupled to Circuit F 41 through via 22 with fst layer metallization (901 shown), First layer metallization is, but isnot limited to, for example alu- ‘minum, copper or an alloy thereof. Antisuse pad 315 adja- ‘cent in part to pad segment 38 and to pad segment 26, with, Jnervening space 27 lying there between, Pad segment 35 is ‘coupled to Circuit B40 through via 38 with frst layer metal lization (uot shown), Pad segment 26s coupled 1 Circuit D 39 through via 37 with frst layer metallization (not shown). “The anti-fuse pad and the pad segments reside on the second, metallization ayer First and second metallization layers are separated by a passivation layer (not shown} 10027] sone skilled in the art would recognize, additional metallization, circuit elements, and components maybe ‘coupled othe pad segments through the second metallization Iayer. Additional vias may be added (0 the respective pad segments to provide further coupling to fist ayer metalliza- tion and corresponding eireitry (not shown). Furthemore, pad seaments may be elongated or extended o facilitate add tional bonding ares and probe area, or 1 provide for distei- bution of higher cureats, 10028] Circuits D, F, and F are, but are not limited to ‘elecionie eizcuitry, active elements (Single or grouped), oF passive elements Single or grouped). [0029] Anti-fuse pads 28 and 31 are depicted as octagonal jn shape, but one skilled in the at would recognize ether shape considerations are viable altematives, [0030] For the example of FIG. 24, anti-fase pad 28 is sletel to be programmed at the final assembly step to con- eet Cireut D to Circuit F, Ball-bond 32 is placed concur rently on antifise pad 28, pad sepment 24, pad segment 26 tnd intervening space 33. The capillary pressure applied to the ball hond, ring the bonding process, squishes, ie, ILED DESCRIPTION OF THE DRAWINGS. Mar. 15, 2012 deforms, he bal bond, the pa sepment pds and the ant fuse pad. The sguising process cata the sain pal ‘hepa seyment to shor togtie. Thus Cieuit Dis coupled to Cireuit Ftrvgh the at-fse {0031} »Sccond layer metallization i, bt i ot nied 20d, aluminum, CON:Pd, CuNiAU, NiAU, Ag. Alor Cu For this cxample, the thickness ofthe second metalation layer nlleable eleewoplted 01,9 microns witha range fo 10.28 microns. The infervening space bewween te aifase rex and surounding pad segments is adequate to provide Clecrival isolation ithe un-bonded sae Interven space Jing between the pods is 12 microns and ean be sped, for simple, fom 610 25 microns and is dependent upon pad thieknoss and px material Wie material, tis nt insted t0, gold, copper, akin, and alloys. Wire mtrial aad diameter and resting ball bond diameter ae selected to noquately coer theanti-fose pad, the intervening space, and the surrounding pad segments Fra given proces, given the present embodiment ofthe iaveaton, one skilled inthe at Understands specific process and. material variations and ‘herefoecan derive press ae material parameters required ‘oauately perform the suishing proces forthe anise {0032} Looking now to FIG. 28, anifase configuration 220 bas nlp sits pads surrounded by «single pad Seument io provide programming options fr coupling of the pail seamen to a mlpe of ecu options. {0033} "Pad segment 29 surounds anti-foe pad 228 with {intervening space 233 thee beteen and suerundsantifse pod 231 with intervening space 227 there belwown. As come pated with FIG. 28, FIG. 23 antisfse pads ate each totally Surounded, jc, 360 depres adjacent, 0 the pad segment. Pad segment 23 is coupled to fist yer metlization (aot shown} and Circuit © 239 though via 297 {0034} -Anticfse pod 28 is coupled t Fist layer stall Zation (oot shown) and eovple to Cine B 241 through via 280. Thus, ant-fse 228 provides an opportunity for eoupling CGivcuit B to Circuit C. The antefuse setae of FIG. 28 provides the opportunity to couple CieuitC to citer Cire B or Cieuit Av orto both, dependent upon the selection of applicaion of an appropriate corresponding ball Bond {0035} "Ansi-fupad 231i coupled irs layer mal (act Shown) and to Cie A 240 thot via 28 {0036} "Additional metalization and components (aot shown) may be coupled tothe pd segments through the Second metallization layer 10037] Additional vies may be aed to the respective pat Seumeuts to provide Frtor coupling to fist ier mts tion and comesponding eter (a shown). Furthermore, pralsegmentsmuy bectonated or extended elite ald Fional bonding area and probe asa, oro provide for dst bution or higher eurens. {0038} For the example of F1G. 28, ant-ise pad 231 is selected tobe progranimd atthe final snsembly sep to con- oot Circuit to CieeitC. Ball bond 30 is placed concur really fants pad 2, po semen 23, an inervenig spoee 227, The capillary pressure applied tothe ball bond, during the bonding process, squshes, ic, deforms, the bs bond, the pt segment pads, and the antfuse pad. The scuising proces causes the aatifune pad and the pad soa ‘ent to deform and short together. Thus Circuit Ais coupled to Cit C through the antife. {0039} "Second layer metallization i, but is ot Tinted od, aluminum, CuNPd, CuNiAU, NIA, Ag_ Alor Cu. For {his example, the thickness ofthe second metallization layer, US 2012/0061796 AI tualleable electroplated gold, is 9 micros wih range fom 1025 mierous. The intervening save beween the anise par and surrounding pad segments is adequate to provide ‘lectrcal scltion it the ut-bonded sae Inlervening spac- ing betwoen the pad is 12 microns and can be spaced, for example, from 6 25 microns and is dependem upon pad thicknessandpadmateriat. Wire materia, bat sno ined to, gol, copper, sluminur, and alloys. Wire material and ameter and resting ball bond diameter are selected to adequately cover te ant-fuse pad teintervening space, and the surrounding pad seuments. For a given proces, given the present embodiment ofthe invention, one skilled inthe at Understands specific process and material variations and therefore can derive proces, pad design rule, and mata parameters required to adequately perform the squishing pro- fer for the ani fise, [0040] Anti-fuse pads 228 and 231 are depicted as octago- tal in shape, but one skilled inthe at would recognize other shape considerations ae viable slematives [0041] Looking to FIG. 2C, a cross-section of second layer inetalzation coupling o fit layer intercounet is shown “The cross-sectional view apples wo second layer metlin tin to int layer metallization coupling, for example, in FIGS. 24.20, 4 §,and 6. [0042] Second layer metallization 294 is coupled to first Inyer metalation 296through via 298, Passivation nyer292 Fes ween he fst and second metallization layers. Posse tation layer 292 i for example, but not limited oy silicon Aioxie,nitide, polyimide, ora combination of muliple films 10043] Looking now io FIG, 3,crst-section 6 of FIG.24 's shown, Substate 68 is configured for fabrication of in tinted componeis, bot active and passive, The itera ‘omponent are ot drawn to simpy the figure. Likewise, ‘addtional metallization interconnect layers, intervening ay x, Bil not linited to, interlayer deletes (LD), and ‘iss ae aot draw, Subsite 68 fe sulle for ousting Integrated components and not Finite, silicon, GaAs, ‘ther compound semicondicior, printed circa boars, fiberglass, LTCC, ceramic, glass, sd exible cies [0044] Dummy metal layer 63 is placed partially under pad einen 24,26, and 35, under inkervening spaces 33 ane 27, 31. The dummy metal ayer nol conneced o any inlegrated Component cacti met- alization inerwonnect wii the iterated semiconductor Hrctue, Dummy’ fist metal layer 68 provides protection fiom mechanical damage for ings! components (oot showin located unde the dunn layer [0045] A standard passivation film 64 covers the first layer Ineallzation interconnect and sls covers the dummy metal layer. The passivation i scoveredby polyimide ayer 6210 providea potetve cushioning effect forthe iterated com Ponents below. Topside polyimide 60 used a a proeetive barre to regions not exposed ofaetions suc probing oF bonding Polyimide layer 60, but no init, polyimide, benzocyclobutene (BCB), other organi fins and pls “oxy-nitride (PON). [0046] Ball bond 32 is placed atop pad segments 24 and 26 and atop of ant-fuse pd 28, using a capil ball bonding, ‘The force frm the bonding copllary it suficen to squish ant-fise pad 2 anda portion othe pad segments, The force ‘cases deformation ofthe at-fse pa and he adjacent pad Mar. 15, 2012 eames, narrowing intervening space 391 the point that a ‘otal shor or nearshirtis created Between hepa Ths the a-fise is programmed [0047] Referring now w FIG. 4, an an-se configuration ‘ied for sorting bond pads is shown, The anise config ration formed with eeond layer mealzaion using a mal Ieabl thik metal or metal lly. {0048} Ant-se pad 48 is adacent w pad segment 380, ‘ond: pad padsewent 4, and bond-pad pad seinen 46 wih intervening space 300 there between [0049] Bail bonds2isplaced atop pa sepments 44,46, and S0andatopofantfse pad 8, using odingcapllay The force from the boning eapillary is sulicint to squish an {use pad 48 and a portion ofthe pod. segments, The force causes deformation of theantifasepatand the adjacent pad Sunes narowing intervening space 300 the point tbat a {otal shor oF ner short is rete btwn the pds. Ths, the antifse is programmed shoring the thre pad segments tothe ant-Risepad. The square shape of ani-stose pad 48s efficient bond target forthe two ajacent octagonal shaped pod seaments 4 and 46 {0080} Vias 380,342, and 346 couple pod segments 5 aun 46 1 underlying fst layer metlization (at shows) as osded. Additional second layer metallizaon runners may be implemented to further couple sition cic (00S1] An application for the antfuse configuration of FIG. 4s shown in FIG. 6 [0052] Referring 10 FG. §, an antcfase configuration Jncorporating an elongated pad segment song with multiple ante ods, i used © provide programming options for [o0s3} ppd segment 71, with intervening spaces $18, $20, and $22, respectively, there between. The pad segment and anti-fuse pads are formed on the top metallization layer ofa semicon- ductor wafer. Altematively, pad segment and ani-fuse pads ‘are formecionthe top metallization ayerof, but not limited 0, Aaticfuse pads $24, 526, and 528, are surrounded by ‘printed circuit board, or a ceramic substrate device. [0084] Pad segment 71 is coupled to capacitor 00, through via 10 and intervening first layer metallization (not shown), ‘and Further coupled to Cirewit K S08. Anise pad $24 is ‘couple to eapacitor $01 through via $12 and intervening first layer metallization (aot shown). Likewise, ant-fuse pads $26 and 528 are conple to capacitors 502 and 50S throu Vias ‘4 and $16 respectively and comesponding intervening first Jayer metallization (not shown), The capacitors are further ‘cupled to outpost terminal 350, [0085] For the example of FIG. S, itis desired to program capacitors S01 and S02 in parallel configuration with capacitor $00, Ball bond 74 is placed concurrently on ant {use pad $24, pad segment 71 and intervening space 818, and second ball bond 73 is placed concurrently on anise pad 526, pad segment 71 and intervening space $20, The capillary pressure exerted on the ball bonds, ring the bonding pro- fess, causes the respective aatifine pads to be squished ‘thereby shorting the spective ant-fuse pads to the pad seg. ‘ment. Thus the programming function fr the eapacitors is completed. Alternatively, passive citcuit elements, res tors and inductors: active circuit elements, eg transistors and diodes; and electronic circuits may be programmed in a ‘manner similar to that ofthe capacitors. [056] sone skilled inthe art would recognize, additional vias may be incomporated in pad segment 71 to provide addi- ‘ional interconnects to the first metallization layer. For US 2012/0061796 AI ‘example, Circuit K $08 is coupled to pad segment 71 through via 72. Likewise, additonal metal runners may be added to the pad segment to provide luther interconnect 10 second layer metallization, [0087] FIG. 6 shows an implementation of the ant-fuse ‘configuration of FIG, 4 rim an indict. The application is relative to, for example but not limite to tuning circuitry. 10058] An on-chip inductor is formed with a high perme- ability mapneti core looped by coils, ie, windings, formed by a combination of thick poser metal rannes located under- neath the magnetic core and coupled to wire loops formed ‘over the magnetic core 10089] Magnetic core 91 having aperture 92 is mounted ‘atop a substrate. The substrate (nol shown) is configured for Jabrieation of integrated or mounted components, both active ‘and passive. The substrate is, but is no Timited to, silicon, IAs, other compound semiconductors, printod circuit boards, ex, ibergass, LTCC, ceramic, glass, and flexible 10060] ‘The substrate has a frst metallization layer (not shown) wsed for interconnect of respective eieuity attached wo the substrate [0061] In FIG. 6, metallization under-loop portions 81, 1689, 691, 693, bond-pad pad seuments and primary bond- pads 83, 683, 685, 687 are formed in sean layer metaliza- tion usinga thick malleable power metal Likewise, bond-pad pad segment 86, 88, 90, 94, 82. 80, 681, pad seuments 692, 694, and ani-fise pads 698,697 are ulso formed inthe second metallization layer. Primary bond-pads, fabricated with sec- fond layer power metal metallization, ane coupled to the respective second layer metallization unde-loop portions. Bond wires, e., 88, 81, 901, and 84 couple the respective bond pad segments to the primary pads to complete the upper Joops forthe inductor For example, under-1oxp portions 689, pads 88 and 688, coupled to wire bond 881 completes one ‘urn, ie. one loop of te inductor of FIG. 6, 10062] "The use of power metal for pad segments, and anti fase pad, permits wire bonding ofboth primary and second- ily over active cireuits. The thick malleable ‘also Forms the lowest resistance stroctues, thus induetor and enhancing Q. 0063) the loops ofthe inductor to fist layer metallization and wo the associated electrical components, both active and passive. The completed inductor structure terminals reside between bond-pod pad segment 86 and bond-pad pad segment 681 Yi e680 and 682 provide path for souptng 10064} To program an antifuse in FIG. 6, a ball-bond is placed concurently over the designated unti-fise pad, dhe Felated pad segments, and the related intervening spaces. The result is decrease in indictance duc to shorting of adjacent ‘wire loops. Bonding to an anti-use structure has same effect ‘eliminating one inductor ten and therehy trims the ind tance valve. Ball bonding is particularly suitable for square shaped pads [0065] For example, in FIG. 6, two loops are shorted. Anti fise pad 695 is adjacently surrounded by pact segment 694 bond-pod pad seument 86, and bond-pad pad segment 88 with intervening space 696 there between, Ball-bond 87 is placed ‘concurrently over the anicfuse structure shorting out the ‘associated wire loop containing metallization under-loop 6689, bond pads 683 and 86 and bond wire 88. 0066] To program the second loop asa short, Js placed concurrently atop anti-fuse pad 697, Mar. 15, 2012 SEEM bowl mdr scan 9a 698, shorting the wire loop contain Joop 681, bond pads 68S and 88 and bond vie 881, Ths 60 ‘ums have been effectively trimmed off from the inductor structure of FIG. 6 [0067] Alternatively, the secondary bond pad 94 can also serves a primary bal bond pad ta implement an inductance {ap point, for example, to provide a voltage rato (step-down) {roma vollageapplied across bond-pad pad segments 681 and 86, The tp point may also be used a an input vo the inductor to provide a stepped-up vollage from the ap point applied voltage to bond:pad pad segments 681 and 86. Thus, the pplication has relevance i power supply ccc. [0068] Thus it can now be appreciated that the present invention provides a process nx! method for fabricating a novel programmable anti-fuse structure by utilizing a thick ‘malleable metallization layer to pattern an anti-fuse pad sur- rounded by or partially adjacent to a pad segment with an intervening space there between, The capillary pressure ‘exerted on ball bond placed atop the ant-fise pad, the inter ‘ening space, anda portion of the pad segment causes the all bond, the antifise pad, and a portion of the pad segment to {deform and provide highly reliable electrical total shor, or near short, between the anti-fuse pod and the pad segment thus programming the ant-fuse and corresponding coupled clemeats [0069] Iran be futher appreciated thatthe programmable Antisfoseconfiguratonof the presen invention ineoeporates a Sinle elongated pad sepmeat to provide area efficent oppor tunities for placement of multiple anti-fuse programming pds, thus conserving valuable circuit layout real estate when compared to multiple programming pals required by the present at, [0070] Itcan be even farther appreciated thatthe elongated Aantisfise configuration of the present invention provides perimeter saving space when incorporated in a semiconduc- {or device or on an altemative substrate, [0071] 1c can be even more so appreciated that the thick ‘malleable metallization charaterstics ofthe ant-fuse ofthe ‘present invention permit placement of the anise eoatign- ‘nition atop active and passive cree. [0072] I¢-can be sill further appreciated that the anti-fuse ‘configuration of the present invention provides lexbiity of pad area for probing before and after the trim operation [0073] Itean also he appreciato that the flexibility of th fant-fise pad of the present invention provides unlimited polygon type shapes 10 accommodate various pad segment programming option arrangements, [0074] It can also be more appreciated that the present invention is applicable to fabrication on varying types of substrates, eg. printed circuit board materials, and ceramics. [0075] In the foregoing specification, the invention has ‘been described with reference to specific embodiments and to specif materials and (0 specific process steps. It is reog- sized tht more steps are required W form a complete man ‘acturing los and method, These steps are known to skilled artisans and therefore are not reference in arr to simplify the drawings. Variation in process flow is possible and stil achieves similar results, [0076] Likewise, skilled artisans appreciate that elements in the figures are ilusrated for simplicity and have not been drawn to seal. The size of anti-fse metal pads ad interven- ‘ng spacing are dependent on pad metal thickness, pad mate- Fal, operating Vollage and bond wire parameters. Metal pad US 2012/0061796 AI shapes.¢ . circular or other polygon shapes canbe designed tnd sil function as antiefse pad configurations [0077] While specific emboxtiments of the present inven- tion have been shown and described, Turher modifications ‘and improvements will oecur to those skilled in the at es understood tat the invention is not Himited to the parcular forms shown, and it is intended fr the appended claims Tela 1. An antifuse apparatus comprising a subsieate, ‘ananti-fuse pa located partially adjacent toa pad segment ‘wih @ predetermined intervening space located there ‘between, and configured fora concurrent placementof'a ‘ond to program the anifuse apparatus, ‘wherein Said anti-fase pad, said pad segment, and said predetermined intervening space are located above Said substate, ‘wherein said antifuse pad and said pad segment are construc! from a thick metal having malleable properties «first circuit element coupled to said anti-fuse pa and ‘ second circuit element coupled to said pad segment. 2. The ant-fase apparatus of claim 1, wherein sai thick metal is of gold composition 3 The anticuse apparatus of claims 1, wherein said inter vening space is predetermined to ereate a near short upar pplication of sad bond. 4, The anti-luse apparatus of elsim 1, wherein suid subs strate isa semiconductor substrate. 8, The ant-fuse apparatus of elsim 1, further comprising imervening layers between said ant-fase apparatus and sad substrate, 6, The antisfuse apparatus of elaim 1, wherein said sab- strate is configured for forming inteprated components 7. The antifuse apparatus of claim 1, wherein said sub- strate isa printed eiruit board ', The aatifuse apparatus of claim 1, wherein suid sub- strate is configured for mounting eleetronie component. 9. The anti-fuse apparatus of claim 1, wherein said fist

    You might also like