TSMC: Advanced Design for

Low Power at 65nm and Below

TSMC: Advanced Design for Low Power

at 65nm and Below
By L.C. Lu, Deputy Director of the Design Methodology Program at TSMC, and
David Lan, Senior Manager in design methodology at TSMC North America.
Several drivers create the need for low power today. These include advanced
processes at 65nm and below, which, although they enable SoC designs with much
more complexity, consume more power. Mobile devices also require low-power
chips to extend the battery life in order to compete in the market place and also to
reduce overall system cost, which includes packaging costs To achieve low-power,
design for power has to be a goal from the start.
Today, low-power design demands the best efforts of the design and manufacturing
ecosystem, including:

Process optimization
Low-power design techniques
CPF standard support throughout tools flow
Libraries and IP
Reference design flow (RDF) as exemplified in the TSMC 9.0 RDF

To meet customers demands in low power, TSMC optimizes its process technology
for low-power designs. Nevertheless, at todays extremely small feature sizes,
dynamic and leakage power issues remain.
This means techniques for mitigating power consumption must come from the
design side.
For foundry customers power-sensitive 65nm or 45nm designs, it is critical to fully
leverage TSMC processes with compatible, power-saving EDA tool flows. TSMC
already brings to bear low-power methodologies and IP aimed at reducing dynamic,
active, and standby power leakage. All of these low-power methodologies require
fully automated EDA support, as shown below.
Low-Power Automation Power Format
Adaptive Voltage
Scaling (AVS)

Source + Back Bias

Coarse-Grain Power
Gating with Lower Vdd

Dual Power SRAM

Longer Channel
in Non-Critical Paths

Coarse-Grain
Data Retention

Dynamic Voltage
Freq. Scaling (DVFS)

Voltage Scaling

Coarse-Grain
Power Gating

Voltage Island

Back Bias

Fine-Grain
Power Gating

Clock Gating

Muti-Vt Device

Power Shutdown

Dynamic Power

Active Leakage

Standby Leakage

Low-Power Methodologies

Low-Power
Lib

Low-Power
SRAM

Low-Power Process

Figure 142. TSMC integrated low-power solution

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TSMC: Advanced Design for Low-Power at 65nm and Below

TSMC 65nm Low-Power Process

Today, the 65nm TSMC process includes:

Multi-Vt cells
New gate oxide material
Low K interconnect, including ELK, ULK
Strained engineering

However, the low-power challenge requires more than just process support.

Low-Power Design Techniques

TSMC customers utilize the full gamut of power reduction techniques, and TSMC
has expanded support for these approaches, culminating in the new Reference
Design Flow 9.0 (RDF 9.0):
For dynamic power: clock gating, multiple-voltage domains, dynamic voltage
and frequency scaling, hierarchical voltage with dual power SRAM, and adaptive
voltage scaling
For active leakage power: multi-Vt, back-biasing, voltage scaling, and source-and
back-biasing
For standby leakage power: fine- and coarse-grain power gating, power shut-off,
and data retention

CPF: The Low-Power Standard

TSMC and Cadence have collaborated on low-power since early 2004. In 2006, TSMC
was a founding member of the Si2 Low Power Coalition and the Power Forward
Initiative, recognizing that another key requirement is that design tools in the
methodology communicate low-power design intent in a single, standard format.
The Si2 Common Power Format (CPF), the first low-power EDA format embraced
by TSMC for 65nm low-power design, enables this capability.

The Need for CPF

What are the challenges of design-based solutions? Who are the stakeholders?
Management, the design team, the verification team, and the implementation team
all depend on low-power design efficiencies for productivity and success.
For management:
Increases schedule risk
Increases risk of failure
Increases silicon cost
For the design team:
Greatly increases complexity of quality-of-silicon (QoS) tradeoffs to explore
Isolation and retention add complexity to design
Introduces architecture modeling challenges
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TSMC: Advanced Design for Low-Power at 65nm and Below

For the verification team:

More functionality to verify

How is the functionality specified?
How will changes be communicated?
Now need to verify power structure implementation

For the implementation team:

Adds complexity to floorplanning, power planning, placement, clock tree synthesis,

and routing
Increases difficulty of timing closure
Increases design-for-test difficulty
Management
Design
Team

Verification
Team
Implementation
Team

Figure 143. Design-based solutions affect everyone

CPF Capabilities
The Common Power Format (CPF) is a single specification of power intent used
throughout design, verification, and implementation.
Common Power Format (CPF) is an ASCII File that captures:
Power design intent
Power domain
Logical: hierarchical modules
as domain members
Physical: power/ground nets
and connectivity
Analysis view: timing library
sets for power domains

Power logic
Level shifter logic
Isolation logic
State-retention logic
Switch logic & Control signals

Power modes
Definitions
Transition expressions
Modal analysis

Technology information
Level shifter cells
Isolation cells
State-retention cells
Switch cells
Always-on cells

Figure 144. CPF enables low-power automation

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TSMC: Advanced Design for Low-Power at 65nm and Below

TSMC has taken a leadership role in ensuring that the rich variety of power
reduction techniques automated by CPF result in verifiable improvements to
65nm designs. The following section describes an early program to validate the
Common Power Format for use with TSMC technology.

The TSMC Proof-Point Project

The proof-point project objectives included: [33]
Enhancing communications between logic design and physical design teams
Achieving synergy between TSMC low-power IP and EDA tools for implementing
power gating and power shut-off
Validating advanced design techniques in silicon using a CPF-based EDA tool flow
Verifying functionality and timing results for advanced techniques
Improving verification technologies
Looking for opportunities for further automation
In any design project, if the design intent is clearly specified, it unifies the design
team. CPF provides a single file with standard definitions of power intent, allowing
designers and design tools to utilize a common data set throughout the design flow.
To help drive CPF-awareness into a low-power methodology, TSMC undertook a
verification project and defined the techniques which would be used, as shown in
Figure 145.

Figure 145. TSMCs low-power test run

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TSMC: Advanced Design for Low-Power at 65nm and Below

The baseline for the project was a comparison to previous design techniques, without
CPF support. Simpler, earlier, power-reduction design techniques (area optimization
and clock gating) had little functionality and timing impact, but also contributed
little reduction in power. More advanced techniques now being applied, such as
power gating, were expected to impact functional and timing verification, as well
as dramatically reducing power, so this project was developed to measure power
reduction, gauge the complexity impact of advanced power gating, and work to
minimize that impact.

TSMC Proof-Point Design

TSMC used a large system-on-chip design block, with more than 100,000 instances,
50 (RAM) blocks, and more than 100,000 nets. [33]
In the design flow, TSMC used CPF-enabled EDA tools and focused on power
gating as the key power reduction design technique to best evaluate the full benefit
of the technique.
Power gating involves switching off the power to blocks of the circuit when those
portions are idle, and signal isolation, so that powered-down blocks do not pose
unintended loads on other active portions. When used together, power switching
and signal isolation can impact SoC timing, and even functionality if blocks are
switched on or off improperly.
The proof-point project comprised:

500K gate block

52 RAM blocks
Power gating implementation and verification
Auto switch and isolation cell insertion
Automatic power grid connection
Simulation verification for power gating
Formal verification

IP Usage in the TSMC Proof-Point Project

The project used a TSMC 65LP library, including special low-power IP, which is
a requirement for power-gated low-power design. This IP included specialized
power-gating cells to allow both column-style power gating and ring-type power
gating. The specialized power switches automatically eliminate power-up glitches
and electromigration, through dual control and a dual-switch structure.
An important part of the project was to validate that the CPF-enabled EDA flow took
proper advantage of these IP elements. With Cadence CPF-enabled technologies,
TSMC captured the proof-point design and proceeded through the design and
implementation flow shown in Figure 146.

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TSMC: Advanced Design for Low-Power at 65nm and Below

Figure 146. Flow of automation from RTL to GDS [33]

With this powerful CPF-based flow, the design was automatically augmented with
power switches and isolation cells to accomplish power gating. RTL synthesis used
power-gating auto-switching inserted as a checkerboard or surrounding floorplan
(Figure 147). RTL simulation verified power gating and retention flip-flop behavior.
Then, gate-level simulation of power shutdown was done under power-mode
transition and unknown propagation. Unknown signal generation and propagation
was done automatically in the CPF environment without Verilog model changes in
the library.

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TSMC: Advanced Design for Low-Power at 65nm and Below

Figure 147. Power-gating inserted surrounding the floorplan [Ref. 33]

Cadence Encounter Conformal Equivalence Checker and Conformal Low Power

were used to formally verify the auto-control signal setting for the switches and
isolation cells, as well as the actual power/ground connection to the network. Before
CPF, designers would have needed to manually check the connections and generate
large amounts of verification testbenches to check for functional correctness. These
are all error-prone activities. The use of automated formal verification from design
intent, through RTL and final implementation, is one of the visible benefits of CPF
as used throughout this flow.

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TSMC: Advanced Design for Low-Power at 65nm and Below

Results of the Proof-Point Project

When comparing a baseline project, utilizing low-power design techniqueswhich
did not use CPFwith a CPF-based EDA tool flow, clear benefits were realized.
Notable benefits included:
The design was completed faster
The design required fewer iterations
Design intent was consistent throughout the flow, so the integrity of the power
gating structure was preserved throughout the design
Automated power gating achieved 40x leakage power reduction
CPF-based automation was successful, created no functional nor timing failures,
and lead to no area inefficiencies.
The pilot project also revealed a variety of additional opportunities to enhance
low-power design techniques through the use of a CPF-based format. This work is
already under way in ongoing projects between TSMC and Cadence.
Enjoying success in this first proof-point project, the two companies set to work to
refine and integrate IP design using the Common Power Format. In addition, TSMC
was able to validate CPF support for TSMC Reference Flow 9.0.

CPF-Based TSMC Reference Flow 9.0

The TSMC Reference Flow 9.0 was announced in June 2007. This flow supports CPF
tools for 65nm and 45nm process technologies.

Figure 148. TSMC Reference Flow 9.0: complete CPF integration [Ref. 34]
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TSMC: Advanced Design for Low-Power at 65nm and Below

This 9.0 flow solves critical problems since it is based on CPF. The details of the
Cadence technologies involved in this flow are as follows:
Pervasive CPF
CPF Quality Check
Encounter Conformal Low Power

Verification of virtual LP logic: Linting, consistency, functional, structural checks

Functional Simulation
Incisive Design Team Simulator
Incisive Design Team Manager

Functional validation of virtual LP behavior and PSO: State loss, isolation, SRPG
Auto generation of PSO mode coverage.

Logic Synthesis and DFT

Encounter RTL Compiler

Power domain, multi mode, DVFS aware synthesis and power analysis. Auto
insertion, mapping and optimization of iso, LS, SRPG. Power domain aware test
synthesis, insertion of iso/LS on DFT nets.

LEC + Power Checks

Encounter Conformal Low Power

RTL2Gate logic equivalence checks (incl. LP cells).

Structural, property, and functional checks for LP logic.

Logic Simulation
Incisive Design Team Simulator

Functional validation of LP logic behavior and PSO: state loss, isolation, SRPG

Physical Implementation
SoC Encounter System

Power domain/mode aware P&R, w/o dont_touch

Power switch insertion and optimization. LS and clamp optimization. DVFS and
MMMC support.

LEC + Power Checks

Encounter Conformal Low Power

Gate2Gate logic equivalence checks. Structural, property, and functional checks

For LP logic.

ATPG
Encounter Test

Automatic mapping of power-modes (from CPF) into test-modes

Fault model/coverage of low power structures, SRPG (excluding power switches).

Timing & SI Signoff

Encounter Timing System
IR Drop and Power Signoff
VoltageStorm Dynamic Gate Option

Power domain/mode aware delay calculation, including DVFS, MMMC support.

Power domain/mode aware IR drop analysis (static and dynamic).
Power-up analysis of power switches and impact on neighbors.

Figure 149. CPF flow: Supported tool functionality

Sample Design Information from CPF

This multi-supply voltage (MSV) design (see Figure 150) contains a DMA block and
a DMA bridge, with two MACs that are based on identical RTL but have different
power behavior.
Three power domains and four power modes are specified, as shown in the figure
below. The power modes, the state behavior, the isolation cells, and state retention
all conspire to pose a significant challenge!

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TSMC: Advanced Design for Low-Power at 65nm and Below

RTL Design

DMA and DMA Bridge

Two MACs w/ identical RTL

VDD (1V)

VDDM (0.84V)

Define power domains

PDCore
PDMac1
PDMac2

Switch
VDDau

Phys I

Define state retention

MAC1 optimized
MAC2 stores all regs

MAC I
(0.84V)

Switch
VDDlu

Phys II

DMA Bridge

PCM

AHMB

Define power controls

Define isolation logic
Power modes:

DMA

Mode #

Mac 1

Mac 2

ON

OFF

OFF

ON

OFF

OFF

ON

ON

MAC II
(0.84V)

Technology data

Retention registers
Enabled level shifters (level shifter w/isolation)

Library cells
Operating conditions

Requires functional verification!

Figure 150. MSV design example

Functional and Logic Simulation

Ad-hoc power management verification is very risky, impacting productivity because
manual intervention is required to model power management, and there are many
files and changes to maintain. Quality is at risk, because there is no guarantee that
what is verified is what is actually implemented. Schedule predictability also suffers,
because power-related errors may be discovered late.

Modify testbench to simulate

power shut-off
Modify RTL to instantiate
low-power models
Create custom PLI to model
low-power operation
Create custom libraries to support
low-power models

Figure 151. Ad-hoc verification steps

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TSMC: Advanced Design for Low-Power at 65nm and Below

But with the CPF-enabled flow, verification benefits are realized, including improved
productivity, with no impact to existing verification methodology, no golden design
file changes, no custom library development, and no PLI development. It also results
in enhanced quality, because what designers verify is what they actually design.
Better schedule predictability is achieved, because power issues are detected early.
The bottom line is: reduced risk!

The ONLY power-aware

verification flow
RTL

CPF

Design Verification

Formal
Analysis

Simulation

Acceleration
and Emulation

Testbench Automation

Verification Coverage

Lint and Structural

Analysis

Figure 152. Incisive power management verification approach

Real customer design issues uncovered with the CPF-enabled verification flow have
included:
Cache memory in power down domain, where the processor running from cache
would lose program and hang. Simulations were used to determine cache and
power sequencing
Power-down caused a hang on the system bus due to isolation values. One
customer commented,We were worried something like that would happen
The restore from power-down was not clean; non-state retention flops needed a
reset or initialization signal
Power-up and isolation disable was happening at the same time, there was not
enough time for power to stabilize before enabling outputs
Incorrect design of the power control module created oscillations on control
signals in one mode
CPF automation identified these issues early to ensure design integrity.
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TSMC: Advanced Design for Low-Power at 65nm and Below

Logic Synthesis and DFT

The contributions of CPF in the logic synthesis and DFP stages of design included:
Multi-objective synthesis structures logic for timing, power, and area
simultaneously. This is the only way to close on multiple orthogonal objectives.
Also, better logic structure delivers superior quality of silicon through physical
implementation
Top-down multi-power domain synthesis optimizes across power domains,
including isolation and level shifter latency. Supports fast what-if exploration of
MSV and PSO scenarios, power mode-aware power exploration, and is key to
achieving optimal power/timing balance
Clock Period
Encounter RTL
Compiler = 5% faster

Die Size
RTL Compiler =
12% smaller
RTL Compiler =
45% cooler

Leakage Power

Lib1 Lib2
0.8V 1.0V Lib3
1.2V

RTL

Top

Chip
CPF

Chip
SDC

PSO
C
B

Too slow?

Isolation

Too hot?

Figure 153. Encounter RTL Compiler: Multi-objective, multi-voltage RTL synthesis

Logic Equivalence Checking (LEC) and Power Checks

CPF quality checking helps eliminate errors in the CPF. Three critical areas for
checking include:
Logic equivalence checking (LEC) ensures that low-power optimizations do not
introduce logical errors; enables true EC leveraging CPF; checks state retention
mapping from RTL to gate; checks corresponding presence of isolation and level
shifter during implementation; and checks power domain boundaries
Functional and structural checks ensure proper insertion of low-power cells and
proper connectivity of low-power cells, and formally validate isolation and state
retention functions. This runs at RTL design, both logical and physical netlist
leveraging CPF as the golden specification
Transistor-level checks check domain boundaries for un-buffered inputs (sneak paths)
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TSMC: Advanced Design for Low-Power at 65nm and Below

Figure 154. Encounter Conformal Low Power: Independent low-power implementation verification

Automatic Test Pattern Generation (ATPG)

Automatic test pattern generation (ATPG) is challenging for designs with advanced
power management techniques. With the TSMC RDF 9.0:
Domain-aware scan testing recognizes power domains and enables a full scan
test even when a module is shut down
ATPG test coverage for low-power structures
Power-aware ATPG minimizes power during test mode by intelligent fill of test
patterns
Excessive power
consumption during
scan testing
Low-power scan
vectors manage power
during scan test

Mode

Clock
(MHz)

% Switching

Switch power
(mW)

Normal operation

500

10~20

2.96

Scan test

50

46

11.86

Low-power
50
6
scan test
Nano CPU, 35K instances, 9K registers

Figure 155. Encounter Test: Unique power-aware test solution

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1.66

TSMC: Advanced Design for Low-Power at 65nm and Below

Physical Implementation
Physical implementation with CPF supports multi-supply voltage designs, with
automated insertion of low-power elements and concurrent optimization of multiple
power domains.

1.2V

1.0V

0.9V

Level shifters
included

module (top):
module (A):

module (B):

Physical synthesis
Level shifters placed concurrently
during physical synthesis

Single pass top-down MSV, multi-mode synthesis

0.9V
1.2V

1.2V
0.9V

Clock tree synthesis

1.2V

0.9V

ONE
block

ONE tree

MSV
physical synthesis
Concurrent
optimization of 0.9V
and 1.2V domains

Figure 156. SoC Encounter RTL-to-GDSII System: Automation for multiple power domains

Timing and SI Signoff

In the TSMC RDF 9.0, timing and signal integrity (SI) signoff with CPF feature
complete signoff static timing analysis, built from production-proven products such

as Cadence CTE, CeltIC Signal Integrity Analysis, and SignalStorm Nanometer

Delay Calculator (NDC), plus silicon validation and support from foundry and
IP/library vendors.
Advanced timing debug speeds analysis, increasing productivity, and supports
standard interfaces. The flow can be tcl- or GUI-driven, and supports timing debug,
interactive queries, tcl API, and histograms.

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TSMC: Advanced Design for Low-Power at 65nm and Below

SDC

.lib

Netlist CPF
SPEF/
SDF/
WLM

Encounter Timing
System

ECSM

DEF

cdB

SDF

Paths

DRVs

Optional

Figure 157. Encounter Timing System

IR Drop and Power Signoff

In the TSMC Cadence RDF 9.0 flow, IR drop and power signoff capabilities include
static and dynamic power rail verification, based on patented power consumption
algorithms, and power rail verification for IR drop and electromigration. Cadence

VoltageStorm Power Verification supports both vectorless and vector-driven

analysis modes. It provides comprehensive low-power support for MSMV, power
switches, and power-up. IR drop and power signoff is integrated with Cadence
Encounter platform techonologies for automatic de-coupling capacitance
optimization; with CeltIC NDC to determine the impact of IR drop on timing and

noise; and with Cadence Allegro Package Designer to easily determine the impact
of package loading on IR drop.

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TSMC: Advanced Design for Low-Power at 65nm and Below

Encounter
platform

Allegro
Package
Designer

DEF
GDSII
OA

VoltageStorm DG
RC extraction engine
PowerMeter
power calculation

Power grid
view library

Static and dynamic

rail analysis

Encounter
Timing
System

Figure 158. VoltageStorm dynamic power analysis

SoC Encounter System

Placed and Routed Design

Database
Edit Power-Pad
Location
CPF Mode
Specification

Power
Libraries

Plots

Report Power
(Common Power Engine)

Static and Dynamic

IR-Drop Analysis

Power-Switch
ECO

Waveforms and IR Drop Files

Decap
ECO

Timing and Critical

Path Analysis
(Encounter
Timing System)

Figure 159. SoC Encounter System: VoltageStorm flow

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TSMC: Advanced Design for Low-Power at 65nm and Below

The following diagram shows the power switch insertion and optimization flow,
with power, current, and IR drop reporting.
ram2
PD1
PLL

SoC Encounter
System

ram1
PD1

addPowerSwitch

runVSDG
DEF

SOC
TWF, VCD

VoltageStorm
optPowerSwitch

RC Extraction Engine
Power Grid
View Library

Power Calculation
Rail Analysis

Power Switch
Current and
IR-DropReport

Figure 160. Power switch optimization flow

The following diagram describes how power-up modes and sequencing are analysed,
starting with creation of the circuit netlist, simulation, creation of dynamic power
grid views, and analysis and viewing capabilities.
PowerMeter

UltraSim

VoltageStorm
(Power Meter)

VDD

Top Level
Circuit File

Control

Logic

Circuit
Netlist

1. Create circuit netlist

UltraSim

Inputs
clamped

Circuit
Netlist

Outputs
correctly
loaded

2. Simulate with Virtuoso UltraSim

Full-Chip Simulator
VDD

VoltageStorm DG

RC Grid

Signal
Loading

Netlist

Sleep ctrl
RC Network

Template
Stimulus

Voltage
Sources

UltraSim
Circuit
Netlist

Capture dynamic
current in PGV

3. Create dynamic power grid views

Load full-chip power RC network

with PGVs and analyze
4. Analyze in VoltageStorm DG

Figure 161. Powerup flow

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Spice
Waveforms
and Results

Power-Transistor
Dynamic
Currents (ptl)

TSMC: Advanced Design for Low-Power at 65nm and Below

The de-coupling capacitor, or decap, insertion and optimization can ensure power
grid integrity while preventing excess power dissipation. Intelligent insertion of
decaps is increasingly critical for small geometry processes due to leakage concerns.
The following flow shows the process of decap insertion in the Cadence TSMC
Reference Design Flow 9.0.
* Decaps are Placed where Most Effective
Area Based Decap Opt Flow

Rule-Based De-Cap and Filter Cells Insertion

Featibility Serve Decap Opt Flow

Decap Added Anywhere

in the Region

Dynamic IR Drop Analysis

Filter Cell Swapped with Decap

ECO
Placement-Aware De-Cap Analysis
Cell with no IR Drop

ECO File for SoC Encounter

Voltage Storm

Cell with High IR Drop

Congested Design with High IR Drop

Decap Cell

Components are Missed to Make

Roam for Filters (Decaps)

Run ECO in SoC Encounter System

DEF

Figure 162. Decap optimization flow

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TSMC: Advanced Design for Low-Power at 65nm and Below

So, in summary, as we have seen, the TSMC RDF 9.0 flow supports all the key power
management techniques in an automated fashion through CPF.
Isolation,
SRPG,
state loss
CPF

RTL

CPF quality check

MSMV,
MM,
DVFS,
SRPG

RTL simulation
MSMV, SRPG, PSO,
MMMC, DVFS, alwayson buffers
MSMV, MMMC, DVFS,
power switch, always-on
buffers

Logic synthesis and DFT

Gate netlist

LEC and power checks

Isolation,
SRPG,
state loss

Logic simulation
Physical implementation

Physical
netlist

LEC and power checks

ATPG
Timing and SI signoff

Auto map
of power
modes to
test modes

IR drop and power signoff

Figure 163. CPF-based tool flow for TSMC 9.0

TSMC Low-Power Library: CPF Compliant

TSMC has developed low-power libraries that support all of the low-power
management techniques enabled by the CPF flow. These include:
Dual power SRAM (45nm)
Voltage island support elements
Level shifters
Enabled level shifters for shutdown domain
Different voltage library
Back bias library
Power-gating power switches
Footer, header support
Isolation cells (ISO-0, ISO-1, ISO-retention)
Always-on switches for feed-through
Retention flip-flops

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TSMC: Advanced Design for Low-Power at 65nm and Below

In addition, TSMC and Cadence have embarked upon numerous CPF-based

low-power follow-on projects. These projects focus on complex low-power design
techniques such as hierarchical voltage islands, adaptive-voltage scaling, and power
gating with data retention, as well as support for TSMCs new 45nm processes.

Summary
Since 2004, TSMC and Cadence have enjoyed a history of low-power collaboration,
and have made significant efforts in developing the CPF standard.
Common Power Format flow automation delivers up to 2x productivity improvement
over previous methods. CPF facilitates power reduction benefits from a wide variety
of power management techniques:
For dynamic power: clock gating, multiple-voltage domains, dynamic voltage
and frequency scaling, hierarchical voltage with dual power SRAM, and adaptive
voltage scaling
For active leakage power: multi-Vt, back-biasing, voltage scaling, and source- and
back-biasing
For standby leakage power: fine- and coarse-grain power gating, power shutoff, and data retention
TSMC and Cadence continue to work together to deliver advanced low-power
design capabilities to joint customers in two key ways:
Customers are supported through the TSMC Reference Flow
TSMC libraries enable advanced low-power design techniques used in the
CPF-based flow
Together, TSMC and Cadence offer the first complete low-power solution: technology,
combined with methodology, enabled by CPF.

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TSMC: Advanced Design for Low-Power at 65nm and Below

Technology + CPF + Methodology

Holistic Solution!
Power Planning and Metrics

Achieve optimal
timing/area/power balance
Reduced failure risk
Schedule predictability

Cadence Logic Design Team Solution

Design

Verification

Cadence
Low-Power
Solution
CPF Enabled

Quick what-if exploration of QoS tradeoffs

Synthesize w/ power structures better netlist for implementation

Cadence Digital
Implementation
Solution

Functional
Verify what is designed
Track functional coverage of power modes

Implementation
Verify what is implemented
Verify retention/isolation cell functionality

Implementation
Native power domain infrastructure eases implementation complexity
Automatic partitioning and scheduling of power domains for test

Figure 164. The first complete low-power solution

Dr. L.C. Lu is Deputy Director of the Design Methodology Program at TSMC. David Lan, Senior
Manager in design methodology at TSMC North America, has been responsible for providing
solutions in chip implementation, verification and DFM to TSMC customers. Prior to his current
position, he held management positions in various ASIC companies and fabless design companies
in CAD, chip integration and verification. He received his MS in computer engineering in 1987
from UC Santa Barbara.

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